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framebuffer: fix border color
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci.c
blob83b51b5a601d756561953e33c8f6f9834c161df1
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/sfi.h>
27 #include <linux/pm_runtime.h>
28
29 #include "sdhci.h"
30
31 /*
32 * PCI registers
33 */
34
35 #define PCI_SDHCI_IFPIO 0x00
36 #define PCI_SDHCI_IFDMA 0x01
37 #define PCI_SDHCI_IFVENDOR 0x02
38
39 #define PCI_SLOT_INFO 0x40 /* 8 bits */
40 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
41 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
42
43 #define MAX_SLOTS 8
44
45 struct sdhci_pci_chip;
46 struct sdhci_pci_slot;
47
48 struct sdhci_pci_fixes {
49 unsigned int quirks;
50 bool allow_runtime_pm;
51
52 int (*probe) (struct sdhci_pci_chip *);
53
54 int (*probe_slot) (struct sdhci_pci_slot *);
55 void (*remove_slot) (struct sdhci_pci_slot *, int);
56
57 int (*suspend) (struct sdhci_pci_chip *);
58 int (*resume) (struct sdhci_pci_chip *);
59 };
60
61 struct sdhci_pci_slot {
62 struct sdhci_pci_chip *chip;
63 struct sdhci_host *host;
64
65 int pci_bar;
66 int rst_n_gpio;
67 int cd_gpio;
68 int cd_irq;
69 };
70
71 struct sdhci_pci_chip {
72 struct pci_dev *pdev;
73
74 unsigned int quirks;
75 bool allow_runtime_pm;
76 const struct sdhci_pci_fixes *fixes;
77
78 int num_slots; /* Slots on controller */
79 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
80 };
81
82
83 /*****************************************************************************\
84 * *
85 * Hardware specific quirk handling *
86 * *
87 \*****************************************************************************/
88
89 static int ricoh_probe(struct sdhci_pci_chip *chip)
90 {
91 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
92 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
93 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
94 return 0;
95 }
96
97 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
98 {
99 slot->host->caps =
100 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
101 & SDHCI_TIMEOUT_CLK_MASK) |
102
103 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
104 & SDHCI_CLOCK_BASE_MASK) |
105
106 SDHCI_TIMEOUT_CLK_UNIT |
107 SDHCI_CAN_VDD_330 |
108 SDHCI_CAN_DO_SDMA;
109 return 0;
110 }
111
112 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
113 {
114 /* Apply a delay to allow controller to settle */
115 /* Otherwise it becomes confused if card state changed
116 during suspend */
117 msleep(500);
118 return 0;
119 }
120
121 static const struct sdhci_pci_fixes sdhci_ricoh = {
122 .probe = ricoh_probe,
123 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
124 SDHCI_QUIRK_FORCE_DMA |
125 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
126 };
127
128 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
129 .probe_slot = ricoh_mmc_probe_slot,
130 .resume = ricoh_mmc_resume,
131 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
132 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
133 SDHCI_QUIRK_NO_CARD_NO_RESET |
134 SDHCI_QUIRK_MISSING_CAPS
135 };
136
137 static const struct sdhci_pci_fixes sdhci_ene_712 = {
138 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
139 SDHCI_QUIRK_BROKEN_DMA,
140 };
141
142 static const struct sdhci_pci_fixes sdhci_ene_714 = {
143 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
144 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
145 SDHCI_QUIRK_BROKEN_DMA,
146 };
147
148 static const struct sdhci_pci_fixes sdhci_cafe = {
149 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
150 SDHCI_QUIRK_NO_BUSY_IRQ |
151 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
152 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
153 };
154
155 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
156 {
157 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
158 return 0;
159 }
160
161 /*
162 * ADMA operation is disabled for Moorestown platform due to
163 * hardware bugs.
164 */
165 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
166 {
167 /*
168 * slots number is fixed here for MRST as SDIO3/5 are never used and
169 * have hardware bugs.
170 */
171 chip->num_slots = 1;
172 return 0;
173 }
174
175 /* Medfield eMMC hardware reset GPIOs */
176 static int mfd_emmc0_rst_gpio = -EINVAL;
177 static int mfd_emmc1_rst_gpio = -EINVAL;
178
179 static int mfd_emmc_gpio_parse(struct sfi_table_header *table)
180 {
181 struct sfi_table_simple *sb = (struct sfi_table_simple *)table;
182 struct sfi_gpio_table_entry *entry;
183 int i, num;
184
185 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
186 entry = (struct sfi_gpio_table_entry *)sb->pentry;
187
188 for (i = 0; i < num; i++, entry++) {
189 if (!strncmp(entry->pin_name, "emmc0_rst", SFI_NAME_LEN))
190 mfd_emmc0_rst_gpio = entry->pin_no;
191 else if (!strncmp(entry->pin_name, "emmc1_rst", SFI_NAME_LEN))
192 mfd_emmc1_rst_gpio = entry->pin_no;
193 }
194
195 return 0;
196 }
197
198 #ifdef CONFIG_PM_RUNTIME
199
200 static irqreturn_t mfd_sd_cd(int irq, void *dev_id)
201 {
202 struct sdhci_pci_slot *slot = dev_id;
203 struct sdhci_host *host = slot->host;
204
205 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
206 return IRQ_HANDLED;
207 }
208
209 #define MFLD_SD_CD_PIN 69
210
211 static int mfd_sd_probe_slot(struct sdhci_pci_slot *slot)
212 {
213 int err, irq, gpio = MFLD_SD_CD_PIN;
214
215 slot->cd_gpio = -EINVAL;
216 slot->cd_irq = -EINVAL;
217
218 err = gpio_request(gpio, "sd_cd");
219 if (err < 0)
220 goto out;
221
222 err = gpio_direction_input(gpio);
223 if (err < 0)
224 goto out_free;
225
226 irq = gpio_to_irq(gpio);
227 if (irq < 0)
228 goto out_free;
229
230 err = request_irq(irq, mfd_sd_cd, IRQF_TRIGGER_RISING |
231 IRQF_TRIGGER_FALLING, "sd_cd", slot);
232 if (err)
233 goto out_free;
234
235 slot->cd_gpio = gpio;
236 slot->cd_irq = irq;
237 slot->host->quirks2 |= SDHCI_QUIRK2_OWN_CARD_DETECTION;
238
239 return 0;
240
241 out_free:
242 gpio_free(gpio);
243 out:
244 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
245 return 0;
246 }
247
248 static void mfd_sd_remove_slot(struct sdhci_pci_slot *slot, int dead)
249 {
250 if (slot->cd_irq >= 0)
251 free_irq(slot->cd_irq, slot);
252 gpio_free(slot->cd_gpio);
253 }
254
255 #else
256
257 #define mfd_sd_probe_slot NULL
258 #define mfd_sd_remove_slot NULL
259
260 #endif
261
262 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
263 {
264 const char *name = NULL;
265 int gpio = -EINVAL;
266
267 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, mfd_emmc_gpio_parse);
268
269 switch (slot->chip->pdev->device) {
270 case PCI_DEVICE_ID_INTEL_MFD_EMMC0:
271 gpio = mfd_emmc0_rst_gpio;
272 name = "eMMC0_reset";
273 break;
274 case PCI_DEVICE_ID_INTEL_MFD_EMMC1:
275 gpio = mfd_emmc1_rst_gpio;
276 name = "eMMC1_reset";
277 break;
278 }
279
280 if (!gpio_request(gpio, name)) {
281 gpio_direction_output(gpio, 1);
282 slot->rst_n_gpio = gpio;
283 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
284 }
285
286 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
287
288 slot->host->mmc->caps2 = MMC_CAP2_BOOTPART_NOACC;
289
290 return 0;
291 }
292
293 static void mfd_emmc_remove_slot(struct sdhci_pci_slot *slot, int dead)
294 {
295 gpio_free(slot->rst_n_gpio);
296 }
297
298 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
299 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
300 .probe_slot = mrst_hc_probe_slot,
301 };
302
303 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
304 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
305 .probe = mrst_hc_probe,
306 };
307
308 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
309 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
310 .allow_runtime_pm = true,
311 .probe_slot = mfd_sd_probe_slot,
312 .remove_slot = mfd_sd_remove_slot,
313 };
314
315 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
316 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
317 .allow_runtime_pm = true,
318 };
319
320 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
321 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
322 .allow_runtime_pm = true,
323 .probe_slot = mfd_emmc_probe_slot,
324 .remove_slot = mfd_emmc_remove_slot,
325 };
326
327 /* O2Micro extra registers */
328 #define O2_SD_LOCK_WP 0xD3
329 #define O2_SD_MULTI_VCC3V 0xEE
330 #define O2_SD_CLKREQ 0xEC
331 #define O2_SD_CAPS 0xE0
332 #define O2_SD_ADMA1 0xE2
333 #define O2_SD_ADMA2 0xE7
334 #define O2_SD_INF_MOD 0xF1
335
336 static int o2_probe(struct sdhci_pci_chip *chip)
337 {
338 int ret;
339 u8 scratch;
340
341 switch (chip->pdev->device) {
342 case PCI_DEVICE_ID_O2_8220:
343 case PCI_DEVICE_ID_O2_8221:
344 case PCI_DEVICE_ID_O2_8320:
345 case PCI_DEVICE_ID_O2_8321:
346 /* This extra setup is required due to broken ADMA. */
347 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
348 if (ret)
349 return ret;
350 scratch &= 0x7f;
351 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
352
353 /* Set Multi 3 to VCC3V# */
354 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
355
356 /* Disable CLK_REQ# support after media DET */
357 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
358 if (ret)
359 return ret;
360 scratch |= 0x20;
361 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
362
363 /* Choose capabilities, enable SDMA. We have to write 0x01
364 * to the capabilities register first to unlock it.
365 */
366 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
367 if (ret)
368 return ret;
369 scratch |= 0x01;
370 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
371 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
372
373 /* Disable ADMA1/2 */
374 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
375 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
376
377 /* Disable the infinite transfer mode */
378 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
379 if (ret)
380 return ret;
381 scratch |= 0x08;
382 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
383
384 /* Lock WP */
385 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
386 if (ret)
387 return ret;
388 scratch |= 0x80;
389 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
390 }
391
392 return 0;
393 }
394
395 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
396 {
397 u8 scratch;
398 int ret;
399
400 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
401 if (ret)
402 return ret;
403
404 /*
405 * Turn PMOS on [bit 0], set over current detection to 2.4 V
406 * [bit 1:2] and enable over current debouncing [bit 6].
407 */
408 if (on)
409 scratch |= 0x47;
410 else
411 scratch &= ~0x47;
412
413 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
414 if (ret)
415 return ret;
416
417 return 0;
418 }
419
420 static int jmicron_probe(struct sdhci_pci_chip *chip)
421 {
422 int ret;
423 u16 mmcdev = 0;
424
425 if (chip->pdev->revision == 0) {
426 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
427 SDHCI_QUIRK_32BIT_DMA_SIZE |
428 SDHCI_QUIRK_32BIT_ADMA_SIZE |
429 SDHCI_QUIRK_RESET_AFTER_REQUEST |
430 SDHCI_QUIRK_BROKEN_SMALL_PIO;
431 }
432
433 /*
434 * JMicron chips can have two interfaces to the same hardware
435 * in order to work around limitations in Microsoft's driver.
436 * We need to make sure we only bind to one of them.
437 *
438 * This code assumes two things:
439 *
440 * 1. The PCI code adds subfunctions in order.
441 *
442 * 2. The MMC interface has a lower subfunction number
443 * than the SD interface.
444 */
445 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
446 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
447 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
448 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
449
450 if (mmcdev) {
451 struct pci_dev *sd_dev;
452
453 sd_dev = NULL;
454 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
455 mmcdev, sd_dev)) != NULL) {
456 if ((PCI_SLOT(chip->pdev->devfn) ==
457 PCI_SLOT(sd_dev->devfn)) &&
458 (chip->pdev->bus == sd_dev->bus))
459 break;
460 }
461
462 if (sd_dev) {
463 pci_dev_put(sd_dev);
464 dev_info(&chip->pdev->dev, "Refusing to bind to "
465 "secondary interface.\n");
466 return -ENODEV;
467 }
468 }
469
470 /*
471 * JMicron chips need a bit of a nudge to enable the power
472 * output pins.
473 */
474 ret = jmicron_pmos(chip, 1);
475 if (ret) {
476 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
477 return ret;
478 }
479
480 /* quirk for unsable RO-detection on JM388 chips */
481 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
482 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
483 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
484
485 return 0;
486 }
487
488 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
489 {
490 u8 scratch;
491
492 scratch = readb(host->ioaddr + 0xC0);
493
494 if (on)
495 scratch |= 0x01;
496 else
497 scratch &= ~0x01;
498
499 writeb(scratch, host->ioaddr + 0xC0);
500 }
501
502 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
503 {
504 if (slot->chip->pdev->revision == 0) {
505 u16 version;
506
507 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
508 version = (version & SDHCI_VENDOR_VER_MASK) >>
509 SDHCI_VENDOR_VER_SHIFT;
510
511 /*
512 * Older versions of the chip have lots of nasty glitches
513 * in the ADMA engine. It's best just to avoid it
514 * completely.
515 */
516 if (version < 0xAC)
517 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
518 }
519
520 /* JM388 MMC doesn't support 1.8V while SD supports it */
521 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
522 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
523 MMC_VDD_29_30 | MMC_VDD_30_31 |
524 MMC_VDD_165_195; /* allow 1.8V */
525 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
526 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
527 }
528
529 /*
530 * The secondary interface requires a bit set to get the
531 * interrupts.
532 */
533 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
534 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
535 jmicron_enable_mmc(slot->host, 1);
536
537 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
538
539 return 0;
540 }
541
542 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
543 {
544 if (dead)
545 return;
546
547 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
548 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
549 jmicron_enable_mmc(slot->host, 0);
550 }
551
552 static int jmicron_suspend(struct sdhci_pci_chip *chip)
553 {
554 int i;
555
556 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
557 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
558 for (i = 0; i < chip->num_slots; i++)
559 jmicron_enable_mmc(chip->slots[i]->host, 0);
560 }
561
562 return 0;
563 }
564
565 static int jmicron_resume(struct sdhci_pci_chip *chip)
566 {
567 int ret, i;
568
569 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
570 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
571 for (i = 0; i < chip->num_slots; i++)
572 jmicron_enable_mmc(chip->slots[i]->host, 1);
573 }
574
575 ret = jmicron_pmos(chip, 1);
576 if (ret) {
577 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
578 return ret;
579 }
580
581 return 0;
582 }
583
584 static const struct sdhci_pci_fixes sdhci_o2 = {
585 .probe = o2_probe,
586 };
587
588 static const struct sdhci_pci_fixes sdhci_jmicron = {
589 .probe = jmicron_probe,
590
591 .probe_slot = jmicron_probe_slot,
592 .remove_slot = jmicron_remove_slot,
593
594 .suspend = jmicron_suspend,
595 .resume = jmicron_resume,
596 };
597
598 /* SysKonnect CardBus2SDIO extra registers */
599 #define SYSKT_CTRL 0x200
600 #define SYSKT_RDFIFO_STAT 0x204
601 #define SYSKT_WRFIFO_STAT 0x208
602 #define SYSKT_POWER_DATA 0x20c
603 #define SYSKT_POWER_330 0xef
604 #define SYSKT_POWER_300 0xf8
605 #define SYSKT_POWER_184 0xcc
606 #define SYSKT_POWER_CMD 0x20d
607 #define SYSKT_POWER_START (1 << 7)
608 #define SYSKT_POWER_STATUS 0x20e
609 #define SYSKT_POWER_STATUS_OK (1 << 0)
610 #define SYSKT_BOARD_REV 0x210
611 #define SYSKT_CHIP_REV 0x211
612 #define SYSKT_CONF_DATA 0x212
613 #define SYSKT_CONF_DATA_1V8 (1 << 2)
614 #define SYSKT_CONF_DATA_2V5 (1 << 1)
615 #define SYSKT_CONF_DATA_3V3 (1 << 0)
616
617 static int syskt_probe(struct sdhci_pci_chip *chip)
618 {
619 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
620 chip->pdev->class &= ~0x0000FF;
621 chip->pdev->class |= PCI_SDHCI_IFDMA;
622 }
623 return 0;
624 }
625
626 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
627 {
628 int tm, ps;
629
630 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
631 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
632 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
633 "board rev %d.%d, chip rev %d.%d\n",
634 board_rev >> 4, board_rev & 0xf,
635 chip_rev >> 4, chip_rev & 0xf);
636 if (chip_rev >= 0x20)
637 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
638
639 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
640 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
641 udelay(50);
642 tm = 10; /* Wait max 1 ms */
643 do {
644 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
645 if (ps & SYSKT_POWER_STATUS_OK)
646 break;
647 udelay(100);
648 } while (--tm);
649 if (!tm) {
650 dev_err(&slot->chip->pdev->dev,
651 "power regulator never stabilized");
652 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
653 return -ENODEV;
654 }
655
656 return 0;
657 }
658
659 static const struct sdhci_pci_fixes sdhci_syskt = {
660 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
661 .probe = syskt_probe,
662 .probe_slot = syskt_probe_slot,
663 };
664
665 static int via_probe(struct sdhci_pci_chip *chip)
666 {
667 if (chip->pdev->revision == 0x10)
668 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
669
670 return 0;
671 }
672
673 static const struct sdhci_pci_fixes sdhci_via = {
674 .probe = via_probe,
675 };
676
677 static const struct pci_device_id pci_ids[] __devinitdata = {
678 {
679 .vendor = PCI_VENDOR_ID_RICOH,
680 .device = PCI_DEVICE_ID_RICOH_R5C822,
681 .subvendor = PCI_ANY_ID,
682 .subdevice = PCI_ANY_ID,
683 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
684 },
685
686 {
687 .vendor = PCI_VENDOR_ID_RICOH,
688 .device = 0x843,
689 .subvendor = PCI_ANY_ID,
690 .subdevice = PCI_ANY_ID,
691 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
692 },
693
694 {
695 .vendor = PCI_VENDOR_ID_RICOH,
696 .device = 0xe822,
697 .subvendor = PCI_ANY_ID,
698 .subdevice = PCI_ANY_ID,
699 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
700 },
701
702 {
703 .vendor = PCI_VENDOR_ID_RICOH,
704 .device = 0xe823,
705 .subvendor = PCI_ANY_ID,
706 .subdevice = PCI_ANY_ID,
707 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
708 },
709
710 {
711 .vendor = PCI_VENDOR_ID_ENE,
712 .device = PCI_DEVICE_ID_ENE_CB712_SD,
713 .subvendor = PCI_ANY_ID,
714 .subdevice = PCI_ANY_ID,
715 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
716 },
717
718 {
719 .vendor = PCI_VENDOR_ID_ENE,
720 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
721 .subvendor = PCI_ANY_ID,
722 .subdevice = PCI_ANY_ID,
723 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
724 },
725
726 {
727 .vendor = PCI_VENDOR_ID_ENE,
728 .device = PCI_DEVICE_ID_ENE_CB714_SD,
729 .subvendor = PCI_ANY_ID,
730 .subdevice = PCI_ANY_ID,
731 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
732 },
733
734 {
735 .vendor = PCI_VENDOR_ID_ENE,
736 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
737 .subvendor = PCI_ANY_ID,
738 .subdevice = PCI_ANY_ID,
739 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
740 },
741
742 {
743 .vendor = PCI_VENDOR_ID_MARVELL,
744 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
745 .subvendor = PCI_ANY_ID,
746 .subdevice = PCI_ANY_ID,
747 .driver_data = (kernel_ulong_t)&sdhci_cafe,
748 },
749
750 {
751 .vendor = PCI_VENDOR_ID_JMICRON,
752 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
753 .subvendor = PCI_ANY_ID,
754 .subdevice = PCI_ANY_ID,
755 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
756 },
757
758 {
759 .vendor = PCI_VENDOR_ID_JMICRON,
760 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
764 },
765
766 {
767 .vendor = PCI_VENDOR_ID_JMICRON,
768 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
769 .subvendor = PCI_ANY_ID,
770 .subdevice = PCI_ANY_ID,
771 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
772 },
773
774 {
775 .vendor = PCI_VENDOR_ID_JMICRON,
776 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
777 .subvendor = PCI_ANY_ID,
778 .subdevice = PCI_ANY_ID,
779 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
780 },
781
782 {
783 .vendor = PCI_VENDOR_ID_SYSKONNECT,
784 .device = 0x8000,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .driver_data = (kernel_ulong_t)&sdhci_syskt,
788 },
789
790 {
791 .vendor = PCI_VENDOR_ID_VIA,
792 .device = 0x95d0,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .driver_data = (kernel_ulong_t)&sdhci_via,
796 },
797
798 {
799 .vendor = PCI_VENDOR_ID_INTEL,
800 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
801 .subvendor = PCI_ANY_ID,
802 .subdevice = PCI_ANY_ID,
803 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
804 },
805
806 {
807 .vendor = PCI_VENDOR_ID_INTEL,
808 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
812 },
813
814 {
815 .vendor = PCI_VENDOR_ID_INTEL,
816 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
820 },
821
822 {
823 .vendor = PCI_VENDOR_ID_INTEL,
824 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
828 },
829
830 {
831 .vendor = PCI_VENDOR_ID_INTEL,
832 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
835 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
836 },
837
838 {
839 .vendor = PCI_VENDOR_ID_INTEL,
840 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
844 },
845
846 {
847 .vendor = PCI_VENDOR_ID_INTEL,
848 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
851 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
852 },
853
854 {
855 .vendor = PCI_VENDOR_ID_INTEL,
856 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
857 .subvendor = PCI_ANY_ID,
858 .subdevice = PCI_ANY_ID,
859 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
860 },
861
862 {
863 .vendor = PCI_VENDOR_ID_O2,
864 .device = PCI_DEVICE_ID_O2_8120,
865 .subvendor = PCI_ANY_ID,
866 .subdevice = PCI_ANY_ID,
867 .driver_data = (kernel_ulong_t)&sdhci_o2,
868 },
869
870 {
871 .vendor = PCI_VENDOR_ID_O2,
872 .device = PCI_DEVICE_ID_O2_8220,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
875 .driver_data = (kernel_ulong_t)&sdhci_o2,
876 },
877
878 {
879 .vendor = PCI_VENDOR_ID_O2,
880 .device = PCI_DEVICE_ID_O2_8221,
881 .subvendor = PCI_ANY_ID,
882 .subdevice = PCI_ANY_ID,
883 .driver_data = (kernel_ulong_t)&sdhci_o2,
884 },
885
886 {
887 .vendor = PCI_VENDOR_ID_O2,
888 .device = PCI_DEVICE_ID_O2_8320,
889 .subvendor = PCI_ANY_ID,
890 .subdevice = PCI_ANY_ID,
891 .driver_data = (kernel_ulong_t)&sdhci_o2,
892 },
893
894 {
895 .vendor = PCI_VENDOR_ID_O2,
896 .device = PCI_DEVICE_ID_O2_8321,
897 .subvendor = PCI_ANY_ID,
898 .subdevice = PCI_ANY_ID,
899 .driver_data = (kernel_ulong_t)&sdhci_o2,
900 },
901
902 { /* Generic SD host controller */
903 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
904 },
905
906 { /* end: all zeroes */ },
907 };
908
909 MODULE_DEVICE_TABLE(pci, pci_ids);
910
911 /*****************************************************************************\
912 * *
913 * SDHCI core callbacks *
914 * *
915 \*****************************************************************************/
916
917 static int sdhci_pci_enable_dma(struct sdhci_host *host)
918 {
919 struct sdhci_pci_slot *slot;
920 struct pci_dev *pdev;
921 int ret;
922
923 slot = sdhci_priv(host);
924 pdev = slot->chip->pdev;
925
926 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
927 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
928 (host->flags & SDHCI_USE_SDMA)) {
929 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
930 "doesn't fully claim to support it.\n");
931 }
932
933 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
934 if (ret)
935 return ret;
936
937 pci_set_master(pdev);
938
939 return 0;
940 }
941
942 static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
943 {
944 u8 ctrl;
945
946 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
947
948 switch (width) {
949 case MMC_BUS_WIDTH_8:
950 ctrl |= SDHCI_CTRL_8BITBUS;
951 ctrl &= ~SDHCI_CTRL_4BITBUS;
952 break;
953 case MMC_BUS_WIDTH_4:
954 ctrl |= SDHCI_CTRL_4BITBUS;
955 ctrl &= ~SDHCI_CTRL_8BITBUS;
956 break;
957 default:
958 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
959 break;
960 }
961
962 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
963
964 return 0;
965 }
966
967 static void sdhci_pci_hw_reset(struct sdhci_host *host)
968 {
969 struct sdhci_pci_slot *slot = sdhci_priv(host);
970 int rst_n_gpio = slot->rst_n_gpio;
971
972 if (!gpio_is_valid(rst_n_gpio))
973 return;
974 gpio_set_value_cansleep(rst_n_gpio, 0);
975 /* For eMMC, minimum is 1us but give it 10us for good measure */
976 udelay(10);
977 gpio_set_value_cansleep(rst_n_gpio, 1);
978 /* For eMMC, minimum is 200us but give it 300us for good measure */
979 usleep_range(300, 1000);
980 }
981
982 static struct sdhci_ops sdhci_pci_ops = {
983 .enable_dma = sdhci_pci_enable_dma,
984 .platform_8bit_width = sdhci_pci_8bit_width,
985 .hw_reset = sdhci_pci_hw_reset,
986 };
987
988 /*****************************************************************************\
989 * *
990 * Suspend/resume *
991 * *
992 \*****************************************************************************/
993
994 #ifdef CONFIG_PM
995
996 static int sdhci_pci_suspend(struct device *dev)
997 {
998 struct pci_dev *pdev = to_pci_dev(dev);
999 struct sdhci_pci_chip *chip;
1000 struct sdhci_pci_slot *slot;
1001 mmc_pm_flag_t slot_pm_flags;
1002 mmc_pm_flag_t pm_flags = 0;
1003 int i, ret;
1004
1005 chip = pci_get_drvdata(pdev);
1006 if (!chip)
1007 return 0;
1008
1009 for (i = 0; i < chip->num_slots; i++) {
1010 slot = chip->slots[i];
1011 if (!slot)
1012 continue;
1013
1014 ret = sdhci_suspend_host(slot->host);
1015
1016 if (ret) {
1017 for (i--; i >= 0; i--)
1018 sdhci_resume_host(chip->slots[i]->host);
1019 return ret;
1020 }
1021
1022 slot_pm_flags = slot->host->mmc->pm_flags;
1023 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1024 sdhci_enable_irq_wakeups(slot->host);
1025
1026 pm_flags |= slot_pm_flags;
1027 }
1028
1029 if (chip->fixes && chip->fixes->suspend) {
1030 ret = chip->fixes->suspend(chip);
1031 if (ret) {
1032 for (i = chip->num_slots - 1; i >= 0; i--)
1033 sdhci_resume_host(chip->slots[i]->host);
1034 return ret;
1035 }
1036 }
1037
1038 pci_save_state(pdev);
1039 if (pm_flags & MMC_PM_KEEP_POWER) {
1040 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1041 pci_pme_active(pdev, true);
1042 pci_enable_wake(pdev, PCI_D3hot, 1);
1043 }
1044 pci_set_power_state(pdev, PCI_D3hot);
1045 } else {
1046 pci_enable_wake(pdev, PCI_D3hot, 0);
1047 pci_disable_device(pdev);
1048 pci_set_power_state(pdev, PCI_D3hot);
1049 }
1050
1051 return 0;
1052 }
1053
1054 static int sdhci_pci_resume(struct device *dev)
1055 {
1056 struct pci_dev *pdev = to_pci_dev(dev);
1057 struct sdhci_pci_chip *chip;
1058 struct sdhci_pci_slot *slot;
1059 int i, ret;
1060
1061 chip = pci_get_drvdata(pdev);
1062 if (!chip)
1063 return 0;
1064
1065 pci_set_power_state(pdev, PCI_D0);
1066 pci_restore_state(pdev);
1067 ret = pci_enable_device(pdev);
1068 if (ret)
1069 return ret;
1070
1071 if (chip->fixes && chip->fixes->resume) {
1072 ret = chip->fixes->resume(chip);
1073 if (ret)
1074 return ret;
1075 }
1076
1077 for (i = 0; i < chip->num_slots; i++) {
1078 slot = chip->slots[i];
1079 if (!slot)
1080 continue;
1081
1082 ret = sdhci_resume_host(slot->host);
1083 if (ret)
1084 return ret;
1085 }
1086
1087 return 0;
1088 }
1089
1090 #else /* CONFIG_PM */
1091
1092 #define sdhci_pci_suspend NULL
1093 #define sdhci_pci_resume NULL
1094
1095 #endif /* CONFIG_PM */
1096
1097 #ifdef CONFIG_PM_RUNTIME
1098
1099 static int sdhci_pci_runtime_suspend(struct device *dev)
1100 {
1101 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1102 struct sdhci_pci_chip *chip;
1103 struct sdhci_pci_slot *slot;
1104 int i, ret;
1105
1106 chip = pci_get_drvdata(pdev);
1107 if (!chip)
1108 return 0;
1109
1110 for (i = 0; i < chip->num_slots; i++) {
1111 slot = chip->slots[i];
1112 if (!slot)
1113 continue;
1114
1115 ret = sdhci_runtime_suspend_host(slot->host);
1116
1117 if (ret) {
1118 for (i--; i >= 0; i--)
1119 sdhci_runtime_resume_host(chip->slots[i]->host);
1120 return ret;
1121 }
1122 }
1123
1124 if (chip->fixes && chip->fixes->suspend) {
1125 ret = chip->fixes->suspend(chip);
1126 if (ret) {
1127 for (i = chip->num_slots - 1; i >= 0; i--)
1128 sdhci_runtime_resume_host(chip->slots[i]->host);
1129 return ret;
1130 }
1131 }
1132
1133 return 0;
1134 }
1135
1136 static int sdhci_pci_runtime_resume(struct device *dev)
1137 {
1138 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1139 struct sdhci_pci_chip *chip;
1140 struct sdhci_pci_slot *slot;
1141 int i, ret;
1142
1143 chip = pci_get_drvdata(pdev);
1144 if (!chip)
1145 return 0;
1146
1147 if (chip->fixes && chip->fixes->resume) {
1148 ret = chip->fixes->resume(chip);
1149 if (ret)
1150 return ret;
1151 }
1152
1153 for (i = 0; i < chip->num_slots; i++) {
1154 slot = chip->slots[i];
1155 if (!slot)
1156 continue;
1157
1158 ret = sdhci_runtime_resume_host(slot->host);
1159 if (ret)
1160 return ret;
1161 }
1162
1163 return 0;
1164 }
1165
1166 static int sdhci_pci_runtime_idle(struct device *dev)
1167 {
1168 return 0;
1169 }
1170
1171 #else
1172
1173 #define sdhci_pci_runtime_suspend NULL
1174 #define sdhci_pci_runtime_resume NULL
1175 #define sdhci_pci_runtime_idle NULL
1176
1177 #endif
1178
1179 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1180 .suspend = sdhci_pci_suspend,
1181 .resume = sdhci_pci_resume,
1182 .runtime_suspend = sdhci_pci_runtime_suspend,
1183 .runtime_resume = sdhci_pci_runtime_resume,
1184 .runtime_idle = sdhci_pci_runtime_idle,
1185 };
1186
1187 /*****************************************************************************\
1188 * *
1189 * Device probing/removal *
1190 * *
1191 \*****************************************************************************/
1192
1193 static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1194 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
1195 {
1196 struct sdhci_pci_slot *slot;
1197 struct sdhci_host *host;
1198 int ret;
1199
1200 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1201 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1202 return ERR_PTR(-ENODEV);
1203 }
1204
1205 if (pci_resource_len(pdev, bar) != 0x100) {
1206 dev_err(&pdev->dev, "Invalid iomem size. You may "
1207 "experience problems.\n");
1208 }
1209
1210 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1211 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1212 return ERR_PTR(-ENODEV);
1213 }
1214
1215 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1216 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1217 return ERR_PTR(-ENODEV);
1218 }
1219
1220 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1221 if (IS_ERR(host)) {
1222 dev_err(&pdev->dev, "cannot allocate host\n");
1223 return ERR_CAST(host);
1224 }
1225
1226 slot = sdhci_priv(host);
1227
1228 slot->chip = chip;
1229 slot->host = host;
1230 slot->pci_bar = bar;
1231 slot->rst_n_gpio = -EINVAL;
1232
1233 host->hw_name = "PCI";
1234 host->ops = &sdhci_pci_ops;
1235 host->quirks = chip->quirks;
1236
1237 host->irq = pdev->irq;
1238
1239 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1240 if (ret) {
1241 dev_err(&pdev->dev, "cannot request region\n");
1242 goto free;
1243 }
1244
1245 host->ioaddr = pci_ioremap_bar(pdev, bar);
1246 if (!host->ioaddr) {
1247 dev_err(&pdev->dev, "failed to remap registers\n");
1248 ret = -ENOMEM;
1249 goto release;
1250 }
1251
1252 if (chip->fixes && chip->fixes->probe_slot) {
1253 ret = chip->fixes->probe_slot(slot);
1254 if (ret)
1255 goto unmap;
1256 }
1257
1258 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1259
1260 ret = sdhci_add_host(host);
1261 if (ret)
1262 goto remove;
1263
1264 return slot;
1265
1266 remove:
1267 if (chip->fixes && chip->fixes->remove_slot)
1268 chip->fixes->remove_slot(slot, 0);
1269
1270 unmap:
1271 iounmap(host->ioaddr);
1272
1273 release:
1274 pci_release_region(pdev, bar);
1275
1276 free:
1277 sdhci_free_host(host);
1278
1279 return ERR_PTR(ret);
1280 }
1281
1282 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1283 {
1284 int dead;
1285 u32 scratch;
1286
1287 dead = 0;
1288 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1289 if (scratch == (u32)-1)
1290 dead = 1;
1291
1292 sdhci_remove_host(slot->host, dead);
1293
1294 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1295 slot->chip->fixes->remove_slot(slot, dead);
1296
1297 pci_release_region(slot->chip->pdev, slot->pci_bar);
1298
1299 sdhci_free_host(slot->host);
1300 }
1301
1302 static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev)
1303 {
1304 pm_runtime_put_noidle(dev);
1305 pm_runtime_allow(dev);
1306 pm_runtime_set_autosuspend_delay(dev, 50);
1307 pm_runtime_use_autosuspend(dev);
1308 pm_suspend_ignore_children(dev, 1);
1309 }
1310
1311 static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev)
1312 {
1313 pm_runtime_forbid(dev);
1314 pm_runtime_get_noresume(dev);
1315 }
1316
1317 static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1318 const struct pci_device_id *ent)
1319 {
1320 struct sdhci_pci_chip *chip;
1321 struct sdhci_pci_slot *slot;
1322
1323 u8 slots, first_bar;
1324 int ret, i;
1325
1326 BUG_ON(pdev == NULL);
1327 BUG_ON(ent == NULL);
1328
1329 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1330 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1331
1332 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1333 if (ret)
1334 return ret;
1335
1336 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1337 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1338 if (slots == 0)
1339 return -ENODEV;
1340
1341 BUG_ON(slots > MAX_SLOTS);
1342
1343 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1344 if (ret)
1345 return ret;
1346
1347 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1348
1349 if (first_bar > 5) {
1350 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1351 return -ENODEV;
1352 }
1353
1354 ret = pci_enable_device(pdev);
1355 if (ret)
1356 return ret;
1357
1358 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1359 if (!chip) {
1360 ret = -ENOMEM;
1361 goto err;
1362 }
1363
1364 chip->pdev = pdev;
1365 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1366 if (chip->fixes) {
1367 chip->quirks = chip->fixes->quirks;
1368 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1369 }
1370 chip->num_slots = slots;
1371
1372 pci_set_drvdata(pdev, chip);
1373
1374 if (chip->fixes && chip->fixes->probe) {
1375 ret = chip->fixes->probe(chip);
1376 if (ret)
1377 goto free;
1378 }
1379
1380 slots = chip->num_slots; /* Quirk may have changed this */
1381
1382 for (i = 0; i < slots; i++) {
1383 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1384 if (IS_ERR(slot)) {
1385 for (i--; i >= 0; i--)
1386 sdhci_pci_remove_slot(chip->slots[i]);
1387 ret = PTR_ERR(slot);
1388 goto free;
1389 }
1390
1391 chip->slots[i] = slot;
1392 }
1393
1394 if (chip->allow_runtime_pm)
1395 sdhci_pci_runtime_pm_allow(&pdev->dev);
1396
1397 return 0;
1398
1399 free:
1400 pci_set_drvdata(pdev, NULL);
1401 kfree(chip);
1402
1403 err:
1404 pci_disable_device(pdev);
1405 return ret;
1406 }
1407
1408 static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1409 {
1410 int i;
1411 struct sdhci_pci_chip *chip;
1412
1413 chip = pci_get_drvdata(pdev);
1414
1415 if (chip) {
1416 if (chip->allow_runtime_pm)
1417 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1418
1419 for (i = 0; i < chip->num_slots; i++)
1420 sdhci_pci_remove_slot(chip->slots[i]);
1421
1422 pci_set_drvdata(pdev, NULL);
1423 kfree(chip);
1424 }
1425
1426 pci_disable_device(pdev);
1427 }
1428
1429 static struct pci_driver sdhci_driver = {
1430 .name = "sdhci-pci",
1431 .id_table = pci_ids,
1432 .probe = sdhci_pci_probe,
1433 .remove = __devexit_p(sdhci_pci_remove),
1434 .driver = {
1435 .pm = &sdhci_pci_pm_ops
1436 },
1437 };
1438
1439 /*****************************************************************************\
1440 * *
1441 * Driver init/exit *
1442 * *
1443 \*****************************************************************************/
1444
1445 static int __init sdhci_drv_init(void)
1446 {
1447 return pci_register_driver(&sdhci_driver);
1448 }
1449
1450 static void __exit sdhci_drv_exit(void)
1451 {
1452 pci_unregister_driver(&sdhci_driver);
1453 }
1454
1455 module_init(sdhci_drv_init);
1456 module_exit(sdhci_drv_exit);
1457
1458 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1459 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1460 MODULE_LICENSE("GPL");
Linux with added FPC-III support