drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32
  33 /* rv515 depends on : */
  34 void r100_hdp_reset(struct radeon_device *rdev);
  35 int r100_cp_reset(struct radeon_device *rdev);
  36 int r100_rb2d_reset(struct radeon_device *rdev);
  37 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  38 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  39 int rv370_pcie_gart_enable(struct radeon_device *rdev);
  40 void rv370_pcie_gart_disable(struct radeon_device *rdev);
  41 void r420_pipes_init(struct radeon_device *rdev);
  42 void rs600_mc_disable_clients(struct radeon_device *rdev);
  43 void rs600_disable_vga(struct radeon_device *rdev);
  44
  45 /* This files gather functions specifics to:
  46  * rv515
  47  *
  48  * Some of these functions might be used by newer ASICs.
  49  */
  50 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  51 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  52 void rv515_gpu_init(struct radeon_device *rdev);
  53 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  54
  55
  56 /*
  57  * MC
  58  */
  59 int rv515_mc_init(struct radeon_device *rdev)
  60 {
  61         uint32_t tmp;
  62         int r;
  63
  64         if (r100_debugfs_rbbm_init(rdev)) {
  65                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  66         }
  67         if (rv515_debugfs_pipes_info_init(rdev)) {
  68                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  69         }
  70         if (rv515_debugfs_ga_info_init(rdev)) {
  71                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  72         }
  73
  74         rv515_gpu_init(rdev);
  75         rv370_pcie_gart_disable(rdev);
  76
  77         /* Setup GPU memory space */
  78         rdev->mc.vram_location = 0xFFFFFFFFUL;
  79         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  80         if (rdev->flags & RADEON_IS_AGP) {
  81                 r = radeon_agp_init(rdev);
  82                 if (r) {
  83                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  84                         rdev->flags &= ~RADEON_IS_AGP;
  85                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  86                 } else {
  87                         rdev->mc.gtt_location = rdev->mc.agp_base;
  88                 }
  89         }
  90         r = radeon_mc_setup(rdev);
  91         if (r) {
  92                 return r;
  93         }
  94
  95         /* Program GPU memory space */
  96         rs600_mc_disable_clients(rdev);
  97         if (rv515_mc_wait_for_idle(rdev)) {
  98                 printk(KERN_WARNING "Failed to wait MC idle while "
  99                        "programming pipes. Bad things might happen.\n");
 100         }
 101         /* Write VRAM size in case we are limiting it */
 102         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
 103         tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
 104         WREG32(0x134, tmp);
 105         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
 106         tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
 107         tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
 108         WREG32_MC(RV515_MC_FB_LOCATION, tmp);
 109         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 110         WREG32(0x310, rdev->mc.vram_location);
 111         if (rdev->flags & RADEON_IS_AGP) {
 112                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 113                 tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
 114                 tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
 115                 WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
 116                 WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
 117                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
 118         } else {
 119                 WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
 120                 WREG32_MC(RV515_MC_AGP_BASE, 0);
 121                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
 122         }
 123         return 0;
 124 }
 125
 126 void rv515_mc_fini(struct radeon_device *rdev)
 127 {
 128         rv370_pcie_gart_disable(rdev);
 129         radeon_gart_table_vram_free(rdev);
 130         radeon_gart_fini(rdev);
 131 }
 132
 133
 134 /*
 135  * Global GPU functions
 136  */
 137 void rv515_ring_start(struct radeon_device *rdev)
 138 {
 139         unsigned gb_tile_config;
 140         int r;
 141
 142         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 143         gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
 144         switch (rdev->num_gb_pipes) {
 145         case 2:
 146                 gb_tile_config |= R300_PIPE_COUNT_R300;
 147                 break;
 148         case 3:
 149                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 150                 break;
 151         case 4:
 152                 gb_tile_config |= R300_PIPE_COUNT_R420;
 153                 break;
 154         case 1:
 155         default:
 156                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 157                 break;
 158         }
 159
 160         r = radeon_ring_lock(rdev, 64);
 161         if (r) {
 162                 return;
 163         }
 164         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 165         radeon_ring_write(rdev,
 166                           RADEON_ISYNC_ANY2D_IDLE3D |
 167                           RADEON_ISYNC_ANY3D_IDLE2D |
 168                           RADEON_ISYNC_WAIT_IDLEGUI |
 169                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 170         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
 171         radeon_ring_write(rdev, gb_tile_config);
 172         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 173         radeon_ring_write(rdev,
 174                           RADEON_WAIT_2D_IDLECLEAN |
 175                           RADEON_WAIT_3D_IDLECLEAN);
 176         radeon_ring_write(rdev, PACKET0(0x170C, 0));
 177         radeon_ring_write(rdev, 1 << 31);
 178         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
 179         radeon_ring_write(rdev, 0);
 180         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
 181         radeon_ring_write(rdev, 0);
 182         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
 183         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
 184         radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
 185         radeon_ring_write(rdev, 0);
 186         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 187         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 188         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 189         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 190         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 191         radeon_ring_write(rdev,
 192                           RADEON_WAIT_2D_IDLECLEAN |
 193                           RADEON_WAIT_3D_IDLECLEAN);
 194         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
 195         radeon_ring_write(rdev, 0);
 196         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 197         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 198         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 199         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 200         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
 201         radeon_ring_write(rdev,
 202                           ((6 << R300_MS_X0_SHIFT) |
 203                            (6 << R300_MS_Y0_SHIFT) |
 204                            (6 << R300_MS_X1_SHIFT) |
 205                            (6 << R300_MS_Y1_SHIFT) |
 206                            (6 << R300_MS_X2_SHIFT) |
 207                            (6 << R300_MS_Y2_SHIFT) |
 208                            (6 << R300_MSBD0_Y_SHIFT) |
 209                            (6 << R300_MSBD0_X_SHIFT)));
 210         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
 211         radeon_ring_write(rdev,
 212                           ((6 << R300_MS_X3_SHIFT) |
 213                            (6 << R300_MS_Y3_SHIFT) |
 214                            (6 << R300_MS_X4_SHIFT) |
 215                            (6 << R300_MS_Y4_SHIFT) |
 216                            (6 << R300_MS_X5_SHIFT) |
 217                            (6 << R300_MS_Y5_SHIFT) |
 218                            (6 << R300_MSBD1_SHIFT)));
 219         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
 220         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 221         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
 222         radeon_ring_write(rdev,
 223                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 224         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
 225         radeon_ring_write(rdev,
 226                           R300_GEOMETRY_ROUND_NEAREST |
 227                           R300_COLOR_ROUND_NEAREST);
 228         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
 229         radeon_ring_write(rdev, 0);
 230         radeon_ring_unlock_commit(rdev);
 231 }
 232
 233 void rv515_errata(struct radeon_device *rdev)
 234 {
 235         rdev->pll_errata = 0;
 236 }
 237
 238 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 239 {
 240         unsigned i;
 241         uint32_t tmp;
 242
 243         for (i = 0; i < rdev->usec_timeout; i++) {
 244                 /* read MC_STATUS */
 245                 tmp = RREG32_MC(RV515_MC_STATUS);
 246                 if (tmp & RV515_MC_STATUS_IDLE) {
 247                         return 0;
 248                 }
 249                 DRM_UDELAY(1);
 250         }
 251         return -1;
 252 }
 253
 254 void rv515_gpu_init(struct radeon_device *rdev)
 255 {
 256         unsigned pipe_select_current, gb_pipe_select, tmp;
 257
 258         r100_hdp_reset(rdev);
 259         r100_rb2d_reset(rdev);
 260
 261         if (r100_gui_wait_for_idle(rdev)) {
 262                 printk(KERN_WARNING "Failed to wait GUI idle while "
 263                        "reseting GPU. Bad things might happen.\n");
 264         }
 265
 266         rs600_disable_vga(rdev);
 267
 268         r420_pipes_init(rdev);
 269         gb_pipe_select = RREG32(0x402C);
 270         tmp = RREG32(0x170C);
 271         pipe_select_current = (tmp >> 2) & 3;
 272         tmp = (1 << pipe_select_current) |
 273               (((gb_pipe_select >> 8) & 0xF) << 4);
 274         WREG32_PLL(0x000D, tmp);
 275         if (r100_gui_wait_for_idle(rdev)) {
 276                 printk(KERN_WARNING "Failed to wait GUI idle while "
 277                        "reseting GPU. Bad things might happen.\n");
 278         }
 279         if (rv515_mc_wait_for_idle(rdev)) {
 280                 printk(KERN_WARNING "Failed to wait MC idle while "
 281                        "programming pipes. Bad things might happen.\n");
 282         }
 283 }
 284
 285 int rv515_ga_reset(struct radeon_device *rdev)
 286 {
 287         uint32_t tmp;
 288         bool reinit_cp;
 289         int i;
 290
 291         reinit_cp = rdev->cp.ready;
 292         rdev->cp.ready = false;
 293         for (i = 0; i < rdev->usec_timeout; i++) {
 294                 WREG32(RADEON_CP_CSQ_MODE, 0);
 295                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 296                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
 297                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
 298                 udelay(200);
 299                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 300                 /* Wait to prevent race in RBBM_STATUS */
 301                 mdelay(1);
 302                 tmp = RREG32(RADEON_RBBM_STATUS);
 303                 if (tmp & ((1 << 20) | (1 << 26))) {
 304                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
 305                         /* GA still busy soft reset it */
 306                         WREG32(0x429C, 0x200);
 307                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 308                         WREG32(0x43E0, 0);
 309                         WREG32(0x43E4, 0);
 310                         WREG32(0x24AC, 0);
 311                 }
 312                 /* Wait to prevent race in RBBM_STATUS */
 313                 mdelay(1);
 314                 tmp = RREG32(RADEON_RBBM_STATUS);
 315                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 316                         break;
 317                 }
 318         }
 319         for (i = 0; i < rdev->usec_timeout; i++) {
 320                 tmp = RREG32(RADEON_RBBM_STATUS);
 321                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 322                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 323                                  tmp);
 324                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
 325                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
 326                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
 327                         if (reinit_cp) {
 328                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 329                         }
 330                         return 0;
 331                 }
 332                 DRM_UDELAY(1);
 333         }
 334         tmp = RREG32(RADEON_RBBM_STATUS);
 335         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 336         return -1;
 337 }
 338
 339 int rv515_gpu_reset(struct radeon_device *rdev)
 340 {
 341         uint32_t status;
 342
 343         /* reset order likely matter */
 344         status = RREG32(RADEON_RBBM_STATUS);
 345         /* reset HDP */
 346         r100_hdp_reset(rdev);
 347         /* reset rb2d */
 348         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 349                 r100_rb2d_reset(rdev);
 350         }
 351         /* reset GA */
 352         if (status & ((1 << 20) | (1 << 26))) {
 353                 rv515_ga_reset(rdev);
 354         }
 355         /* reset CP */
 356         status = RREG32(RADEON_RBBM_STATUS);
 357         if (status & (1 << 16)) {
 358                 r100_cp_reset(rdev);
 359         }
 360         /* Check if GPU is idle */
 361         status = RREG32(RADEON_RBBM_STATUS);
 362         if (status & (1 << 31)) {
 363                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 364                 return -1;
 365         }
 366         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 367         return 0;
 368 }
 369
 370
 371 /*
 372  * VRAM info
 373  */
 374 static void rv515_vram_get_type(struct radeon_device *rdev)
 375 {
 376         uint32_t tmp;
 377
 378         rdev->mc.vram_width = 128;
 379         rdev->mc.vram_is_ddr = true;
 380         tmp = RREG32_MC(RV515_MC_CNTL);
 381         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
 382         switch (tmp) {
 383         case 0:
 384                 rdev->mc.vram_width = 64;
 385                 break;
 386         case 1:
 387                 rdev->mc.vram_width = 128;
 388                 break;
 389         default:
 390                 rdev->mc.vram_width = 128;
 391                 break;
 392         }
 393 }
 394
 395 void rv515_vram_info(struct radeon_device *rdev)
 396 {
 397         rv515_vram_get_type(rdev);
 398         rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 399
 400         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 401         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 402 }
 403
 404
 405 /*
 406  * Indirect registers accessor
 407  */
 408 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 409 {
 410         uint32_t r;
 411
 412         WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 413         r = RREG32(R520_MC_IND_DATA);
 414         WREG32(R520_MC_IND_INDEX, 0);
 415         return r;
 416 }
 417
 418 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 419 {
 420         WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 421         WREG32(R520_MC_IND_DATA, (v));
 422         WREG32(R520_MC_IND_INDEX, 0);
 423 }
 424
 425 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 426 {
 427         uint32_t r;
 428
 429         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
 430         (void)RREG32(RADEON_PCIE_INDEX);
 431         r = RREG32(RADEON_PCIE_DATA);
 432         return r;
 433 }
 434
 435 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 436 {
 437         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
 438         (void)RREG32(RADEON_PCIE_INDEX);
 439         WREG32(RADEON_PCIE_DATA, (v));
 440         (void)RREG32(RADEON_PCIE_DATA);
 441 }
 442
 443
 444 /*
 445  * Debugfs info
 446  */
 447 #if defined(CONFIG_DEBUG_FS)
 448 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 449 {
 450         struct drm_info_node *node = (struct drm_info_node *) m->private;
 451         struct drm_device *dev = node->minor->dev;
 452         struct radeon_device *rdev = dev->dev_private;
 453         uint32_t tmp;
 454
 455         tmp = RREG32(R400_GB_PIPE_SELECT);
 456         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 457         tmp = RREG32(R500_SU_REG_DEST);
 458         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 459         tmp = RREG32(R300_GB_TILE_CONFIG);
 460         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 461         tmp = RREG32(R300_DST_PIPE_CONFIG);
 462         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 463         return 0;
 464 }
 465
 466 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 467 {
 468         struct drm_info_node *node = (struct drm_info_node *) m->private;
 469         struct drm_device *dev = node->minor->dev;
 470         struct radeon_device *rdev = dev->dev_private;
 471         uint32_t tmp;
 472
 473         tmp = RREG32(0x2140);
 474         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 475         radeon_gpu_reset(rdev);
 476         tmp = RREG32(0x425C);
 477         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 478         return 0;
 479 }
 480
 481 static struct drm_info_list rv515_pipes_info_list[] = {
 482         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 483 };
 484
 485 static struct drm_info_list rv515_ga_info_list[] = {
 486         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 487 };
 488 #endif
 489
 490 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 491 {
 492 #if defined(CONFIG_DEBUG_FS)
 493         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 494 #else
 495         return 0;
 496 #endif
 497 }
 498
 499 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 500 {
 501 #if defined(CONFIG_DEBUG_FS)
 502         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 503 #else
 504         return 0;
 505 #endif
 506 }
 507
 508
 509 /*
 510  * Asic initialization
 511  */
 512 static const unsigned r500_reg_safe_bm[159] = {
 513         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 514         0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF,
 515         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 516         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 517         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 518         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 519         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 520         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 521         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 522         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 523         0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
 524         0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
 525         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 526         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 527         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
 528         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 529         0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
 530         0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
 531         0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
 532         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 533         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 534         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 535         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 536         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 537         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 538         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 539         0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 540         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 541         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 542         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 543         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 544         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 545         0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
 546         0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
 547         0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
 548         0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
 549         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 550         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
 551         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 552         0x0003FC01, 0x3FFFFCF8, 0xFE800B19,
 553 };
 554
 555
 556
 557 int rv515_init(struct radeon_device *rdev)
 558 {
 559         rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
 560         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
 561         return 0;
 562 }