drivers/staging/octeon/cvmx-pcsx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_PCSX_DEFS_H__
  29 #define __CVMX_PCSX_DEFS_H__
  30
  31 #define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \
  32          CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  33 #define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \
  34          CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  35 #define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \
  36          CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  37 #define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \
  38          CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  39 #define CVMX_PCSX_INTX_EN_REG(offset, block_id) \
  40          CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  41 #define CVMX_PCSX_INTX_REG(offset, block_id) \
  42          CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  43 #define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \
  44          CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  45 #define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \
  46          CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  47 #define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \
  48          CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  49 #define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \
  50          CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  51 #define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \
  52          CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  53 #define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \
  54          CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  55 #define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \
  56          CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  57 #define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \
  58          CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  59 #define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \
  60          CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  61 #define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \
  62          CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  63 #define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \
  64          CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
  65
  66 union cvmx_pcsx_anx_adv_reg {
  67         uint64_t u64;
  68         struct cvmx_pcsx_anx_adv_reg_s {
  69                 uint64_t reserved_16_63:48;
  70                 uint64_t np:1;
  71                 uint64_t reserved_14_14:1;
  72                 uint64_t rem_flt:2;
  73                 uint64_t reserved_9_11:3;
  74                 uint64_t pause:2;
  75                 uint64_t hfd:1;
  76                 uint64_t fd:1;
  77                 uint64_t reserved_0_4:5;
  78         } s;
  79         struct cvmx_pcsx_anx_adv_reg_s cn52xx;
  80         struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
  81         struct cvmx_pcsx_anx_adv_reg_s cn56xx;
  82         struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
  83 };
  84
  85 union cvmx_pcsx_anx_ext_st_reg {
  86         uint64_t u64;
  87         struct cvmx_pcsx_anx_ext_st_reg_s {
  88                 uint64_t reserved_16_63:48;
  89                 uint64_t thou_xfd:1;
  90                 uint64_t thou_xhd:1;
  91                 uint64_t thou_tfd:1;
  92                 uint64_t thou_thd:1;
  93                 uint64_t reserved_0_11:12;
  94         } s;
  95         struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
  96         struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
  97         struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
  98         struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
  99 };
 100
 101 union cvmx_pcsx_anx_lp_abil_reg {
 102         uint64_t u64;
 103         struct cvmx_pcsx_anx_lp_abil_reg_s {
 104                 uint64_t reserved_16_63:48;
 105                 uint64_t np:1;
 106                 uint64_t ack:1;
 107                 uint64_t rem_flt:2;
 108                 uint64_t reserved_9_11:3;
 109                 uint64_t pause:2;
 110                 uint64_t hfd:1;
 111                 uint64_t fd:1;
 112                 uint64_t reserved_0_4:5;
 113         } s;
 114         struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
 115         struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
 116         struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
 117         struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
 118 };
 119
 120 union cvmx_pcsx_anx_results_reg {
 121         uint64_t u64;
 122         struct cvmx_pcsx_anx_results_reg_s {
 123                 uint64_t reserved_7_63:57;
 124                 uint64_t pause:2;
 125                 uint64_t spd:2;
 126                 uint64_t an_cpt:1;
 127                 uint64_t dup:1;
 128                 uint64_t link_ok:1;
 129         } s;
 130         struct cvmx_pcsx_anx_results_reg_s cn52xx;
 131         struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
 132         struct cvmx_pcsx_anx_results_reg_s cn56xx;
 133         struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
 134 };
 135
 136 union cvmx_pcsx_intx_en_reg {
 137         uint64_t u64;
 138         struct cvmx_pcsx_intx_en_reg_s {
 139                 uint64_t reserved_12_63:52;
 140                 uint64_t dup:1;
 141                 uint64_t sync_bad_en:1;
 142                 uint64_t an_bad_en:1;
 143                 uint64_t rxlock_en:1;
 144                 uint64_t rxbad_en:1;
 145                 uint64_t rxerr_en:1;
 146                 uint64_t txbad_en:1;
 147                 uint64_t txfifo_en:1;
 148                 uint64_t txfifu_en:1;
 149                 uint64_t an_err_en:1;
 150                 uint64_t xmit_en:1;
 151                 uint64_t lnkspd_en:1;
 152         } s;
 153         struct cvmx_pcsx_intx_en_reg_s cn52xx;
 154         struct cvmx_pcsx_intx_en_reg_s cn52xxp1;
 155         struct cvmx_pcsx_intx_en_reg_s cn56xx;
 156         struct cvmx_pcsx_intx_en_reg_s cn56xxp1;
 157 };
 158
 159 union cvmx_pcsx_intx_reg {
 160         uint64_t u64;
 161         struct cvmx_pcsx_intx_reg_s {
 162                 uint64_t reserved_12_63:52;
 163                 uint64_t dup:1;
 164                 uint64_t sync_bad:1;
 165                 uint64_t an_bad:1;
 166                 uint64_t rxlock:1;
 167                 uint64_t rxbad:1;
 168                 uint64_t rxerr:1;
 169                 uint64_t txbad:1;
 170                 uint64_t txfifo:1;
 171                 uint64_t txfifu:1;
 172                 uint64_t an_err:1;
 173                 uint64_t xmit:1;
 174                 uint64_t lnkspd:1;
 175         } s;
 176         struct cvmx_pcsx_intx_reg_s cn52xx;
 177         struct cvmx_pcsx_intx_reg_s cn52xxp1;
 178         struct cvmx_pcsx_intx_reg_s cn56xx;
 179         struct cvmx_pcsx_intx_reg_s cn56xxp1;
 180 };
 181
 182 union cvmx_pcsx_linkx_timer_count_reg {
 183         uint64_t u64;
 184         struct cvmx_pcsx_linkx_timer_count_reg_s {
 185                 uint64_t reserved_16_63:48;
 186                 uint64_t count:16;
 187         } s;
 188         struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
 189         struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
 190         struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
 191         struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
 192 };
 193
 194 union cvmx_pcsx_log_anlx_reg {
 195         uint64_t u64;
 196         struct cvmx_pcsx_log_anlx_reg_s {
 197                 uint64_t reserved_4_63:60;
 198                 uint64_t lafifovfl:1;
 199                 uint64_t la_en:1;
 200                 uint64_t pkt_sz:2;
 201         } s;
 202         struct cvmx_pcsx_log_anlx_reg_s cn52xx;
 203         struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
 204         struct cvmx_pcsx_log_anlx_reg_s cn56xx;
 205         struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
 206 };
 207
 208 union cvmx_pcsx_miscx_ctl_reg {
 209         uint64_t u64;
 210         struct cvmx_pcsx_miscx_ctl_reg_s {
 211                 uint64_t reserved_13_63:51;
 212                 uint64_t sgmii:1;
 213                 uint64_t gmxeno:1;
 214                 uint64_t loopbck2:1;
 215                 uint64_t mac_phy:1;
 216                 uint64_t mode:1;
 217                 uint64_t an_ovrd:1;
 218                 uint64_t samp_pt:7;
 219         } s;
 220         struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
 221         struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
 222         struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
 223         struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
 224 };
 225
 226 union cvmx_pcsx_mrx_control_reg {
 227         uint64_t u64;
 228         struct cvmx_pcsx_mrx_control_reg_s {
 229                 uint64_t reserved_16_63:48;
 230                 uint64_t reset:1;
 231                 uint64_t loopbck1:1;
 232                 uint64_t spdlsb:1;
 233                 uint64_t an_en:1;
 234                 uint64_t pwr_dn:1;
 235                 uint64_t reserved_10_10:1;
 236                 uint64_t rst_an:1;
 237                 uint64_t dup:1;
 238                 uint64_t coltst:1;
 239                 uint64_t spdmsb:1;
 240                 uint64_t uni:1;
 241                 uint64_t reserved_0_4:5;
 242         } s;
 243         struct cvmx_pcsx_mrx_control_reg_s cn52xx;
 244         struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
 245         struct cvmx_pcsx_mrx_control_reg_s cn56xx;
 246         struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
 247 };
 248
 249 union cvmx_pcsx_mrx_status_reg {
 250         uint64_t u64;
 251         struct cvmx_pcsx_mrx_status_reg_s {
 252                 uint64_t reserved_16_63:48;
 253                 uint64_t hun_t4:1;
 254                 uint64_t hun_xfd:1;
 255                 uint64_t hun_xhd:1;
 256                 uint64_t ten_fd:1;
 257                 uint64_t ten_hd:1;
 258                 uint64_t hun_t2fd:1;
 259                 uint64_t hun_t2hd:1;
 260                 uint64_t ext_st:1;
 261                 uint64_t reserved_7_7:1;
 262                 uint64_t prb_sup:1;
 263                 uint64_t an_cpt:1;
 264                 uint64_t rm_flt:1;
 265                 uint64_t an_abil:1;
 266                 uint64_t lnk_st:1;
 267                 uint64_t reserved_1_1:1;
 268                 uint64_t extnd:1;
 269         } s;
 270         struct cvmx_pcsx_mrx_status_reg_s cn52xx;
 271         struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
 272         struct cvmx_pcsx_mrx_status_reg_s cn56xx;
 273         struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
 274 };
 275
 276 union cvmx_pcsx_rxx_states_reg {
 277         uint64_t u64;
 278         struct cvmx_pcsx_rxx_states_reg_s {
 279                 uint64_t reserved_16_63:48;
 280                 uint64_t rx_bad:1;
 281                 uint64_t rx_st:5;
 282                 uint64_t sync_bad:1;
 283                 uint64_t sync:4;
 284                 uint64_t an_bad:1;
 285                 uint64_t an_st:4;
 286         } s;
 287         struct cvmx_pcsx_rxx_states_reg_s cn52xx;
 288         struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
 289         struct cvmx_pcsx_rxx_states_reg_s cn56xx;
 290         struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
 291 };
 292
 293 union cvmx_pcsx_rxx_sync_reg {
 294         uint64_t u64;
 295         struct cvmx_pcsx_rxx_sync_reg_s {
 296                 uint64_t reserved_2_63:62;
 297                 uint64_t sync:1;
 298                 uint64_t bit_lock:1;
 299         } s;
 300         struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
 301         struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
 302         struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
 303         struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
 304 };
 305
 306 union cvmx_pcsx_sgmx_an_adv_reg {
 307         uint64_t u64;
 308         struct cvmx_pcsx_sgmx_an_adv_reg_s {
 309                 uint64_t reserved_16_63:48;
 310                 uint64_t link:1;
 311                 uint64_t ack:1;
 312                 uint64_t reserved_13_13:1;
 313                 uint64_t dup:1;
 314                 uint64_t speed:2;
 315                 uint64_t reserved_1_9:9;
 316                 uint64_t one:1;
 317         } s;
 318         struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
 319         struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
 320         struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
 321         struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
 322 };
 323
 324 union cvmx_pcsx_sgmx_lp_adv_reg {
 325         uint64_t u64;
 326         struct cvmx_pcsx_sgmx_lp_adv_reg_s {
 327                 uint64_t reserved_16_63:48;
 328                 uint64_t link:1;
 329                 uint64_t reserved_13_14:2;
 330                 uint64_t dup:1;
 331                 uint64_t speed:2;
 332                 uint64_t reserved_1_9:9;
 333                 uint64_t one:1;
 334         } s;
 335         struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
 336         struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
 337         struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
 338         struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
 339 };
 340
 341 union cvmx_pcsx_txx_states_reg {
 342         uint64_t u64;
 343         struct cvmx_pcsx_txx_states_reg_s {
 344                 uint64_t reserved_7_63:57;
 345                 uint64_t xmit:2;
 346                 uint64_t tx_bad:1;
 347                 uint64_t ord_st:4;
 348         } s;
 349         struct cvmx_pcsx_txx_states_reg_s cn52xx;
 350         struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
 351         struct cvmx_pcsx_txx_states_reg_s cn56xx;
 352         struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
 353 };
 354
 355 union cvmx_pcsx_tx_rxx_polarity_reg {
 356         uint64_t u64;
 357         struct cvmx_pcsx_tx_rxx_polarity_reg_s {
 358                 uint64_t reserved_4_63:60;
 359                 uint64_t rxovrd:1;
 360                 uint64_t autorxpl:1;
 361                 uint64_t rxplrt:1;
 362                 uint64_t txplrt:1;
 363         } s;
 364         struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
 365         struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
 366         struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
 367         struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
 368 };
 369
 370 #endif