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ASoC: Remove duplicate ADC/DAC widgets from wm_hubs.c
[linux/fpc-iii.git] / drivers / staging / rt2860 / rt28xx.h
blob6e71acb16dc3b610894ef504487addf87531a05e
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
28 rt28xx.h
29
30 Abstract:
31 RT28xx ASIC related definition & structures
32
33 Revision History:
34 Who When What
35 -------- ---------- ----------------------------------------------
36 Jan Lee Jan-3-2006 created for RT2860c
37 */
38
39 #ifndef __RT28XX_H__
40 #define __RT28XX_H__
41
42
43 //
44 // PCI registers - base address 0x0000
45 //
46 #define PCI_CFG 0x0000
47 #define PCI_EECTRL 0x0004
48 #define PCI_MCUCTRL 0x0008
49
50 #ifdef RT30xx
51 #define OPT_14 0x114
52
53 typedef int NTSTATUS;
54 #define RETRY_LIMIT 10
55 #define STATUS_SUCCESS 0x00
56 #define STATUS_UNSUCCESSFUL 0x01
57 #endif
58
59 //
60 // SCH/DMA registers - base address 0x0200
61 //
62 // INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
63 //
64 #define DMA_CSR0 0x200
65 #define INT_SOURCE_CSR 0x200
66 typedef union _INT_SOURCE_CSR_STRUC {
67 struct {
68 UINT32 RxDelayINT:1;
69 UINT32 TxDelayINT:1;
70 UINT32 RxDone:1;
71 UINT32 Ac0DmaDone:1;//4
72 UINT32 Ac1DmaDone:1;
73 UINT32 Ac2DmaDone:1;
74 UINT32 Ac3DmaDone:1;
75 UINT32 HccaDmaDone:1; // bit7
76 UINT32 MgmtDmaDone:1;
77 UINT32 MCUCommandINT:1;//bit 9
78 UINT32 RxTxCoherent:1;
79 UINT32 TBTTInt:1;
80 UINT32 PreTBTT:1;
81 UINT32 TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
82 UINT32 AutoWakeup:1;//bit14
83 UINT32 GPTimer:1;
84 UINT32 RxCoherent:1;//bit16
85 UINT32 TxCoherent:1;
86 UINT32 :14;
87 } field;
88 UINT32 word;
89 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
90
91 //
92 // INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF
93 //
94 #define INT_MASK_CSR 0x204
95 typedef union _INT_MASK_CSR_STRUC {
96 struct {
97 UINT32 RXDelay_INT_MSK:1;
98 UINT32 TxDelay:1;
99 UINT32 RxDone:1;
100 UINT32 Ac0DmaDone:1;
101 UINT32 Ac1DmaDone:1;
102 UINT32 Ac2DmaDone:1;
103 UINT32 Ac3DmaDone:1;
104 UINT32 HccaDmaDone:1;
105 UINT32 MgmtDmaDone:1;
106 UINT32 MCUCommandINT:1;
107 UINT32 :20;
108 UINT32 RxCoherent:1;
109 UINT32 TxCoherent:1;
110 } field;
111 UINT32 word;
112 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
113
114 #define WPDMA_GLO_CFG 0x208
115 typedef union _WPDMA_GLO_CFG_STRUC {
116 struct {
117 UINT32 EnableTxDMA:1;
118 UINT32 TxDMABusy:1;
119 UINT32 EnableRxDMA:1;
120 UINT32 RxDMABusy:1;
121 UINT32 WPDMABurstSIZE:2;
122 UINT32 EnTXWriteBackDDONE:1;
123 UINT32 BigEndian:1;
124 UINT32 RXHdrScater:8;
125 UINT32 HDR_SEG_LEN:16;
126 } field;
127 UINT32 word;
128 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
129
130 #define WPDMA_RST_IDX 0x20c
131 typedef union _WPDMA_RST_IDX_STRUC {
132 struct {
133 UINT32 RST_DTX_IDX0:1;
134 UINT32 RST_DTX_IDX1:1;
135 UINT32 RST_DTX_IDX2:1;
136 UINT32 RST_DTX_IDX3:1;
137 UINT32 RST_DTX_IDX4:1;
138 UINT32 RST_DTX_IDX5:1;
139 UINT32 rsv:10;
140 UINT32 RST_DRX_IDX0:1;
141 UINT32 :15;
142 } field;
143 UINT32 word;
144 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
145
146 #define DELAY_INT_CFG 0x0210
147 typedef union _DELAY_INT_CFG_STRUC {
148 struct {
149 UINT32 RXMAX_PTIME:8;
150 UINT32 RXMAX_PINT:7;
151 UINT32 RXDLY_INT_EN:1;
152 UINT32 TXMAX_PTIME:8;
153 UINT32 TXMAX_PINT:7;
154 UINT32 TXDLY_INT_EN:1;
155 } field;
156 UINT32 word;
157 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
158
159 #define WMM_AIFSN_CFG 0x0214
160 typedef union _AIFSN_CSR_STRUC {
161 struct {
162 UINT32 Aifsn0:4; // for AC_BE
163 UINT32 Aifsn1:4; // for AC_BK
164 UINT32 Aifsn2:4; // for AC_VI
165 UINT32 Aifsn3:4; // for AC_VO
166 UINT32 Rsv:16;
167 } field;
168 UINT32 word;
169 } AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
170
171 //
172 // CWMIN_CSR: CWmin for each EDCA AC
173 //
174 #define WMM_CWMIN_CFG 0x0218
175 typedef union _CWMIN_CSR_STRUC {
176 struct {
177 UINT32 Cwmin0:4; // for AC_BE
178 UINT32 Cwmin1:4; // for AC_BK
179 UINT32 Cwmin2:4; // for AC_VI
180 UINT32 Cwmin3:4; // for AC_VO
181 UINT32 Rsv:16;
182 } field;
183 UINT32 word;
184 } CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
185
186 //
187 // CWMAX_CSR: CWmin for each EDCA AC
188 //
189 #define WMM_CWMAX_CFG 0x021c
190 typedef union _CWMAX_CSR_STRUC {
191 struct {
192 UINT32 Cwmax0:4; // for AC_BE
193 UINT32 Cwmax1:4; // for AC_BK
194 UINT32 Cwmax2:4; // for AC_VI
195 UINT32 Cwmax3:4; // for AC_VO
196 UINT32 Rsv:16;
197 } field;
198 UINT32 word;
199 } CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
200
201 //
202 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
203 //
204 #define WMM_TXOP0_CFG 0x0220
205 typedef union _AC_TXOP_CSR0_STRUC {
206 struct {
207 USHORT Ac0Txop; // for AC_BK, in unit of 32us
208 USHORT Ac1Txop; // for AC_BE, in unit of 32us
209 } field;
210 UINT32 word;
211 } AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
212
213 //
214 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
215 //
216 #define WMM_TXOP1_CFG 0x0224
217 typedef union _AC_TXOP_CSR1_STRUC {
218 struct {
219 USHORT Ac2Txop; // for AC_VI, in unit of 32us
220 USHORT Ac3Txop; // for AC_VO, in unit of 32us
221 } field;
222 UINT32 word;
223 } AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
224
225 #define RINGREG_DIFF 0x10
226 #define GPIO_CTRL_CFG 0x0228 //MAC_CSR13
227 #define MCU_CMD_CFG 0x022c
228 #define TX_BASE_PTR0 0x0230 //AC_BK base address
229 #define TX_MAX_CNT0 0x0234
230 #define TX_CTX_IDX0 0x0238
231 #define TX_DTX_IDX0 0x023c
232 #define TX_BASE_PTR1 0x0240 //AC_BE base address
233 #define TX_MAX_CNT1 0x0244
234 #define TX_CTX_IDX1 0x0248
235 #define TX_DTX_IDX1 0x024c
236 #define TX_BASE_PTR2 0x0250 //AC_VI base address
237 #define TX_MAX_CNT2 0x0254
238 #define TX_CTX_IDX2 0x0258
239 #define TX_DTX_IDX2 0x025c
240 #define TX_BASE_PTR3 0x0260 //AC_VO base address
241 #define TX_MAX_CNT3 0x0264
242 #define TX_CTX_IDX3 0x0268
243 #define TX_DTX_IDX3 0x026c
244 #define TX_BASE_PTR4 0x0270 //HCCA base address
245 #define TX_MAX_CNT4 0x0274
246 #define TX_CTX_IDX4 0x0278
247 #define TX_DTX_IDX4 0x027c
248 #define TX_BASE_PTR5 0x0280 //MGMT base address
249 #define TX_MAX_CNT5 0x0284
250 #define TX_CTX_IDX5 0x0288
251 #define TX_DTX_IDX5 0x028c
252 #define TX_MGMTMAX_CNT TX_MAX_CNT5
253 #define TX_MGMTCTX_IDX TX_CTX_IDX5
254 #define TX_MGMTDTX_IDX TX_DTX_IDX5
255 #define RX_BASE_PTR 0x0290 //RX base address
256 #define RX_MAX_CNT 0x0294
257 #define RX_CRX_IDX 0x0298
258 #define RX_DRX_IDX 0x029c
259 #define USB_DMA_CFG 0x02a0
260
261 typedef union _USB_DMA_CFG_STRUC {
262 struct {
263 UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns
264 UINT32 RxBulkAggLmt:8; //Rx Bulk Aggregation Limit in unit of 256 bytes
265 UINT32 phyclear:1; //phy watch dog enable. write 1
266 UINT32 rsv:2;
267 UINT32 TxClear:1; //Clear USB DMA TX path
268 UINT32 TxopHalt:1; //Halt TXOP count down when TX buffer is full.
269 UINT32 RxBulkAggEn:1; //Enable Rx Bulk Aggregation
270 UINT32 RxBulkEn:1; //Enable USB DMA Rx
271 UINT32 TxBulkEn:1; //Enable USB DMA Tx
272 UINT32 EpoutValid:6; //OUT endpoint data valid
273 UINT32 RxBusy:1; //USB DMA RX FSM busy
274 UINT32 TxBusy:1; //USB DMA TX FSM busy
275 } field;
276 UINT32 word;
277 } USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
278
279 //
280 // 3 PBF registers
281 //
282 //
283 // Most are for debug. Driver doesn't touch PBF register.
284 #define PBF_SYS_CTRL 0x0400
285 #define PBF_CFG 0x0408
286 #define PBF_MAX_PCNT 0x040C
287 #define PBF_CTRL 0x0410
288 #define PBF_INT_STA 0x0414
289 #define PBF_INT_ENA 0x0418
290 #define TXRXQ_PCNT 0x0438
291 #define PBF_DBG 0x043c
292 #define PBF_CAP_CTRL 0x0440
293
294 #ifdef RT30xx
295 // eFuse registers
296 #define EFUSE_CTRL 0x0580
297 #define EFUSE_DATA0 0x0590
298 #define EFUSE_DATA1 0x0594
299 #define EFUSE_DATA2 0x0598
300 #define EFUSE_DATA3 0x059c
301 #define EFUSE_USAGE_MAP_START 0x2d0
302 #define EFUSE_USAGE_MAP_END 0x2fc
303 #define EFUSE_TAG 0x2fe
304 #define EFUSE_USAGE_MAP_SIZE 45
305
306 typedef union _EFUSE_CTRL_STRUC {
307 struct {
308 UINT32 EFSROM_AOUT:6;
309 UINT32 EFSROM_MODE:2;
310 UINT32 EFSROM_LDO_OFF_TIME:6;
311 UINT32 EFSROM_LDO_ON_TIME:2;
312 UINT32 EFSROM_AIN:10;
313 UINT32 RESERVED:4;
314 UINT32 EFSROM_KICK:1;
315 UINT32 SEL_EFUSE:1;
316 } field;
317 UINT32 word;
318 } EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC;
319
320 #define LDO_CFG0 0x05d4
321 #define GPIO_SWITCH 0x05dc
322 #endif /* RT30xx */
323
324 //
325 // 4 MAC registers
326 //
327 //
328 // 4.1 MAC SYSTEM configuration registers (offset:0x1000)
329 //
330 #define MAC_CSR0 0x1000
331 typedef union _ASIC_VER_ID_STRUC {
332 struct {
333 USHORT ASICRev; // reversion : 0
334 USHORT ASICVer; // version : 2860
335 } field;
336 UINT32 word;
337 } ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
338
339 #define MAC_SYS_CTRL 0x1004 //MAC_CSR1
340 #define MAC_ADDR_DW0 0x1008 // MAC ADDR DW0
341 #define MAC_ADDR_DW1 0x100c // MAC ADDR DW1
342 //
343 // MAC_CSR2: STA MAC register 0
344 //
345 typedef union _MAC_DW0_STRUC {
346 struct {
347 UCHAR Byte0; // MAC address byte 0
348 UCHAR Byte1; // MAC address byte 1
349 UCHAR Byte2; // MAC address byte 2
350 UCHAR Byte3; // MAC address byte 3
351 } field;
352 UINT32 word;
353 } MAC_DW0_STRUC, *PMAC_DW0_STRUC;
354
355 //
356 // MAC_CSR3: STA MAC register 1
357 //
358 typedef union _MAC_DW1_STRUC {
359 struct {
360 UCHAR Byte4; // MAC address byte 4
361 UCHAR Byte5; // MAC address byte 5
362 UCHAR U2MeMask;
363 UCHAR Rsvd1;
364 } field;
365 UINT32 word;
366 } MAC_DW1_STRUC, *PMAC_DW1_STRUC;
367
368 #define MAC_BSSID_DW0 0x1010 // MAC BSSID DW0
369 #define MAC_BSSID_DW1 0x1014 // MAC BSSID DW1
370
371 //
372 // MAC_CSR5: BSSID register 1
373 //
374 typedef union _MAC_CSR5_STRUC {
375 struct {
376 UCHAR Byte4; // BSSID byte 4
377 UCHAR Byte5; // BSSID byte 5
378 USHORT BssIdMask:2; // 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID
379 USHORT MBssBcnNum:3;
380 USHORT Rsvd:11;
381 } field;
382 UINT32 word;
383 } MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
384
385 #define MAX_LEN_CFG 0x1018 // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
386 #define BBP_CSR_CFG 0x101c //
387 //
388 // BBP_CSR_CFG: BBP serial control register
389 //
390 typedef union _BBP_CSR_CFG_STRUC {
391 struct {
392 UINT32 Value:8; // Register value to program into BBP
393 UINT32 RegNum:8; // Selected BBP register
394 UINT32 fRead:1; // 0: Write BBP, 1: Read BBP
395 UINT32 Busy:1; // 1: ASIC is busy execute BBP programming.
396 UINT32 BBP_PAR_DUR:1; // 0: 4 MAC clock cycles 1: 8 MAC clock cycles
397 UINT32 BBP_RW_MODE:1; // 0: use serial mode 1:parallel
398 UINT32 :12;
399 } field;
400 UINT32 word;
401 } BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
402
403 #define RF_CSR_CFG0 0x1020
404 //
405 // RF_CSR_CFG: RF control register
406 //
407 typedef union _RF_CSR_CFG0_STRUC {
408 struct {
409 UINT32 RegIdAndContent:24; // Register value to program into BBP
410 UINT32 bitwidth:5; // Selected BBP register
411 UINT32 StandbyMode:1; // 0: high when stand by 1: low when standby
412 UINT32 Sel:1; // 0:RF_LE0 activate 1:RF_LE1 activate
413 UINT32 Busy:1; // 0: idle 1: 8busy
414 } field;
415 UINT32 word;
416 } RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
417
418 #define RF_CSR_CFG1 0x1024
419 typedef union _RF_CSR_CFG1_STRUC {
420 struct {
421 UINT32 RegIdAndContent:24; // Register value to program into BBP
422 UINT32 RFGap:5; // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
423 UINT32 rsv:7; // 0: idle 1: 8busy
424 } field;
425 UINT32 word;
426 } RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
427
428 #define RF_CSR_CFG2 0x1028 //
429 typedef union _RF_CSR_CFG2_STRUC {
430 struct {
431 UINT32 RegIdAndContent:24; // Register value to program into BBP
432 UINT32 rsv:8; // 0: idle 1: 8busy
433 } field;
434 UINT32 word;
435 } RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
436
437 #define LED_CFG 0x102c // MAC_CSR14
438 typedef union _LED_CFG_STRUC {
439 struct {
440 UINT32 OnPeriod:8; // blinking on period unit 1ms
441 UINT32 OffPeriod:8; // blinking off period unit 1ms
442 UINT32 SlowBlinkPeriod:6; // slow blinking period. unit:1ms
443 UINT32 rsv:2;
444 UINT32 RLedMode:2; // red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on
445 UINT32 GLedMode:2; // green Led Mode
446 UINT32 YLedMode:2; // yellow Led Mode
447 UINT32 LedPolar:1; // Led Polarity. 0: active low1: active high
448 UINT32 :1;
449 } field;
450 UINT32 word;
451 } LED_CFG_STRUC, *PLED_CFG_STRUC;
452
453 //
454 // 4.2 MAC TIMING configuration registers (offset:0x1100)
455 //
456 #define XIFS_TIME_CFG 0x1100 // MAC_CSR8 MAC_CSR9
457 typedef union _IFS_SLOT_CFG_STRUC {
458 struct {
459 UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX
460 UINT32 OfdmSifsTime:8; // unit 1us. Applied after OFDM RX/TX
461 UINT32 OfdmXifsTime:4; //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
462 UINT32 EIFS:9; // unit 1us
463 UINT32 BBRxendEnable:1; // reference RXEND signal to begin XIFS defer
464 UINT32 rsv:2;
465 } field;
466 UINT32 word;
467 } IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
468
469 #define BKOFF_SLOT_CFG 0x1104 // mac_csr9 last 8 bits
470 #define NAV_TIME_CFG 0x1108 // NAV (MAC_CSR15)
471 #define CH_TIME_CFG 0x110C // Count as channel busy
472 #define PBF_LIFE_TIMER 0x1110 //TX/RX MPDU timestamp timer (free run)Unit: 1us
473 #define BCN_TIME_CFG 0x1114 // TXRX_CSR9
474
475 #define BCN_OFFSET0 0x042C
476 #define BCN_OFFSET1 0x0430
477
478 //
479 // BCN_TIME_CFG : Synchronization control register
480 //
481 typedef union _BCN_TIME_CFG_STRUC {
482 struct {
483 UINT32 BeaconInterval:16; // in unit of 1/16 TU
484 UINT32 bTsfTicking:1; // Enable TSF auto counting
485 UINT32 TsfSyncMode:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
486 UINT32 bTBTTEnable:1;
487 UINT32 bBeaconGen:1; // Enable beacon generator
488 UINT32 :3;
489 UINT32 TxTimestampCompensate:8;
490 } field;
491 UINT32 word;
492 } BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
493
494 #define TBTT_SYNC_CFG 0x1118 // txrx_csr10
495 #define TSF_TIMER_DW0 0x111C // Local TSF timer lsb 32 bits. Read-only
496 #define TSF_TIMER_DW1 0x1120 // msb 32 bits. Read-only.
497 #define TBTT_TIMER 0x1124 // TImer remains till next TBTT. Read-only. TXRX_CSR14
498 #define INT_TIMER_CFG 0x1128 //
499 #define INT_TIMER_EN 0x112c // GP-timer and pre-tbtt Int enable
500 #define CH_IDLE_STA 0x1130 // channel idle time
501 #define CH_BUSY_STA 0x1134 // channle busy time
502 //
503 // 4.2 MAC POWER configuration registers (offset:0x1200)
504 //
505 #define MAC_STATUS_CFG 0x1200 // old MAC_CSR12
506 #define PWR_PIN_CFG 0x1204 // old MAC_CSR12
507 #define AUTO_WAKEUP_CFG 0x1208 // old MAC_CSR10
508 //
509 // AUTO_WAKEUP_CFG: Manual power control / status register
510 //
511 typedef union _AUTO_WAKEUP_STRUC {
512 struct {
513 UINT32 AutoLeadTime:8;
514 UINT32 NumofSleepingTbtt:7; // ForceWake has high privilege than PutToSleep when both set
515 UINT32 EnableAutoWakeup:1; // 0:sleep, 1:awake
516 UINT32 :16;
517 } field;
518 UINT32 word;
519 } AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
520
521 //
522 // 4.3 MAC TX configuration registers (offset:0x1300)
523 //
524
525 #define EDCA_AC0_CFG 0x1300 //AC_TXOP_CSR0 0x3474
526 #define EDCA_AC1_CFG 0x1304
527 #define EDCA_AC2_CFG 0x1308
528 #define EDCA_AC3_CFG 0x130c
529 typedef union _EDCA_AC_CFG_STRUC {
530 struct {
531 UINT32 AcTxop:8; // in unit of 32us
532 UINT32 Aifsn:4; // # of slot time
533 UINT32 Cwmin:4; //
534 UINT32 Cwmax:4; //unit power of 2
535 UINT32 :12; //
536 } field;
537 UINT32 word;
538 } EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
539
540 #define EDCA_TID_AC_MAP 0x1310
541 #define TX_PWR_CFG_0 0x1314
542 #define TX_PWR_CFG_1 0x1318
543 #define TX_PWR_CFG_2 0x131C
544 #define TX_PWR_CFG_3 0x1320
545 #define TX_PWR_CFG_4 0x1324
546 #define TX_PIN_CFG 0x1328
547 #define TX_BAND_CFG 0x132c // 0x1 use upper 20MHz. 0 juse lower 20MHz
548 #define TX_SW_CFG0 0x1330
549 #define TX_SW_CFG1 0x1334
550 #define TX_SW_CFG2 0x1338
551 #define TXOP_THRES_CFG 0x133c
552 #define TXOP_CTRL_CFG 0x1340
553 #define TX_RTS_CFG 0x1344
554
555 typedef union _TX_RTS_CFG_STRUC {
556 struct {
557 UINT32 AutoRtsRetryLimit:8;
558 UINT32 RtsThres:16; // unit:byte
559 UINT32 RtsFbkEn:1; // enable rts rate fallback
560 UINT32 rsv:7; // 1: HT non-STBC control frame enable
561 } field;
562 UINT32 word;
563 } TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
564
565 #define TX_TIMEOUT_CFG 0x1348
566 typedef union _TX_TIMEOUT_CFG_STRUC {
567 struct {
568 UINT32 rsv:4;
569 UINT32 MpduLifeTime:4; // expiration time = 2^(9+MPDU LIFE TIME) us
570 UINT32 RxAckTimeout:8; // unit:slot. Used for TX precedure
571 UINT32 TxopTimeout:8; //TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
572 UINT32 rsv2:8; // 1: HT non-STBC control frame enable
573 } field;
574 UINT32 word;
575 } TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
576
577 #define TX_RTY_CFG 0x134c
578 typedef union PACKED _TX_RTY_CFG_STRUC {
579 struct {
580 UINT32 ShortRtyLimit:8; // short retry limit
581 UINT32 LongRtyLimit:8; //long retry limit
582 UINT32 LongRtyThre:12; // Long retry threshoold
583 UINT32 NonAggRtyMode:1; // Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
584 UINT32 AggRtyMode:1; // Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
585 UINT32 TxautoFBEnable:1; // Tx retry PHY rate auto fallback enable
586 UINT32 rsv:1; // 1: HT non-STBC control frame enable
587 } field;
588 UINT32 word;
589 } TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
590
591 #define TX_LINK_CFG 0x1350
592 typedef union PACKED _TX_LINK_CFG_STRUC {
593 struct PACKED {
594 UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us
595 UINT32 MFBEnable:1; // TX apply remote MFB 1:enable
596 UINT32 RemoteUMFSEnable:1; // remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7)
597 UINT32 TxMRQEn:1; // MCS request TX enable
598 UINT32 TxRDGEn:1; // RDG TX enable
599 UINT32 TxCFAckEn:1; // Piggyback CF-ACK enable
600 UINT32 rsv:3; //
601 UINT32 RemotMFB:8; // remote MCS feedback
602 UINT32 RemotMFS:8; //remote MCS feedback sequence number
603 } field;
604 UINT32 word;
605 } TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
606
607 #define HT_FBK_CFG0 0x1354
608 typedef union PACKED _HT_FBK_CFG0_STRUC {
609 struct {
610 UINT32 HTMCS0FBK:4;
611 UINT32 HTMCS1FBK:4;
612 UINT32 HTMCS2FBK:4;
613 UINT32 HTMCS3FBK:4;
614 UINT32 HTMCS4FBK:4;
615 UINT32 HTMCS5FBK:4;
616 UINT32 HTMCS6FBK:4;
617 UINT32 HTMCS7FBK:4;
618 } field;
619 UINT32 word;
620 } HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
621
622 #define HT_FBK_CFG1 0x1358
623 typedef union _HT_FBK_CFG1_STRUC {
624 struct {
625 UINT32 HTMCS8FBK:4;
626 UINT32 HTMCS9FBK:4;
627 UINT32 HTMCS10FBK:4;
628 UINT32 HTMCS11FBK:4;
629 UINT32 HTMCS12FBK:4;
630 UINT32 HTMCS13FBK:4;
631 UINT32 HTMCS14FBK:4;
632 UINT32 HTMCS15FBK:4;
633 } field;
634 UINT32 word;
635 } HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
636
637 #define LG_FBK_CFG0 0x135c
638 typedef union _LG_FBK_CFG0_STRUC {
639 struct {
640 UINT32 OFDMMCS0FBK:4; //initial value is 0
641 UINT32 OFDMMCS1FBK:4; //initial value is 0
642 UINT32 OFDMMCS2FBK:4; //initial value is 1
643 UINT32 OFDMMCS3FBK:4; //initial value is 2
644 UINT32 OFDMMCS4FBK:4; //initial value is 3
645 UINT32 OFDMMCS5FBK:4; //initial value is 4
646 UINT32 OFDMMCS6FBK:4; //initial value is 5
647 UINT32 OFDMMCS7FBK:4; //initial value is 6
648 } field;
649 UINT32 word;
650 } LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
651
652 #define LG_FBK_CFG1 0x1360
653 typedef union _LG_FBK_CFG1_STRUC {
654 struct {
655 UINT32 CCKMCS0FBK:4; //initial value is 0
656 UINT32 CCKMCS1FBK:4; //initial value is 0
657 UINT32 CCKMCS2FBK:4; //initial value is 1
658 UINT32 CCKMCS3FBK:4; //initial value is 2
659 UINT32 rsv:16;
660 } field;
661 UINT32 word;
662 } LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
663
664 //=======================================================
665 //================ Protection Paramater================================
666 //=======================================================
667 #define CCK_PROT_CFG 0x1364 //CCK Protection
668 #define ASIC_SHORTNAV 1
669 #define ASIC_LONGNAV 2
670 #define ASIC_RTS 1
671 #define ASIC_CTS 2
672 typedef union _PROT_CFG_STRUC {
673 struct {
674 UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
675 UINT32 ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
676 UINT32 ProtectNav:2; //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv
677 UINT32 TxopAllowCck:1; //CCK TXOP allowance.0:disallow.
678 UINT32 TxopAllowOfdm:1; //CCK TXOP allowance.0:disallow.
679 UINT32 TxopAllowMM20:1; //CCK TXOP allowance. 0:disallow.
680 UINT32 TxopAllowMM40:1; //CCK TXOP allowance.0:disallow.
681 UINT32 TxopAllowGF20:1; //CCK TXOP allowance.0:disallow.
682 UINT32 TxopAllowGF40:1; //CCK TXOP allowance.0:disallow.
683 UINT32 RTSThEn:1; //RTS threshold enable on CCK TX
684 UINT32 rsv:5;
685 } field;
686 UINT32 word;
687 } PROT_CFG_STRUC, *PPROT_CFG_STRUC;
688
689 #define OFDM_PROT_CFG 0x1368 //OFDM Protection
690 #define MM20_PROT_CFG 0x136C //MM20 Protection
691 #define MM40_PROT_CFG 0x1370 //MM40 Protection
692 #define GF20_PROT_CFG 0x1374 //GF20 Protection
693 #define GF40_PROT_CFG 0x1378 //GR40 Protection
694 #define EXP_CTS_TIME 0x137C //
695 #define EXP_ACK_TIME 0x1380 //
696
697 //
698 // 4.4 MAC RX configuration registers (offset:0x1400)
699 //
700 #define RX_FILTR_CFG 0x1400 //TXRX_CSR0
701 #define AUTO_RSP_CFG 0x1404 //TXRX_CSR4
702 //
703 // TXRX_CSR4: Auto-Responder/
704 //
705 typedef union _AUTO_RSP_CFG_STRUC {
706 struct {
707 UINT32 AutoResponderEnable:1;
708 UINT32 BACAckPolicyEnable:1; // 0:long, 1:short preamble
709 UINT32 CTS40MMode:1; // Response CTS 40MHz duplicate mode
710 UINT32 CTS40MRef:1; // Response CTS 40MHz duplicate mode
711 UINT32 AutoResponderPreamble:1; // 0:long, 1:short preamble
712 UINT32 rsv:1; // Power bit value in conrtrol frame
713 UINT32 DualCTSEn:1; // Power bit value in conrtrol frame
714 UINT32 AckCtsPsmBit:1; // Power bit value in conrtrol frame
715 UINT32 :24;
716 } field;
717 UINT32 word;
718 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
719
720 #define LEGACY_BASIC_RATE 0x1408 // TXRX_CSR5 0x3054
721 #define HT_BASIC_RATE 0x140c
722 #define HT_CTRL_CFG 0x1410
723 #define SIFS_COST_CFG 0x1414
724 #define RX_PARSER_CFG 0x1418 //Set NAV for all received frames
725
726 //
727 // 4.5 MAC Security configuration (offset:0x1500)
728 //
729 #define TX_SEC_CNT0 0x1500 //
730 #define RX_SEC_CNT0 0x1504 //
731 #define CCMP_FC_MUTE 0x1508 //
732 //
733 // 4.6 HCCA/PSMP (offset:0x1600)
734 //
735 #define TXOP_HLDR_ADDR0 0x1600
736 #define TXOP_HLDR_ADDR1 0x1604
737 #define TXOP_HLDR_ET 0x1608
738 #define QOS_CFPOLL_RA_DW0 0x160c
739 #define QOS_CFPOLL_A1_DW1 0x1610
740 #define QOS_CFPOLL_QC 0x1614
741 //
742 // 4.7 MAC Statistis registers (offset:0x1700)
743 //
744 #define RX_STA_CNT0 0x1700 //
745 #define RX_STA_CNT1 0x1704 //
746 #define RX_STA_CNT2 0x1708 //
747
748 //
749 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
750 //
751 typedef union _RX_STA_CNT0_STRUC {
752 struct {
753 USHORT CrcErr;
754 USHORT PhyErr;
755 } field;
756 UINT32 word;
757 } RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
758
759 //
760 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
761 //
762 typedef union _RX_STA_CNT1_STRUC {
763 struct {
764 USHORT FalseCca;
765 USHORT PlcpErr;
766 } field;
767 UINT32 word;
768 } RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
769
770 //
771 // RX_STA_CNT2_STRUC:
772 //
773 typedef union _RX_STA_CNT2_STRUC {
774 struct {
775 USHORT RxDupliCount;
776 USHORT RxFifoOverflowCount;
777 } field;
778 UINT32 word;
779 } RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
780
781 #define TX_STA_CNT0 0x170C //
782 //
783 // STA_CSR3: TX Beacon count
784 //
785 typedef union _TX_STA_CNT0_STRUC {
786 struct {
787 USHORT TxFailCount;
788 USHORT TxBeaconCount;
789 } field;
790 UINT32 word;
791 } TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
792
793 #define TX_STA_CNT1 0x1710 //
794 //
795 // TX_STA_CNT1: TX tx count
796 //
797 typedef union _TX_STA_CNT1_STRUC {
798 struct {
799 USHORT TxSuccess;
800 USHORT TxRetransmit;
801 } field;
802 UINT32 word;
803 } TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
804
805 #define TX_STA_CNT2 0x1714 //
806 //
807 // TX_STA_CNT2: TX tx count
808 //
809 typedef union _TX_STA_CNT2_STRUC {
810 struct {
811 USHORT TxZeroLenCount;
812 USHORT TxUnderFlowCount;
813 } field;
814 UINT32 word;
815 } TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
816
817 #define TX_STA_FIFO 0x1718 //
818 //
819 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
820 //
821 typedef union PACKED _TX_STA_FIFO_STRUC {
822 struct {
823 UINT32 bValid:1; // 1:This register contains a valid TX result
824 UINT32 PidType:4;
825 UINT32 TxSuccess:1; // Tx No retry success
826 UINT32 TxAggre:1; // Tx Retry Success
827 UINT32 TxAckRequired:1; // Tx fail
828 UINT32 wcid:8; //wireless client index
829 // UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
830 UINT32 SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
831 UINT32 TxBF:1;
832 UINT32 Reserve:2;
833 } field;
834 UINT32 word;
835 } TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
836
837 // Debug counter
838 #define TX_AGG_CNT 0x171c
839 typedef union _TX_AGG_CNT_STRUC {
840 struct {
841 USHORT NonAggTxCount;
842 USHORT AggTxCount;
843 } field;
844 UINT32 word;
845 } TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
846
847 // Debug counter
848 #define TX_AGG_CNT0 0x1720
849 typedef union _TX_AGG_CNT0_STRUC {
850 struct {
851 USHORT AggSize1Count;
852 USHORT AggSize2Count;
853 } field;
854 UINT32 word;
855 } TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
856
857 // Debug counter
858 #define TX_AGG_CNT1 0x1724
859 typedef union _TX_AGG_CNT1_STRUC {
860 struct {
861 USHORT AggSize3Count;
862 USHORT AggSize4Count;
863 } field;
864 UINT32 word;
865 } TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
866
867 #define TX_AGG_CNT2 0x1728
868 typedef union _TX_AGG_CNT2_STRUC {
869 struct {
870 USHORT AggSize5Count;
871 USHORT AggSize6Count;
872 } field;
873 UINT32 word;
874 } TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
875
876 // Debug counter
877 #define TX_AGG_CNT3 0x172c
878 typedef union _TX_AGG_CNT3_STRUC {
879 struct {
880 USHORT AggSize7Count;
881 USHORT AggSize8Count;
882 } field;
883 UINT32 word;
884 } TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
885
886 // Debug counter
887 #define TX_AGG_CNT4 0x1730
888 typedef union _TX_AGG_CNT4_STRUC {
889 struct {
890 USHORT AggSize9Count;
891 USHORT AggSize10Count;
892 } field;
893 UINT32 word;
894 } TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
895
896 #define TX_AGG_CNT5 0x1734
897 typedef union _TX_AGG_CNT5_STRUC {
898 struct {
899 USHORT AggSize11Count;
900 USHORT AggSize12Count;
901 } field;
902 UINT32 word;
903 } TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
904
905 #define TX_AGG_CNT6 0x1738
906 typedef union _TX_AGG_CNT6_STRUC {
907 struct {
908 USHORT AggSize13Count;
909 USHORT AggSize14Count;
910 } field;
911 UINT32 word;
912 } TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
913
914 #define TX_AGG_CNT7 0x173c
915 typedef union _TX_AGG_CNT7_STRUC {
916 struct {
917 USHORT AggSize15Count;
918 USHORT AggSize16Count;
919 } field;
920 UINT32 word;
921 } TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
922
923 #define MPDU_DENSITY_CNT 0x1740
924 typedef union _MPDU_DEN_CNT_STRUC {
925 struct {
926 USHORT TXZeroDelCount; //TX zero length delimiter count
927 USHORT RXZeroDelCount; //RX zero length delimiter count
928 } field;
929 UINT32 word;
930 } MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
931
932 //
933 // TXRX control registers - base address 0x3000
934 //
935 // rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
936 #define TXRX_CSR1 0x77d0
937
938 //
939 // Security key table memory, base address = 0x1000
940 //
941 #define MAC_WCID_BASE 0x1800 //8-bytes(use only 6-bytes) * 256 entry =
942 #define HW_WCID_ENTRY_SIZE 8
943 #define PAIRWISE_KEY_TABLE_BASE 0x4000 // 32-byte * 256-entry = -byte
944 #define HW_KEY_ENTRY_SIZE 0x20
945 #define PAIRWISE_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
946 #define MAC_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
947 #define HW_IVEIV_ENTRY_SIZE 8
948 #define MAC_WCID_ATTRIBUTE_BASE 0x6800 // 4-byte * 256-entry = -byte
949 #define HW_WCID_ATTRI_SIZE 4
950 #define WCID_RESERVED 0x6bfc
951 #define SHARED_KEY_TABLE_BASE 0x6c00 // 32-byte * 16-entry = 512-byte
952 #define SHARED_KEY_MODE_BASE 0x7000 // 32-byte * 16-entry = 512-byte
953 #define HW_SHARED_KEY_MODE_SIZE 4
954 #define SHAREDKEYTABLE 0
955 #define PAIRWISEKEYTABLE 1
956
957 typedef union _SHAREDKEY_MODE_STRUC {
958 struct {
959 UINT32 Bss0Key0CipherAlg:3;
960 UINT32 :1;
961 UINT32 Bss0Key1CipherAlg:3;
962 UINT32 :1;
963 UINT32 Bss0Key2CipherAlg:3;
964 UINT32 :1;
965 UINT32 Bss0Key3CipherAlg:3;
966 UINT32 :1;
967 UINT32 Bss1Key0CipherAlg:3;
968 UINT32 :1;
969 UINT32 Bss1Key1CipherAlg:3;
970 UINT32 :1;
971 UINT32 Bss1Key2CipherAlg:3;
972 UINT32 :1;
973 UINT32 Bss1Key3CipherAlg:3;
974 UINT32 :1;
975 } field;
976 UINT32 word;
977 } SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
978
979 // 64-entry for pairwise key table
980 typedef struct _HW_WCID_ENTRY { // 8-byte per entry
981 UCHAR Address[6];
982 UCHAR Rsv[2];
983 } HW_WCID_ENTRY, PHW_WCID_ENTRY;
984
985
986
987 //
988 // Other on-chip shared memory space, base = 0x2000
989 //
990
991 // CIS space - base address = 0x2000
992 #define HW_CIS_BASE 0x2000
993
994 // Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
995 #define HW_CS_CTS_BASE 0x7700
996 // DFS CTS frame base address. It's where mac stores CTS frame for DFS.
997 #define HW_DFS_CTS_BASE 0x7780
998 #define HW_CTS_FRAME_SIZE 0x80
999
1000 // 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
1001 // to save debugging settings
1002 #define HW_DEBUG_SETTING_BASE 0x77f0 // 0x77f0~0x77ff total 16 bytes
1003 #define HW_DEBUG_SETTING_BASE2 0x7770 // 0x77f0~0x77ff total 16 bytes
1004
1005 // In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
1006 // Three section discontinue memory segments will be used.
1007 // 1. The original region for BCN 0~3
1008 // 2. Extract memory from FCE table for BCN 4~5
1009 // 3. Extract memory from Pair-wise key table for BCN 6~7
1010 // It occupied those memory of wcid 238~253 for BCN 6
1011 // and wcid 222~237 for BCN 7
1012 #define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
1013 #define HW_BEACON_BASE0 0x7800
1014 #define HW_BEACON_BASE1 0x7A00
1015 #define HW_BEACON_BASE2 0x7C00
1016 #define HW_BEACON_BASE3 0x7E00
1017 #define HW_BEACON_BASE4 0x7200
1018 #define HW_BEACON_BASE5 0x7400
1019 #define HW_BEACON_BASE6 0x5DC0
1020 #define HW_BEACON_BASE7 0x5BC0
1021
1022 #define HW_BEACON_MAX_COUNT 8
1023 #define HW_BEACON_OFFSET 0x0200
1024 #define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
1025
1026 // HOST-MCU shared memory - base address = 0x2100
1027 #define HOST_CMD_CSR 0x404
1028 #define H2M_MAILBOX_CSR 0x7010
1029 #define H2M_MAILBOX_CID 0x7014
1030 #define H2M_MAILBOX_STATUS 0x701c
1031 #define H2M_INT_SRC 0x7024
1032 #define H2M_BBP_AGENT 0x7028
1033 #define M2H_CMD_DONE_CSR 0x000c
1034 #define MCU_TXOP_ARRAY_BASE 0x000c // TODO: to be provided by Albert
1035 #define MCU_TXOP_ENTRY_SIZE 32 // TODO: to be provided by Albert
1036 #define MAX_NUM_OF_TXOP_ENTRY 16 // TODO: must be same with 8051 firmware
1037 #define MCU_MBOX_VERSION 0x01 // TODO: to be confirmed by Albert
1038 #define MCU_MBOX_VERSION_OFFSET 5 // TODO: to be provided by Albert
1039
1040 //
1041 // Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
1042 //
1043 //
1044 // DMA RING DESCRIPTOR
1045 //
1046 #define E2PROM_CSR 0x0004
1047 #define IO_CNTL_CSR 0x77d0
1048
1049 #ifdef RT2860
1050 // 8051 firmware image for RT2860 - base address = 0x4000
1051 #define FIRMWARE_IMAGE_BASE 0x2000
1052 #define MAX_FIRMWARE_IMAGE_SIZE 0x2000 // 8kbyte
1053 #endif
1054 #ifdef RT2870
1055 // 8051 firmware image for usb - use last-half base address = 0x3000
1056 #define FIRMWARE_IMAGE_BASE 0x3000
1057 #define MAX_FIRMWARE_IMAGE_SIZE 0x1000 // 4kbyte
1058 #endif // RT2870 //
1059
1060 // ================================================================
1061 // Tx / Rx / Mgmt ring descriptor definition
1062 // ================================================================
1063
1064 // the following PID values are used to mark outgoing frame type in TXD->PID so that
1065 // proper TX statistics can be collected based on these categories
1066 // b3-2 of PID field -
1067 #define PID_MGMT 0x05
1068 #define PID_BEACON 0x0c
1069 #define PID_DATA_NORMALUCAST 0x02
1070 #define PID_DATA_AMPDU 0x04
1071 #define PID_DATA_NO_ACK 0x08
1072 #define PID_DATA_NOT_NORM_ACK 0x03
1073 // value domain of pTxD->HostQId (4-bit: 0~15)
1074 #define QID_AC_BK 1 // meet ACI definition in 802.11e
1075 #define QID_AC_BE 0 // meet ACI definition in 802.11e
1076 #define QID_AC_VI 2
1077 #define QID_AC_VO 3
1078 #define QID_HCCA 4
1079 #define NUM_OF_TX_RING 5
1080 #define QID_MGMT 13
1081 #define QID_RX 14
1082 #define QID_OTHER 15
1083
1084
1085 // ------------------------------------------------------
1086 // BBP & RF definition
1087 // ------------------------------------------------------
1088 #define BUSY 1
1089 #define IDLE 0
1090
1091 #define RF_R00 0
1092 #define RF_R01 1
1093 #define RF_R02 2
1094 #define RF_R03 3
1095 #define RF_R04 4
1096 #define RF_R05 5
1097 #define RF_R06 6
1098 #define RF_R07 7
1099 #define RF_R08 8
1100 #define RF_R09 9
1101 #define RF_R10 10
1102 #define RF_R11 11
1103 #define RF_R12 12
1104 #define RF_R13 13
1105 #define RF_R14 14
1106 #define RF_R15 15
1107 #define RF_R16 16
1108 #define RF_R17 17
1109 #define RF_R18 18
1110 #define RF_R19 19
1111 #define RF_R20 20
1112 #define RF_R21 21
1113 #define RF_R22 22
1114 #define RF_R23 23
1115 #define RF_R24 24
1116 #define RF_R25 25
1117 #define RF_R26 26
1118 #define RF_R27 27
1119 #define RF_R28 28
1120 #define RF_R29 29
1121 #define RF_R30 30
1122 #define RF_R31 31
1123
1124 #define BBP_R0 0 // version
1125 #define BBP_R1 1 // TSSI
1126 #define BBP_R2 2 // TX configure
1127 #define BBP_R3 3
1128 #define BBP_R4 4
1129 #define BBP_R5 5
1130 #define BBP_R6 6
1131 #define BBP_R14 14 // RX configure
1132 #define BBP_R16 16
1133 #define BBP_R17 17 // RX sensibility
1134 #define BBP_R18 18
1135 #define BBP_R21 21
1136 #define BBP_R22 22
1137 #define BBP_R24 24
1138 #define BBP_R25 25
1139 #ifdef RT30xx
1140 #define BBP_R31 31
1141 #endif
1142 #define BBP_R49 49 //TSSI
1143 #define BBP_R50 50
1144 #define BBP_R51 51
1145 #define BBP_R52 52
1146 #define BBP_R55 55
1147 #define BBP_R62 62 // Rx SQ0 Threshold HIGH
1148 #define BBP_R63 63
1149 #define BBP_R64 64
1150 #define BBP_R65 65
1151 #define BBP_R66 66
1152 #define BBP_R67 67
1153 #define BBP_R68 68
1154 #define BBP_R69 69
1155 #define BBP_R70 70 // Rx AGC SQ CCK Xcorr threshold
1156 #define BBP_R73 73
1157 #define BBP_R75 75
1158 #define BBP_R77 77
1159 #ifdef RT30xx
1160 #define BBP_R79 79
1161 #define BBP_R80 80
1162 #endif
1163 #define BBP_R81 81
1164 #define BBP_R82 82
1165 #define BBP_R83 83
1166 #define BBP_R84 84
1167 #define BBP_R86 86
1168 #define BBP_R91 91
1169 #define BBP_R92 92
1170 #define BBP_R94 94 // Tx Gain Control
1171 #define BBP_R103 103
1172 #define BBP_R105 105
1173 #define BBP_R113 113
1174 #define BBP_R114 114
1175 #define BBP_R115 115
1176 #define BBP_R116 116
1177 #define BBP_R117 117
1178 #define BBP_R118 118
1179 #define BBP_R119 119
1180 #define BBP_R120 120
1181 #define BBP_R121 121
1182 #define BBP_R122 122
1183 #define BBP_R123 123
1184 #ifdef RT30xx
1185 #define BBP_R138 138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
1186 #endif // RT30xx //
1187
1188
1189 #define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
1190
1191 #define RSSI_FOR_VERY_LOW_SENSIBILITY -35
1192 #define RSSI_FOR_LOW_SENSIBILITY -58
1193 #define RSSI_FOR_MID_LOW_SENSIBILITY -80
1194 #define RSSI_FOR_MID_SENSIBILITY -90
1195
1196 //-------------------------------------------------------------------------
1197 // EEPROM definition
1198 //-------------------------------------------------------------------------
1199 #define EEDO 0x08
1200 #define EEDI 0x04
1201 #define EECS 0x02
1202 #define EESK 0x01
1203 #define EERL 0x80
1204
1205 #define EEPROM_WRITE_OPCODE 0x05
1206 #define EEPROM_READ_OPCODE 0x06
1207 #define EEPROM_EWDS_OPCODE 0x10
1208 #define EEPROM_EWEN_OPCODE 0x13
1209
1210 #define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
1211 #define NUM_EEPROM_TX_G_PARMS 7
1212 #define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID
1213 #define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID
1214 #define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID
1215 #define EEPROM_G_TX_PWR_OFFSET 0x52
1216 #define EEPROM_G_TX2_PWR_OFFSET 0x60
1217 #define EEPROM_LED1_OFFSET 0x3c
1218 #define EEPROM_LED2_OFFSET 0x3e
1219 #define EEPROM_LED3_OFFSET 0x40
1220 #define EEPROM_LNA_OFFSET 0x44
1221 #define EEPROM_RSSI_BG_OFFSET 0x46
1222 #define EEPROM_RSSI_A_OFFSET 0x4a
1223 #define EEPROM_DEFINE_MAX_TXPWR 0x4e
1224 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde // 20MHZ 2.4G tx power.
1225 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee // 40MHZ 2.4G tx power.
1226 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa // 20MHZ 5G tx power.
1227 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a // 40MHZ 5G tx power.
1228 #define EEPROM_A_TX_PWR_OFFSET 0x78
1229 #define EEPROM_A_TX2_PWR_OFFSET 0xa6
1230 #define EEPROM_VERSION_OFFSET 0x02
1231 #define EEPROM_FREQ_OFFSET 0x3a
1232 #define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power.
1233 #define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
1234 #define VALID_EEPROM_VERSION 1
1235
1236 // PairKeyMode definition
1237 #define PKMODE_NONE 0
1238 #define PKMODE_WEP64 1
1239 #define PKMODE_WEP128 2
1240 #define PKMODE_TKIP 3
1241 #define PKMODE_AES 4
1242 #define PKMODE_CKIP64 5
1243 #define PKMODE_CKIP128 6
1244 #define PKMODE_TKIP_NO_MIC 7 // MIC appended by driver: not a valid value in hardware key table
1245
1246 // =================================================================================
1247 // WCID format
1248 // =================================================================================
1249 //7.1 WCID ENTRY format : 8bytes
1250 typedef struct _WCID_ENTRY_STRUC {
1251 UCHAR RXBABitmap7; // bit0 for TID8, bit7 for TID 15
1252 UCHAR RXBABitmap0; // bit0 for TID0, bit7 for TID 7
1253 UCHAR MAC[6]; // 0 for shared key table. 1 for pairwise key table
1254 } WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1255
1256 //8.1.1 SECURITY KEY format : 8DW
1257 // 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
1258 typedef struct _HW_KEY_ENTRY { // 32-byte per entry
1259 UCHAR Key[16];
1260 UCHAR TxMic[8];
1261 UCHAR RxMic[8];
1262 } HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1263
1264 //8.1.2 IV/EIV format : 2DW
1265
1266 //8.1.3 RX attribute entry format : 1DW
1267 typedef struct _MAC_ATTRIBUTE_STRUC {
1268 UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table
1269 UINT32 PairKeyMode:3;
1270 UINT32 BSSIDIdx:3; //multipleBSS index for the WCID
1271 UINT32 RXWIUDF:3;
1272 UINT32 rsv:22;
1273 } MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1274
1275 // =================================================================================
1276 // TX / RX ring descriptor format
1277 // =================================================================================
1278
1279 // the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
1280 // MAC block use this TXINFO to control the transmission behavior of this frame.
1281 #define FIFO_MGMT 0
1282 #define FIFO_HCCA 1
1283 #define FIFO_EDCA 2
1284
1285 //
1286 // TX descriptor format, Tx ring, Mgmt Ring
1287 //
1288 typedef struct PACKED _TXD_STRUC {
1289 // Word 0
1290 UINT32 SDPtr0;
1291 // Word 1
1292 UINT32 SDLen1:14;
1293 UINT32 LastSec1:1;
1294 UINT32 Burst:1;
1295 UINT32 SDLen0:14;
1296 UINT32 LastSec0:1;
1297 UINT32 DMADONE:1;
1298 //Word2
1299 UINT32 SDPtr1;
1300 //Word3
1301 UINT32 rsv2:24;
1302 UINT32 WIV:1; // Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition
1303 UINT32 QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
1304 UINT32 rsv:2;
1305 UINT32 TCO:1; //
1306 UINT32 UCO:1; //
1307 UINT32 ICO:1; //
1308 } TXD_STRUC, *PTXD_STRUC;
1309
1310 //
1311 // TXD Wireless Information format for Tx ring and Mgmt Ring
1312 //
1313 //txop : for txop mode
1314 // 0:txop for the MPDU frame will be handles by ASIC by register
1315 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
1316 typedef struct PACKED _TXWI_STRUC {
1317 // Word 0
1318 UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment.
1319 UINT32 MIMOps:1; // the remote peer is in dynamic MIMO-PS mode
1320 UINT32 CFACK:1;
1321 UINT32 TS:1;
1322
1323 UINT32 AMPDU:1;
1324 UINT32 MpduDensity:3;
1325 UINT32 txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
1326 UINT32 rsv:6;
1327
1328 UINT32 MCS:7;
1329 UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz
1330 UINT32 ShortGI:1;
1331 UINT32 STBC:2; // 1: STBC support MCS =0-7, 2,3 : RESERVE
1332 UINT32 Ifs:1; //
1333 UINT32 rsv2:1;
1334 UINT32 TxBF:1; // 3*3
1335 UINT32 PHYMODE:2;
1336 // Word 1
1337 UINT32 ACK:1;
1338 UINT32 NSEQ:1;
1339 UINT32 BAWinSize:6;
1340 UINT32 WirelessCliID:8;
1341 UINT32 MPDUtotalByteCount:12;
1342 UINT32 PacketId:4;
1343 //Word2
1344 UINT32 IV;
1345 //Word3
1346 UINT32 EIV;
1347 } TXWI_STRUC, *PTXWI_STRUC;
1348
1349 //
1350 // Rx descriptor format, Rx Ring
1351 //
1352 #ifdef RT2860
1353 typedef struct PACKED _RXD_STRUC {
1354 // Word 0
1355 UINT32 SDP0;
1356 // Word 1
1357 UINT32 SDL1:14;
1358 UINT32 Rsv:2;
1359 UINT32 SDL0:14;
1360 UINT32 LS0:1;
1361 UINT32 DDONE:1;
1362 // Word 2
1363 UINT32 SDP1;
1364 // Word 3
1365 UINT32 BA:1;
1366 UINT32 DATA:1;
1367 UINT32 NULLDATA:1;
1368 UINT32 FRAG:1;
1369 UINT32 U2M:1; // 1: this RX frame is unicast to me
1370 UINT32 Mcast:1; // 1: this is a multicast frame
1371 UINT32 Bcast:1; // 1: this is a broadcast frame
1372 UINT32 MyBss:1; // 1: this frame belongs to the same BSSID
1373 UINT32 Crc:1; // 1: CRC error
1374 UINT32 CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
1375 UINT32 AMSDU:1; // rx with 802.3 header, not 802.11 header.
1376 UINT32 HTC:1;
1377 UINT32 RSSI:1;
1378 UINT32 L2PAD:1;
1379 UINT32 AMPDU:1;
1380 UINT32 Decrypted:1; // this frame is being decrypted.
1381 UINT32 PlcpSignal:1; // To be moved
1382 UINT32 PlcpRssil:1;// To be moved
1383 UINT32 Rsv1:13;
1384 } RXD_STRUC, *PRXD_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
1385 #endif /* RT2860 */
1386
1387 //
1388 // RXWI wireless information format, in PBF. invisible in driver.
1389 //
1390 typedef struct PACKED _RXWI_STRUC {
1391 // Word 0
1392 UINT32 WirelessCliID:8;
1393 UINT32 KeyIndex:2;
1394 UINT32 BSSID:3;
1395 UINT32 UDF:3;
1396 UINT32 MPDUtotalByteCount:12;
1397 UINT32 TID:4;
1398 // Word 1
1399 UINT32 FRAG:4;
1400 UINT32 SEQUENCE:12;
1401 UINT32 MCS:7;
1402 UINT32 BW:1;
1403 UINT32 ShortGI:1;
1404 UINT32 STBC:2;
1405 UINT32 rsv:3;
1406 UINT32 PHYMODE:2; // 1: this RX frame is unicast to me
1407 //Word2
1408 UINT32 RSSI0:8;
1409 UINT32 RSSI1:8;
1410 UINT32 RSSI2:8;
1411 UINT32 rsv1:8;
1412 //Word3
1413 UINT32 SNR0:8;
1414 UINT32 SNR1:8;
1415 UINT32 rsv2:16;
1416 } RXWI_STRUC, *PRXWI_STRUC;
1417
1418 // =================================================================================
1419 // HOST-MCU communication data structure
1420 // =================================================================================
1421
1422 //
1423 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
1424 //
1425 typedef union _H2M_MAILBOX_STRUC {
1426 struct {
1427 UINT32 LowByte:8;
1428 UINT32 HighByte:8;
1429 UINT32 CmdToken:8;
1430 UINT32 Owner:8;
1431 } field;
1432 UINT32 word;
1433 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
1434
1435 //
1436 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
1437 //
1438 typedef union _M2H_CMD_DONE_STRUC {
1439 struct {
1440 UINT32 CmdToken0;
1441 UINT32 CmdToken1;
1442 UINT32 CmdToken2;
1443 UINT32 CmdToken3;
1444 } field;
1445 UINT32 word;
1446 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
1447
1448 //
1449 // MCU_LEDCS: MCU LED Control Setting.
1450 //
1451 typedef union _MCU_LEDCS_STRUC {
1452 struct {
1453 UCHAR LedMode:7;
1454 UCHAR Polarity:1;
1455 } field;
1456 UCHAR word;
1457 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
1458
1459 // =================================================================================
1460 // Register format
1461 // =================================================================================
1462
1463
1464
1465 //NAV_TIME_CFG :NAV
1466 typedef union _NAV_TIME_CFG_STRUC {
1467 struct {
1468 UCHAR Sifs; // in unit of 1-us
1469 UCHAR SlotTime; // in unit of 1-us
1470 USHORT Eifs:9; // in unit of 1-us
1471 USHORT ZeroSifs:1; // Applied zero SIFS timer after OFDM RX 0: disable
1472 USHORT rsv:6;
1473 } field;
1474 UINT32 word;
1475 } NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
1476
1477 //
1478 // RX_FILTR_CFG: /RX configuration register
1479 //
1480 typedef union _RX_FILTR_CFG_STRUC {
1481 struct {
1482 UINT32 DropCRCErr:1; // Drop CRC error
1483 UINT32 DropPhyErr:1; // Drop physical error
1484 UINT32 DropNotToMe:1; // Drop not to me unicast frame
1485 UINT32 DropNotMyBSSID:1; // Drop fram ToDs bit is true
1486
1487 UINT32 DropVerErr:1; // Drop version error frame
1488 UINT32 DropMcast:1; // Drop multicast frames
1489 UINT32 DropBcast:1; // Drop broadcast frames
1490 UINT32 DropDuplicate:1; // Drop duplicate frame
1491
1492 UINT32 DropCFEndAck:1; // Drop Ps-Poll
1493 UINT32 DropCFEnd:1; // Drop Ps-Poll
1494 UINT32 DropAck:1; // Drop Ps-Poll
1495 UINT32 DropCts:1; // Drop Ps-Poll
1496
1497 UINT32 DropRts:1; // Drop Ps-Poll
1498 UINT32 DropPsPoll:1; // Drop Ps-Poll
1499 UINT32 DropBA:1; //
1500 UINT32 DropBAR:1; //
1501
1502 UINT32 DropRsvCntlType:1;
1503 UINT32 :15;
1504 } field;
1505 UINT32 word;
1506 } RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
1507
1508 //
1509 // PHY_CSR4: RF serial control register
1510 //
1511 typedef union _PHY_CSR4_STRUC {
1512 struct {
1513 UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1514 UINT32 NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1515 UINT32 IFSelect:1; // 1: select IF to program, 0: select RF to program
1516 UINT32 PLL_LD:1; // RF PLL_LD status
1517 UINT32 Busy:1; // 1: ASIC is busy execute RF programming.
1518 } field;
1519 UINT32 word;
1520 } PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
1521
1522 //
1523 // SEC_CSR5: shared key table security mode register
1524 //
1525 typedef union _SEC_CSR5_STRUC {
1526 struct {
1527 UINT32 Bss2Key0CipherAlg:3;
1528 UINT32 :1;
1529 UINT32 Bss2Key1CipherAlg:3;
1530 UINT32 :1;
1531 UINT32 Bss2Key2CipherAlg:3;
1532 UINT32 :1;
1533 UINT32 Bss2Key3CipherAlg:3;
1534 UINT32 :1;
1535 UINT32 Bss3Key0CipherAlg:3;
1536 UINT32 :1;
1537 UINT32 Bss3Key1CipherAlg:3;
1538 UINT32 :1;
1539 UINT32 Bss3Key2CipherAlg:3;
1540 UINT32 :1;
1541 UINT32 Bss3Key3CipherAlg:3;
1542 UINT32 :1;
1543 } field;
1544 UINT32 word;
1545 } SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
1546
1547 //
1548 // HOST_CMD_CSR: For HOST to interrupt embedded processor
1549 //
1550 typedef union _HOST_CMD_CSR_STRUC {
1551 struct {
1552 UINT32 HostCommand:8;
1553 UINT32 Rsv:24;
1554 } field;
1555 UINT32 word;
1556 } HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
1557
1558 //
1559 // AIFSN_CSR: AIFSN for each EDCA AC
1560 //
1561
1562
1563
1564 //
1565 // E2PROM_CSR: EEPROM control register
1566 //
1567 typedef union _E2PROM_CSR_STRUC {
1568 struct {
1569 UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
1570 UINT32 EepromSK:1;
1571 UINT32 EepromCS:1;
1572 UINT32 EepromDI:1;
1573 UINT32 EepromDO:1;
1574 UINT32 Type:1; // 1: 93C46, 0:93C66
1575 UINT32 LoadStatus:1; // 1:loading, 0:done
1576 UINT32 Rsvd:25;
1577 } field;
1578 UINT32 word;
1579 } E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
1580
1581 // -------------------------------------------------------------------
1582 // E2PROM data layout
1583 // -------------------------------------------------------------------
1584
1585 //
1586 // EEPROM antenna select format
1587 //
1588 typedef union _EEPROM_ANTENNA_STRUC {
1589 struct {
1590 USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
1591 USHORT TxPath:4; // 1: 1T, 2: 2T
1592 USHORT RfIcType:4; // see E2PROM document
1593 USHORT Rsv:4;
1594 } field;
1595 USHORT word;
1596 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
1597
1598 typedef union _EEPROM_NIC_CINFIG2_STRUC {
1599 struct {
1600 USHORT HardwareRadioControl:1; // 1:enable, 0:disable
1601 USHORT DynamicTxAgcControl:1; //
1602 USHORT ExternalLNAForG:1; //
1603 USHORT ExternalLNAForA:1; // external LNA enable for 2.4G
1604 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1605 USHORT BW40MSidebandForG:1;
1606 USHORT BW40MSidebandForA:1;
1607 USHORT EnableWPSPBC:1; // WPS PBC Control bit
1608 USHORT BW40MAvailForG:1; // 0:enable, 1:disable
1609 USHORT BW40MAvailForA:1; // 0:enable, 1:disable
1610 #ifndef RT30xx
1611 USHORT Rsv2:6; // must be 0
1612 #endif
1613 #ifdef RT30xx
1614 USHORT Rsv1:1; // must be 0
1615 USHORT AntDiversity:1; // Antenna diversity
1616 USHORT Rsv2:3; // must be 0
1617 USHORT DACTestBit:1; // control if driver should patch the DAC issue
1618 #endif
1619 } field;
1620 USHORT word;
1621 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
1622
1623 //
1624 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
1625 //
1626 typedef union _EEPROM_TX_PWR_STRUC {
1627 struct {
1628 CHAR Byte0; // Low Byte
1629 CHAR Byte1; // High Byte
1630 } field;
1631 USHORT word;
1632 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
1633
1634 typedef union _EEPROM_VERSION_STRUC {
1635 struct {
1636 UCHAR FaeReleaseNumber; // Low Byte
1637 UCHAR Version; // High Byte
1638 } field;
1639 USHORT word;
1640 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
1641
1642 typedef union _EEPROM_LED_STRUC {
1643 struct {
1644 USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
1645 USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
1646 USHORT PolarityACT:1; // Polarity ACT setting.
1647 USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
1648 USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
1649 USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
1650 USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
1651 USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
1652 USHORT LedMode:5; // Led mode.
1653 USHORT Rsvd:3; // Reserved
1654 } field;
1655 USHORT word;
1656 } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
1657
1658 typedef union _EEPROM_TXPOWER_DELTA_STRUC {
1659 struct {
1660 UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
1661 UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
1662 UCHAR TxPowerEnable:1;// Enable
1663 } field;
1664 UCHAR value;
1665 } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
1666
1667 //
1668 // QOS_CSR0: TXOP holder address0 register
1669 //
1670 typedef union _QOS_CSR0_STRUC {
1671 struct {
1672 UCHAR Byte0; // MAC address byte 0
1673 UCHAR Byte1; // MAC address byte 1
1674 UCHAR Byte2; // MAC address byte 2
1675 UCHAR Byte3; // MAC address byte 3
1676 } field;
1677 UINT32 word;
1678 } QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
1679
1680 //
1681 // QOS_CSR1: TXOP holder address1 register
1682 //
1683 typedef union _QOS_CSR1_STRUC {
1684 struct {
1685 UCHAR Byte4; // MAC address byte 4
1686 UCHAR Byte5; // MAC address byte 5
1687 UCHAR Rsvd0;
1688 UCHAR Rsvd1;
1689 } field;
1690 UINT32 word;
1691 } QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
1692
1693 #define RF_CSR_CFG 0x500
1694 typedef union _RF_CSR_CFG_STRUC {
1695 struct {
1696 UINT RF_CSR_DATA:8; // DATA
1697 UINT TESTCSR_RFACC_REGNUM:5; // RF register ID
1698 UINT Rsvd2:3; // Reserved
1699 UINT RF_CSR_WR:1; // 0: read 1: write
1700 UINT RF_CSR_KICK:1; // kick RF register read/write
1701 UINT Rsvd1:14; // Reserved
1702 } field;
1703 UINT word;
1704 } RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
1705
1706 #endif // __RT28XX_H__
Linux with added FPC-III support