drivers/staging/stlc45xx/stlc45xx.h

   1 /*
   2  * This file is part of stlc45xx
   3  *
   4  * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
   5  *
   6  * Contact: Kalle Valo <kalle.valo@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/mutex.h>
  25 #include <linux/list.h>
  26 #include <net/mac80211.h>
  27
  28 #include "stlc45xx_lmac.h"
  29
  30 #define DRIVER_NAME "stlc45xx"
  31 #define DRIVER_VERSION "0.1.3"
  32
  33 #define DRIVER_PREFIX DRIVER_NAME ": "
  34
  35 enum {
  36         DEBUG_NONE = 0,
  37         DEBUG_FUNC = 1 << 0,
  38         DEBUG_IRQ = 1 << 1,
  39         DEBUG_BH = 1 << 2,
  40         DEBUG_RX = 1 << 3,
  41         DEBUG_RX_CONTENT = 1 << 5,
  42         DEBUG_TX = 1 << 6,
  43         DEBUG_TX_CONTENT = 1 << 8,
  44         DEBUG_TXBUFFER = 1 << 9,
  45         DEBUG_QUEUE = 1 << 10,
  46         DEBUG_BOOT = 1 << 11,
  47         DEBUG_PSM = 1 << 12,
  48         DEBUG_ALL = ~0,
  49 };
  50
  51 #define DEBUG_LEVEL DEBUG_NONE
  52 /* #define DEBUG_LEVEL DEBUG_ALL */
  53 /* #define DEBUG_LEVEL (DEBUG_TX | DEBUG_RX | DEBUG_IRQ) */
  54 /* #define DEBUG_LEVEL (DEBUG_TX | DEBUG_MEMREGION | DEBUG_QUEUE) */
  55 /* #define DEBUG_LEVEL (DEBUG_MEMREGION | DEBUG_QUEUE) */
  56
  57 #define stlc45xx_error(fmt, arg...) \
  58         printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
  59
  60 #define stlc45xx_warning(fmt, arg...) \
  61         printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
  62
  63 #define stlc45xx_info(fmt, arg...) \
  64         printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
  65
  66 #define stlc45xx_debug(level, fmt, arg...) \
  67         do { \
  68                 if (level & DEBUG_LEVEL) \
  69                         printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
  70         } while (0)
  71
  72 #define stlc45xx_dump(level, buf, len)          \
  73         do { \
  74                 if (level & DEBUG_LEVEL) \
  75                         print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, \
  76                                        16, 1, buf, len, 1);             \
  77         } while (0)
  78
  79 #define MAC2STR(a) ((a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5])
  80 #define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
  81
  82 /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */
  83 #define ADDR_READ_BIT_15  0x8000
  84
  85 #define SPI_ADRS_ARM_INTERRUPTS     0x00
  86 #define SPI_ADRS_ARM_INT_EN         0x04
  87
  88 #define SPI_ADRS_HOST_INTERRUPTS    0x08
  89 #define SPI_ADRS_HOST_INT_EN        0x0c
  90 #define SPI_ADRS_HOST_INT_ACK       0x10
  91
  92 #define SPI_ADRS_GEN_PURP_1         0x14
  93 #define SPI_ADRS_GEN_PURP_2         0x18
  94
  95 /* high word */
  96 #define SPI_ADRS_DEV_CTRL_STAT      0x26
  97
  98 #define SPI_ADRS_DMA_DATA           0x28
  99
 100 #define SPI_ADRS_DMA_WRITE_CTRL     0x2c
 101 #define SPI_ADRS_DMA_WRITE_LEN      0x2e
 102 #define SPI_ADRS_DMA_WRITE_BASE     0x30
 103
 104 #define SPI_ADRS_DMA_READ_CTRL      0x34
 105 #define SPI_ADRS_DMA_READ_LEN       0x36
 106 #define SPI_ADRS_DMA_READ_BASE      0x38
 107
 108 #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000
 109 #define SPI_CTRL_STAT_START_HALTED  0x4000
 110 #define SPI_CTRL_STAT_RAM_BOOT      0x2000
 111 #define SPI_CTRL_STAT_HOST_RESET    0x1000
 112 #define SPI_CTRL_STAT_HOST_CPU_EN   0x0800
 113
 114 #define SPI_DMA_WRITE_CTRL_ENABLE   0x0001
 115 #define SPI_DMA_READ_CTRL_ENABLE    0x0001
 116 #define HOST_ALLOWED                (1 << 7)
 117
 118 #define FIRMWARE_ADDRESS                        0x20000
 119
 120 #define SPI_TIMEOUT                             100         /* msec */
 121
 122 #define SPI_MAX_TX_PACKETS                      32
 123
 124 #define SPI_MAX_PACKET_SIZE                     32767
 125
 126 #define SPI_TARGET_INT_WAKEUP                   0x00000001
 127 #define SPI_TARGET_INT_SLEEP                    0x00000002
 128 #define SPI_TARGET_INT_RDDONE                   0x00000004
 129
 130 #define SPI_TARGET_INT_CTS                      0x00004000
 131 #define SPI_TARGET_INT_DR                       0x00008000
 132
 133 #define SPI_HOST_INT_READY                      0x00000001
 134 #define SPI_HOST_INT_WR_READY                   0x00000002
 135 #define SPI_HOST_INT_SW_UPDATE                  0x00000004
 136 #define SPI_HOST_INT_UPDATE                     0x10000000
 137
 138 /* clear to send */
 139 #define SPI_HOST_INT_CTS                        0x00004000
 140
 141 /* data ready */
 142 #define SPI_HOST_INT_DR                         0x00008000
 143
 144 #define SPI_HOST_INTS_DEFAULT \
 145         (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)
 146
 147 #define TARGET_BOOT_SLEEP 50
 148
 149 /* The firmware buffer is divided into three areas:
 150  *
 151  * o config area (for control commands)
 152  * o tx buffer
 153  * o rx buffer
 154  */
 155 #define FIRMWARE_BUFFER_START 0x20200
 156 #define FIRMWARE_BUFFER_END 0x27c60
 157 #define FIRMWARE_BUFFER_LEN (FIRMWARE_BUFFER_END - FIRMWARE_BUFFER_START)
 158 #define FIRMWARE_MTU 3240
 159 #define FIRMWARE_CONFIG_PAYLOAD_LEN 1024
 160 #define FIRMWARE_CONFIG_START FIRMWARE_BUFFER_START
 161 #define FIRMWARE_CONFIG_LEN (sizeof(struct s_lm_control) + \
 162                              FIRMWARE_CONFIG_PAYLOAD_LEN)
 163 #define FIRMWARE_CONFIG_END (FIRMWARE_CONFIG_START + FIRMWARE_CONFIG_LEN - 1)
 164 #define FIRMWARE_RXBUFFER_LEN (5 * FIRMWARE_MTU + 1024)
 165 #define FIRMWARE_RXBUFFER_START (FIRMWARE_BUFFER_END - FIRMWARE_RXBUFFER_LEN)
 166 #define FIRMWARE_RXBUFFER_END (FIRMWARE_RXBUFFER_START + \
 167                                FIRMWARE_RXBUFFER_LEN - 1)
 168 #define FIRMWARE_TXBUFFER_START (FIRMWARE_BUFFER_START + FIRMWARE_CONFIG_LEN)
 169 #define FIRMWARE_TXBUFFER_LEN (FIRMWARE_BUFFER_LEN - FIRMWARE_CONFIG_LEN - \
 170                                FIRMWARE_RXBUFFER_LEN)
 171 #define FIRMWARE_TXBUFFER_END (FIRMWARE_TXBUFFER_START + \
 172                                FIRMWARE_TXBUFFER_LEN - 1)
 173
 174 #define FIRMWARE_TXBUFFER_HEADER 100
 175 #define FIRMWARE_TXBUFFER_TRAILER 4
 176
 177 /* FIXME: come up with a proper value */
 178 #define MAX_FRAME_LEN 2500
 179
 180 /* unit is ms */
 181 #define TX_FRAME_LIFETIME 2000
 182 #define TX_TIMEOUT 4000
 183
 184 #define SUPPORTED_CHANNELS 13
 185
 186 /* FIXME */
 187 /* #define CHANNEL_CAL_LEN offsetof(struct s_lmo_scan, bratemask) - \ */
 188 /*      offsetof(struct s_lmo_scan, channel) */
 189 #define CHANNEL_CAL_LEN 292
 190 #define CHANNEL_CAL_ARRAY_LEN (SUPPORTED_CHANNELS * CHANNEL_CAL_LEN)
 191 /* FIXME */
 192 /* #define RSSI_CAL_LEN sizeof(struct s_lmo_scan) - \ */
 193 /*      offsetof(struct s_lmo_scan, rssical) */
 194 #define RSSI_CAL_LEN 8
 195 #define RSSI_CAL_ARRAY_LEN (SUPPORTED_CHANNELS * RSSI_CAL_LEN)
 196
 197 struct s_dma_regs {
 198         unsigned short cmd;
 199         unsigned short len;
 200         unsigned long addr;
 201 };
 202
 203 struct stlc45xx_ie_tim {
 204         u8 dtim_count;
 205         u8 dtim_period;
 206         u8 bmap_control;
 207         u8 pvbmap[251];
 208 };
 209
 210 struct txbuffer {
 211         /* can be removed when switched to skb queue */
 212         struct list_head tx_list;
 213
 214         struct list_head buffer_list;
 215
 216         int start;
 217         int frame_start;
 218         int end;
 219
 220         struct sk_buff *skb;
 221         u32 handle;
 222
 223         bool status_needed;
 224
 225         int header_len;
 226
 227         /* unit jiffies */
 228         unsigned long lifetime;
 229 };
 230
 231 enum fw_state {
 232         FW_STATE_OFF,
 233         FW_STATE_BOOTING,
 234         FW_STATE_READY,
 235         FW_STATE_RESET,
 236         FW_STATE_RESETTING,
 237 };
 238
 239 struct stlc45xx {
 240         struct ieee80211_hw *hw;
 241         struct spi_device *spi;
 242         struct work_struct work;
 243         struct work_struct work_reset;
 244         struct delayed_work work_tx_timeout;
 245         struct mutex mutex;
 246         struct completion fw_comp;
 247
 248
 249         u8 bssid[ETH_ALEN];
 250         u8 mac_addr[ETH_ALEN];
 251         int channel;
 252
 253         u8 *cal_rssi;
 254         u8 *cal_channels;
 255
 256         enum fw_state fw_state;
 257
 258         spinlock_t tx_lock;
 259
 260         /* protected by tx_lock */
 261         struct list_head txbuffer;
 262
 263         /* protected by tx_lock */
 264         struct list_head tx_pending;
 265
 266         /* protected by tx_lock */
 267         int tx_queue_stopped;
 268
 269         /* protected by mutex */
 270         struct list_head tx_sent;
 271
 272         int tx_frames;
 273
 274         u8 *fw;
 275         int fw_len;
 276
 277         bool psm;
 278         bool associated;
 279         int aid;
 280         bool pspolling;
 281 };
 282
 283