?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
m68k/defconfig: Enable automounting of devtmpfs at /dev
[linux/fpc-iii.git] / drivers / infiniband / hw / qib / qib_iba7220.c
blob7dec89fdc1248dc69c3cab38069e5e2f32986ce3
1 /*
2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
3 * All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34 /*
35 * This file contains all of the code that is specific to the
36 * QLogic_IB 7220 chip (except that specific to the SerDes)
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/module.h>
43 #include <linux/io.h>
44 #include <rdma/ib_verbs.h>
45
46 #include "qib.h"
47 #include "qib_7220.h"
48
49 static void qib_setup_7220_setextled(struct qib_pportdata *, u32);
50 static void qib_7220_handle_hwerrors(struct qib_devdata *, char *, size_t);
51 static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op);
52 static u32 qib_7220_iblink_state(u64);
53 static u8 qib_7220_phys_portstate(u64);
54 static void qib_sdma_update_7220_tail(struct qib_pportdata *, u16);
55 static void qib_set_ib_7220_lstate(struct qib_pportdata *, u16, u16);
56
57 /*
58 * This file contains almost all the chip-specific register information and
59 * access functions for the QLogic QLogic_IB 7220 PCI-Express chip, with the
60 * exception of SerDes support, which in in qib_sd7220.c.
61 */
62
63 /* Below uses machine-generated qib_chipnum_regs.h file */
64 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
65
66 /* Use defines to tie machine-generated names to lower-case names */
67 #define kr_control KREG_IDX(Control)
68 #define kr_counterregbase KREG_IDX(CntrRegBase)
69 #define kr_errclear KREG_IDX(ErrClear)
70 #define kr_errmask KREG_IDX(ErrMask)
71 #define kr_errstatus KREG_IDX(ErrStatus)
72 #define kr_extctrl KREG_IDX(EXTCtrl)
73 #define kr_extstatus KREG_IDX(EXTStatus)
74 #define kr_gpio_clear KREG_IDX(GPIOClear)
75 #define kr_gpio_mask KREG_IDX(GPIOMask)
76 #define kr_gpio_out KREG_IDX(GPIOOut)
77 #define kr_gpio_status KREG_IDX(GPIOStatus)
78 #define kr_hrtbt_guid KREG_IDX(HRTBT_GUID)
79 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
80 #define kr_hwerrclear KREG_IDX(HwErrClear)
81 #define kr_hwerrmask KREG_IDX(HwErrMask)
82 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
83 #define kr_ibcctrl KREG_IDX(IBCCtrl)
84 #define kr_ibcddrctrl KREG_IDX(IBCDDRCtrl)
85 #define kr_ibcddrstatus KREG_IDX(IBCDDRStatus)
86 #define kr_ibcstatus KREG_IDX(IBCStatus)
87 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
88 #define kr_intclear KREG_IDX(IntClear)
89 #define kr_intmask KREG_IDX(IntMask)
90 #define kr_intstatus KREG_IDX(IntStatus)
91 #define kr_ncmodectrl KREG_IDX(IBNCModeCtrl)
92 #define kr_palign KREG_IDX(PageAlign)
93 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
94 #define kr_portcnt KREG_IDX(PortCnt)
95 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
96 #define kr_rcvctrl KREG_IDX(RcvCtrl)
97 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
98 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
99 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
100 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
101 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
102 #define kr_rcvpktledcnt KREG_IDX(RcvPktLEDCnt)
103 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
104 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
105 #define kr_revision KREG_IDX(Revision)
106 #define kr_scratch KREG_IDX(Scratch)
107 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
108 #define kr_sendctrl KREG_IDX(SendCtrl)
109 #define kr_senddmabase KREG_IDX(SendDmaBase)
110 #define kr_senddmabufmask0 KREG_IDX(SendDmaBufMask0)
111 #define kr_senddmabufmask1 (KREG_IDX(SendDmaBufMask0) + 1)
112 #define kr_senddmabufmask2 (KREG_IDX(SendDmaBufMask0) + 2)
113 #define kr_senddmahead KREG_IDX(SendDmaHead)
114 #define kr_senddmaheadaddr KREG_IDX(SendDmaHeadAddr)
115 #define kr_senddmalengen KREG_IDX(SendDmaLenGen)
116 #define kr_senddmastatus KREG_IDX(SendDmaStatus)
117 #define kr_senddmatail KREG_IDX(SendDmaTail)
118 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
119 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
120 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
121 #define kr_sendpiosize KREG_IDX(SendBufSize)
122 #define kr_sendregbase KREG_IDX(SendRegBase)
123 #define kr_userregbase KREG_IDX(UserRegBase)
124 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
125
126 /* These must only be written via qib_write_kreg_ctxt() */
127 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
128 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
129
130
131 #define CREG_IDX(regname) ((QIB_7220_##regname##_OFFS - \
132 QIB_7220_LBIntCnt_OFFS) / sizeof(u64))
133
134 #define cr_badformat CREG_IDX(RxVersionErrCnt)
135 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
136 #define cr_errlink CREG_IDX(RxLinkMalformCnt)
137 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
138 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
139 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlViolCnt)
140 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
141 #define cr_errslen CREG_IDX(TxLenErrCnt)
142 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
143 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
144 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
145 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
146 #define cr_lbint CREG_IDX(LBIntCnt)
147 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
148 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
149 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
150 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
151 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
152 #define cr_pktsend CREG_IDX(TxDataPktCnt)
153 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
154 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
155 #define cr_rcvebp CREG_IDX(RxEBPCnt)
156 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
157 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
158 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
159 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
160 #define cr_wordrcv CREG_IDX(RxDwordCnt)
161 #define cr_wordsend CREG_IDX(TxDwordCnt)
162 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
163 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
164 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
165 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
166 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
167 #define cr_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
168 #define cr_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
169 #define cr_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
170 #define cr_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
171 #define cr_rxvlerr CREG_IDX(RxVlErrCnt)
172 #define cr_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
173 #define cr_psstat CREG_IDX(PSStat)
174 #define cr_psstart CREG_IDX(PSStart)
175 #define cr_psinterval CREG_IDX(PSInterval)
176 #define cr_psrcvdatacount CREG_IDX(PSRcvDataCount)
177 #define cr_psrcvpktscount CREG_IDX(PSRcvPktsCount)
178 #define cr_psxmitdatacount CREG_IDX(PSXmitDataCount)
179 #define cr_psxmitpktscount CREG_IDX(PSXmitPktsCount)
180 #define cr_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
181 #define cr_txsdmadesc CREG_IDX(TxSDmaDescCnt)
182 #define cr_pcieretrydiag CREG_IDX(PcieRetryBufDiagQwordCnt)
183
184 #define SYM_RMASK(regname, fldname) ((u64) \
185 QIB_7220_##regname##_##fldname##_RMASK)
186 #define SYM_MASK(regname, fldname) ((u64) \
187 QIB_7220_##regname##_##fldname##_RMASK << \
188 QIB_7220_##regname##_##fldname##_LSB)
189 #define SYM_LSB(regname, fldname) (QIB_7220_##regname##_##fldname##_LSB)
190 #define SYM_FIELD(value, regname, fldname) ((u64) \
191 (((value) >> SYM_LSB(regname, fldname)) & \
192 SYM_RMASK(regname, fldname)))
193 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
194 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
195
196 /* ibcctrl bits */
197 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
198 /* cycle through TS1/TS2 till OK */
199 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
200 /* wait for TS1, then go on */
201 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
202 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
203
204 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
205 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
206 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
207
208 #define BLOB_7220_IBCHG 0x81
209
210 /*
211 * We could have a single register get/put routine, that takes a group type,
212 * but this is somewhat clearer and cleaner. It also gives us some error
213 * checking. 64 bit register reads should always work, but are inefficient
214 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
215 * so we use kreg32 wherever possible. User register and counter register
216 * reads are always 32 bit reads, so only one form of those routines.
217 */
218
219 /**
220 * qib_read_ureg32 - read 32-bit virtualized per-context register
221 * @dd: device
222 * @regno: register number
223 * @ctxt: context number
224 *
225 * Return the contents of a register that is virtualized to be per context.
226 * Returns -1 on errors (not distinguishable from valid contents at
227 * runtime; we may add a separate error variable at some point).
228 */
229 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
230 enum qib_ureg regno, int ctxt)
231 {
232 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
233 return 0;
234
235 if (dd->userbase)
236 return readl(regno + (u64 __iomem *)
237 ((char __iomem *)dd->userbase +
238 dd->ureg_align * ctxt));
239 else
240 return readl(regno + (u64 __iomem *)
241 (dd->uregbase +
242 (char __iomem *)dd->kregbase +
243 dd->ureg_align * ctxt));
244 }
245
246 /**
247 * qib_write_ureg - write 32-bit virtualized per-context register
248 * @dd: device
249 * @regno: register number
250 * @value: value
251 * @ctxt: context
252 *
253 * Write the contents of a register that is virtualized to be per context.
254 */
255 static inline void qib_write_ureg(const struct qib_devdata *dd,
256 enum qib_ureg regno, u64 value, int ctxt)
257 {
258 u64 __iomem *ubase;
259
260 if (dd->userbase)
261 ubase = (u64 __iomem *)
262 ((char __iomem *) dd->userbase +
263 dd->ureg_align * ctxt);
264 else
265 ubase = (u64 __iomem *)
266 (dd->uregbase +
267 (char __iomem *) dd->kregbase +
268 dd->ureg_align * ctxt);
269
270 if (dd->kregbase && (dd->flags & QIB_PRESENT))
271 writeq(value, &ubase[regno]);
272 }
273
274 /**
275 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
276 * @dd: the qlogic_ib device
277 * @regno: the register number to write
278 * @ctxt: the context containing the register
279 * @value: the value to write
280 */
281 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
282 const u16 regno, unsigned ctxt,
283 u64 value)
284 {
285 qib_write_kreg(dd, regno + ctxt, value);
286 }
287
288 static inline void write_7220_creg(const struct qib_devdata *dd,
289 u16 regno, u64 value)
290 {
291 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
292 writeq(value, &dd->cspec->cregbase[regno]);
293 }
294
295 static inline u64 read_7220_creg(const struct qib_devdata *dd, u16 regno)
296 {
297 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
298 return 0;
299 return readq(&dd->cspec->cregbase[regno]);
300 }
301
302 static inline u32 read_7220_creg32(const struct qib_devdata *dd, u16 regno)
303 {
304 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
305 return 0;
306 return readl(&dd->cspec->cregbase[regno]);
307 }
308
309 /* kr_revision bits */
310 #define QLOGIC_IB_R_EMULATORREV_MASK ((1ULL << 22) - 1)
311 #define QLOGIC_IB_R_EMULATORREV_SHIFT 40
312
313 /* kr_control bits */
314 #define QLOGIC_IB_C_RESET (1U << 7)
315
316 /* kr_intstatus, kr_intclear, kr_intmask bits */
317 #define QLOGIC_IB_I_RCVURG_MASK ((1ULL << 17) - 1)
318 #define QLOGIC_IB_I_RCVURG_SHIFT 32
319 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1ULL << 17) - 1)
320 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 0
321 #define QLOGIC_IB_I_SERDESTRIMDONE (1ULL << 27)
322
323 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
324 #define QLOGIC_IB_C_LINKENABLE 0x00000004
325
326 #define QLOGIC_IB_I_SDMAINT 0x8000000000000000ULL
327 #define QLOGIC_IB_I_SDMADISABLED 0x4000000000000000ULL
328 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
329 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
330 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
331 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
332
333 /* variables for sanity checking interrupt and errors */
334 #define QLOGIC_IB_I_BITSEXTANT \
335 (QLOGIC_IB_I_SDMAINT | QLOGIC_IB_I_SDMADISABLED | \
336 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
337 (QLOGIC_IB_I_RCVAVAIL_MASK << \
338 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
339 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
340 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO | \
341 QLOGIC_IB_I_SERDESTRIMDONE)
342
343 #define IB_HWE_BITSEXTANT \
344 (HWE_MASK(RXEMemParityErr) | \
345 HWE_MASK(TXEMemParityErr) | \
346 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
347 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
348 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
349 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
350 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
351 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
352 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
353 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
354 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
355 HWE_MASK(PowerOnBISTFailed) | \
356 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
357 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
358 QLOGIC_IB_HWE_SERDESPLLFAILED | \
359 HWE_MASK(IBCBusToSPCParityErr) | \
360 HWE_MASK(IBCBusFromSPCParityErr) | \
361 QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR | \
362 QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR | \
363 QLOGIC_IB_HWE_SDMAMEMREADERR | \
364 QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED | \
365 QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT | \
366 QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT | \
367 QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT | \
368 QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT | \
369 QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR | \
370 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR | \
371 QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR | \
372 QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR)
373
374 #define IB_E_BITSEXTANT \
375 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
376 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
377 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
378 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
379 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
380 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
381 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
382 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
383 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
384 ERR_MASK(SendSpecialTriggerErr) | \
385 ERR_MASK(SDmaDisabledErr) | ERR_MASK(SendMinPktLenErr) | \
386 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnderRunErr) | \
387 ERR_MASK(SendPktLenErr) | ERR_MASK(SendDroppedSmpPktErr) | \
388 ERR_MASK(SendDroppedDataPktErr) | \
389 ERR_MASK(SendPioArmLaunchErr) | \
390 ERR_MASK(SendUnexpectedPktNumErr) | \
391 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(SendBufMisuseErr) | \
392 ERR_MASK(SDmaGenMismatchErr) | ERR_MASK(SDmaOutOfBoundErr) | \
393 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
394 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
395 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
396 ERR_MASK(SDmaUnexpDataErr) | \
397 ERR_MASK(IBStatusChanged) | ERR_MASK(InvalidAddrErr) | \
398 ERR_MASK(ResetNegated) | ERR_MASK(HardwareErr) | \
399 ERR_MASK(SDmaDescAddrMisalignErr) | \
400 ERR_MASK(InvalidEEPCmd))
401
402 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
403 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x00000000000000ffULL
404 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
405 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
406 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
407 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
408 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
409 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
410 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
411 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
412 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
413 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
414 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
415 /* specific to this chip */
416 #define QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR 0x0000000000000040ULL
417 #define QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR 0x0000000000000080ULL
418 #define QLOGIC_IB_HWE_SDMAMEMREADERR 0x0000000010000000ULL
419 #define QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED 0x2000000000000000ULL
420 #define QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT 0x0100000000000000ULL
421 #define QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT 0x0200000000000000ULL
422 #define QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT 0x0400000000000000ULL
423 #define QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT 0x0800000000000000ULL
424 #define QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR 0x0000008000000000ULL
425 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
426 #define QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
427 #define QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
428
429 #define IBA7220_IBCC_LINKCMD_SHIFT 19
430
431 /* kr_ibcddrctrl bits */
432 #define IBA7220_IBC_DLIDLMC_MASK 0xFFFFFFFFUL
433 #define IBA7220_IBC_DLIDLMC_SHIFT 32
434
435 #define IBA7220_IBC_HRTBT_MASK (SYM_RMASK(IBCDDRCtrl, HRTBT_AUTO) | \
436 SYM_RMASK(IBCDDRCtrl, HRTBT_ENB))
437 #define IBA7220_IBC_HRTBT_SHIFT SYM_LSB(IBCDDRCtrl, HRTBT_ENB)
438
439 #define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
440 #define IBA7220_IBC_LREV_MASK 1
441 #define IBA7220_IBC_LREV_SHIFT 8
442 #define IBA7220_IBC_RXPOL_MASK 1
443 #define IBA7220_IBC_RXPOL_SHIFT 7
444 #define IBA7220_IBC_WIDTH_SHIFT 5
445 #define IBA7220_IBC_WIDTH_MASK 0x3
446 #define IBA7220_IBC_WIDTH_1X_ONLY (0 << IBA7220_IBC_WIDTH_SHIFT)
447 #define IBA7220_IBC_WIDTH_4X_ONLY (1 << IBA7220_IBC_WIDTH_SHIFT)
448 #define IBA7220_IBC_WIDTH_AUTONEG (2 << IBA7220_IBC_WIDTH_SHIFT)
449 #define IBA7220_IBC_SPEED_AUTONEG (1 << 1)
450 #define IBA7220_IBC_SPEED_SDR (1 << 2)
451 #define IBA7220_IBC_SPEED_DDR (1 << 3)
452 #define IBA7220_IBC_SPEED_AUTONEG_MASK (0x7 << 1)
453 #define IBA7220_IBC_IBTA_1_2_MASK (1)
454
455 /* kr_ibcddrstatus */
456 /* link latency shift is 0, don't bother defining */
457 #define IBA7220_DDRSTAT_LINKLAT_MASK 0x3ffffff
458
459 /* kr_extstatus bits */
460 #define QLOGIC_IB_EXTS_FREQSEL 0x2
461 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
462 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
463 #define QLOGIC_IB_EXTS_MEMBIST_DISABLED 0x0000000000008000
464
465 /* kr_xgxsconfig bits */
466 #define QLOGIC_IB_XGXS_RESET 0x5ULL
467 #define QLOGIC_IB_XGXS_FC_SAFE (1ULL << 63)
468
469 /* kr_rcvpktledcnt */
470 #define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
471 #define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
472
473 #define _QIB_GPIO_SDA_NUM 1
474 #define _QIB_GPIO_SCL_NUM 0
475 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7220 cards. */
476 #define QIB_TWSI_TEMP_DEV 0x98
477
478 /* HW counter clock is at 4nsec */
479 #define QIB_7220_PSXMITWAIT_CHECK_RATE 4000
480
481 #define IBA7220_R_INTRAVAIL_SHIFT 17
482 #define IBA7220_R_PKEY_DIS_SHIFT 34
483 #define IBA7220_R_TAILUPD_SHIFT 35
484 #define IBA7220_R_CTXTCFG_SHIFT 36
485
486 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
487
488 /*
489 * the size bits give us 2^N, in KB units. 0 marks as invalid,
490 * and 7 is reserved. We currently use only 2KB and 4KB
491 */
492 #define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
493 #define IBA7220_TID_SZ_2K (1UL << IBA7220_TID_SZ_SHIFT) /* 2KB */
494 #define IBA7220_TID_SZ_4K (2UL << IBA7220_TID_SZ_SHIFT) /* 4KB */
495 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
496 #define PBC_7220_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
497 #define PBC_7220_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
498
499 #define AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
500
501 /* packet rate matching delay multiplier */
502 static u8 rate_to_delay[2][2] = {
503 /* 1x, 4x */
504 { 8, 2 }, /* SDR */
505 { 4, 1 } /* DDR */
506 };
507
508 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
509 [IB_RATE_2_5_GBPS] = 8,
510 [IB_RATE_5_GBPS] = 4,
511 [IB_RATE_10_GBPS] = 2,
512 [IB_RATE_20_GBPS] = 1
513 };
514
515 #define IBA7220_LINKSPEED_SHIFT SYM_LSB(IBCStatus, LinkSpeedActive)
516 #define IBA7220_LINKWIDTH_SHIFT SYM_LSB(IBCStatus, LinkWidthActive)
517
518 /* link training states, from IBC */
519 #define IB_7220_LT_STATE_DISABLED 0x00
520 #define IB_7220_LT_STATE_LINKUP 0x01
521 #define IB_7220_LT_STATE_POLLACTIVE 0x02
522 #define IB_7220_LT_STATE_POLLQUIET 0x03
523 #define IB_7220_LT_STATE_SLEEPDELAY 0x04
524 #define IB_7220_LT_STATE_SLEEPQUIET 0x05
525 #define IB_7220_LT_STATE_CFGDEBOUNCE 0x08
526 #define IB_7220_LT_STATE_CFGRCVFCFG 0x09
527 #define IB_7220_LT_STATE_CFGWAITRMT 0x0a
528 #define IB_7220_LT_STATE_CFGIDLE 0x0b
529 #define IB_7220_LT_STATE_RECOVERRETRAIN 0x0c
530 #define IB_7220_LT_STATE_RECOVERWAITRMT 0x0e
531 #define IB_7220_LT_STATE_RECOVERIDLE 0x0f
532
533 /* link state machine states from IBC */
534 #define IB_7220_L_STATE_DOWN 0x0
535 #define IB_7220_L_STATE_INIT 0x1
536 #define IB_7220_L_STATE_ARM 0x2
537 #define IB_7220_L_STATE_ACTIVE 0x3
538 #define IB_7220_L_STATE_ACT_DEFER 0x4
539
540 static const u8 qib_7220_physportstate[0x20] = {
541 [IB_7220_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
542 [IB_7220_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
543 [IB_7220_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
544 [IB_7220_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
545 [IB_7220_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
546 [IB_7220_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
547 [IB_7220_LT_STATE_CFGDEBOUNCE] =
548 IB_PHYSPORTSTATE_CFG_TRAIN,
549 [IB_7220_LT_STATE_CFGRCVFCFG] =
550 IB_PHYSPORTSTATE_CFG_TRAIN,
551 [IB_7220_LT_STATE_CFGWAITRMT] =
552 IB_PHYSPORTSTATE_CFG_TRAIN,
553 [IB_7220_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
554 [IB_7220_LT_STATE_RECOVERRETRAIN] =
555 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
556 [IB_7220_LT_STATE_RECOVERWAITRMT] =
557 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
558 [IB_7220_LT_STATE_RECOVERIDLE] =
559 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
560 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
561 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
562 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
563 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
564 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
565 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
566 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
567 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
568 };
569
570 int qib_special_trigger;
571 module_param_named(special_trigger, qib_special_trigger, int, S_IRUGO);
572 MODULE_PARM_DESC(special_trigger, "Enable SpecialTrigger arm/launch");
573
574 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
575 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
576
577 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
578 (1ULL << (SYM_LSB(regname, fldname) + (bit))))
579
580 #define TXEMEMPARITYERR_PIOBUF \
581 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
582 #define TXEMEMPARITYERR_PIOPBC \
583 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
584 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
585 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
586
587 #define RXEMEMPARITYERR_RCVBUF \
588 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
589 #define RXEMEMPARITYERR_LOOKUPQ \
590 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
591 #define RXEMEMPARITYERR_EXPTID \
592 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
593 #define RXEMEMPARITYERR_EAGERTID \
594 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
595 #define RXEMEMPARITYERR_FLAGBUF \
596 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
597 #define RXEMEMPARITYERR_DATAINFO \
598 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
599 #define RXEMEMPARITYERR_HDRINFO \
600 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
601
602 /* 7220 specific hardware errors... */
603 static const struct qib_hwerror_msgs qib_7220_hwerror_msgs[] = {
604 /* generic hardware errors */
605 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
606 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
607
608 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
609 "TXE PIOBUF Memory Parity"),
610 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
611 "TXE PIOPBC Memory Parity"),
612 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
613 "TXE PIOLAUNCHFIFO Memory Parity"),
614
615 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
616 "RXE RCVBUF Memory Parity"),
617 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
618 "RXE LOOKUPQ Memory Parity"),
619 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
620 "RXE EAGERTID Memory Parity"),
621 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
622 "RXE EXPTID Memory Parity"),
623 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
624 "RXE FLAGBUF Memory Parity"),
625 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
626 "RXE DATAINFO Memory Parity"),
627 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
628 "RXE HDRINFO Memory Parity"),
629
630 /* chip-specific hardware errors */
631 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
632 "PCIe Poisoned TLP"),
633 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
634 "PCIe completion timeout"),
635 /*
636 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
637 * parity or memory parity error failures, because most likely we
638 * won't be able to talk to the core of the chip. Nonetheless, we
639 * might see them, if they are in parts of the PCIe core that aren't
640 * essential.
641 */
642 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
643 "PCIePLL1"),
644 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
645 "PCIePLL0"),
646 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
647 "PCIe XTLH core parity"),
648 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
649 "PCIe ADM TX core parity"),
650 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
651 "PCIe ADM RX core parity"),
652 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
653 "SerDes PLL"),
654 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR,
655 "PCIe cpl header queue"),
656 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR,
657 "PCIe cpl data queue"),
658 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SDMAMEMREADERR,
659 "Send DMA memory read"),
660 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED,
661 "uC PLL clock not locked"),
662 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT,
663 "PCIe serdes Q0 no clock"),
664 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT,
665 "PCIe serdes Q1 no clock"),
666 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT,
667 "PCIe serdes Q2 no clock"),
668 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT,
669 "PCIe serdes Q3 no clock"),
670 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR,
671 "DDS RXEQ memory parity"),
672 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR,
673 "IB uC memory parity"),
674 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR,
675 "PCIe uC oct0 memory parity"),
676 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR,
677 "PCIe uC oct1 memory parity"),
678 };
679
680 #define RXE_PARITY (RXEMEMPARITYERR_EAGERTID|RXEMEMPARITYERR_EXPTID)
681
682 #define QLOGIC_IB_E_PKTERRS (\
683 ERR_MASK(SendPktLenErr) | \
684 ERR_MASK(SendDroppedDataPktErr) | \
685 ERR_MASK(RcvVCRCErr) | \
686 ERR_MASK(RcvICRCErr) | \
687 ERR_MASK(RcvShortPktLenErr) | \
688 ERR_MASK(RcvEBPErr))
689
690 /* Convenience for decoding Send DMA errors */
691 #define QLOGIC_IB_E_SDMAERRS ( \
692 ERR_MASK(SDmaGenMismatchErr) | \
693 ERR_MASK(SDmaOutOfBoundErr) | \
694 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
695 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
696 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
697 ERR_MASK(SDmaUnexpDataErr) | \
698 ERR_MASK(SDmaDescAddrMisalignErr) | \
699 ERR_MASK(SDmaDisabledErr) | \
700 ERR_MASK(SendBufMisuseErr))
701
702 /* These are all rcv-related errors which we want to count for stats */
703 #define E_SUM_PKTERRS \
704 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
705 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
706 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
707 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
708 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
709 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
710
711 /* These are all send-related errors which we want to count for stats */
712 #define E_SUM_ERRS \
713 (ERR_MASK(SendPioArmLaunchErr) | ERR_MASK(SendUnexpectedPktNumErr) | \
714 ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
715 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
716 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
717 ERR_MASK(InvalidAddrErr))
718
719 /*
720 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
721 * errors not related to freeze and cancelling buffers. Can't ignore
722 * armlaunch because could get more while still cleaning up, and need
723 * to cancel those as they happen.
724 */
725 #define E_SPKT_ERRS_IGNORE \
726 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
727 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
728 ERR_MASK(SendPktLenErr))
729
730 /*
731 * these are errors that can occur when the link changes state while
732 * a packet is being sent or received. This doesn't cover things
733 * like EBP or VCRC that can be the result of a sending having the
734 * link change state, so we receive a "known bad" packet.
735 */
736 #define E_SUM_LINK_PKTERRS \
737 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
738 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
739 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
740 ERR_MASK(RcvUnexpectedCharErr))
741
742 static void autoneg_7220_work(struct work_struct *);
743 static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *, u64, u32 *);
744
745 /*
746 * Called when we might have an error that is specific to a particular
747 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
748 * because we don't need to force the update of pioavail.
749 */
750 static void qib_disarm_7220_senderrbufs(struct qib_pportdata *ppd)
751 {
752 unsigned long sbuf[3];
753 struct qib_devdata *dd = ppd->dd;
754
755 /*
756 * It's possible that sendbuffererror could have bits set; might
757 * have already done this as a result of hardware error handling.
758 */
759 /* read these before writing errorclear */
760 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
761 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
762 sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
763
764 if (sbuf[0] || sbuf[1] || sbuf[2])
765 qib_disarm_piobufs_set(dd, sbuf,
766 dd->piobcnt2k + dd->piobcnt4k);
767 }
768
769 static void qib_7220_txe_recover(struct qib_devdata *dd)
770 {
771 qib_devinfo(dd->pcidev, "Recovering from TXE PIO parity error\n");
772 qib_disarm_7220_senderrbufs(dd->pport);
773 }
774
775 /*
776 * This is called with interrupts disabled and sdma_lock held.
777 */
778 static void qib_7220_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
779 {
780 struct qib_devdata *dd = ppd->dd;
781 u64 set_sendctrl = 0;
782 u64 clr_sendctrl = 0;
783
784 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
785 set_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
786 else
787 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
788
789 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
790 set_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
791 else
792 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
793
794 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
795 set_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
796 else
797 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
798
799 spin_lock(&dd->sendctrl_lock);
800
801 dd->sendctrl |= set_sendctrl;
802 dd->sendctrl &= ~clr_sendctrl;
803
804 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
805 qib_write_kreg(dd, kr_scratch, 0);
806
807 spin_unlock(&dd->sendctrl_lock);
808 }
809
810 static void qib_decode_7220_sdma_errs(struct qib_pportdata *ppd,
811 u64 err, char *buf, size_t blen)
812 {
813 static const struct {
814 u64 err;
815 const char *msg;
816 } errs[] = {
817 { ERR_MASK(SDmaGenMismatchErr),
818 "SDmaGenMismatch" },
819 { ERR_MASK(SDmaOutOfBoundErr),
820 "SDmaOutOfBound" },
821 { ERR_MASK(SDmaTailOutOfBoundErr),
822 "SDmaTailOutOfBound" },
823 { ERR_MASK(SDmaBaseErr),
824 "SDmaBase" },
825 { ERR_MASK(SDma1stDescErr),
826 "SDma1stDesc" },
827 { ERR_MASK(SDmaRpyTagErr),
828 "SDmaRpyTag" },
829 { ERR_MASK(SDmaDwEnErr),
830 "SDmaDwEn" },
831 { ERR_MASK(SDmaMissingDwErr),
832 "SDmaMissingDw" },
833 { ERR_MASK(SDmaUnexpDataErr),
834 "SDmaUnexpData" },
835 { ERR_MASK(SDmaDescAddrMisalignErr),
836 "SDmaDescAddrMisalign" },
837 { ERR_MASK(SendBufMisuseErr),
838 "SendBufMisuse" },
839 { ERR_MASK(SDmaDisabledErr),
840 "SDmaDisabled" },
841 };
842 int i;
843 size_t bidx = 0;
844
845 for (i = 0; i < ARRAY_SIZE(errs); i++) {
846 if (err & errs[i].err)
847 bidx += scnprintf(buf + bidx, blen - bidx,
848 "%s ", errs[i].msg);
849 }
850 }
851
852 /*
853 * This is called as part of link down clean up so disarm and flush
854 * all send buffers so that SMP packets can be sent.
855 */
856 static void qib_7220_sdma_hw_clean_up(struct qib_pportdata *ppd)
857 {
858 /* This will trigger the Abort interrupt */
859 sendctrl_7220_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
860 QIB_SENDCTRL_AVAIL_BLIP);
861 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
862 }
863
864 static void qib_sdma_7220_setlengen(struct qib_pportdata *ppd)
865 {
866 /*
867 * Set SendDmaLenGen and clear and set
868 * the MSB of the generation count to enable generation checking
869 * and load the internal generation counter.
870 */
871 qib_write_kreg(ppd->dd, kr_senddmalengen, ppd->sdma_descq_cnt);
872 qib_write_kreg(ppd->dd, kr_senddmalengen,
873 ppd->sdma_descq_cnt |
874 (1ULL << QIB_7220_SendDmaLenGen_Generation_MSB));
875 }
876
877 static void qib_7220_sdma_hw_start_up(struct qib_pportdata *ppd)
878 {
879 qib_sdma_7220_setlengen(ppd);
880 qib_sdma_update_7220_tail(ppd, 0); /* Set SendDmaTail */
881 ppd->sdma_head_dma[0] = 0;
882 }
883
884 #define DISABLES_SDMA ( \
885 ERR_MASK(SDmaDisabledErr) | \
886 ERR_MASK(SDmaBaseErr) | \
887 ERR_MASK(SDmaTailOutOfBoundErr) | \
888 ERR_MASK(SDmaOutOfBoundErr) | \
889 ERR_MASK(SDma1stDescErr) | \
890 ERR_MASK(SDmaRpyTagErr) | \
891 ERR_MASK(SDmaGenMismatchErr) | \
892 ERR_MASK(SDmaDescAddrMisalignErr) | \
893 ERR_MASK(SDmaMissingDwErr) | \
894 ERR_MASK(SDmaDwEnErr))
895
896 static void sdma_7220_errors(struct qib_pportdata *ppd, u64 errs)
897 {
898 unsigned long flags;
899 struct qib_devdata *dd = ppd->dd;
900 char *msg;
901
902 errs &= QLOGIC_IB_E_SDMAERRS;
903
904 msg = dd->cspec->sdmamsgbuf;
905 qib_decode_7220_sdma_errs(ppd, errs, msg, sizeof dd->cspec->sdmamsgbuf);
906 spin_lock_irqsave(&ppd->sdma_lock, flags);
907
908 if (errs & ERR_MASK(SendBufMisuseErr)) {
909 unsigned long sbuf[3];
910
911 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
912 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
913 sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
914
915 qib_dev_err(ppd->dd,
916 "IB%u:%u SendBufMisuse: %04lx %016lx %016lx\n",
917 ppd->dd->unit, ppd->port, sbuf[2], sbuf[1],
918 sbuf[0]);
919 }
920
921 if (errs & ERR_MASK(SDmaUnexpDataErr))
922 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", ppd->dd->unit,
923 ppd->port);
924
925 switch (ppd->sdma_state.current_state) {
926 case qib_sdma_state_s00_hw_down:
927 /* not expecting any interrupts */
928 break;
929
930 case qib_sdma_state_s10_hw_start_up_wait:
931 /* handled in intr path */
932 break;
933
934 case qib_sdma_state_s20_idle:
935 /* not expecting any interrupts */
936 break;
937
938 case qib_sdma_state_s30_sw_clean_up_wait:
939 /* not expecting any interrupts */
940 break;
941
942 case qib_sdma_state_s40_hw_clean_up_wait:
943 if (errs & ERR_MASK(SDmaDisabledErr))
944 __qib_sdma_process_event(ppd,
945 qib_sdma_event_e50_hw_cleaned);
946 break;
947
948 case qib_sdma_state_s50_hw_halt_wait:
949 /* handled in intr path */
950 break;
951
952 case qib_sdma_state_s99_running:
953 if (errs & DISABLES_SDMA)
954 __qib_sdma_process_event(ppd,
955 qib_sdma_event_e7220_err_halted);
956 break;
957 }
958
959 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
960 }
961
962 /*
963 * Decode the error status into strings, deciding whether to always
964 * print * it or not depending on "normal packet errors" vs everything
965 * else. Return 1 if "real" errors, otherwise 0 if only packet
966 * errors, so caller can decide what to print with the string.
967 */
968 static int qib_decode_7220_err(struct qib_devdata *dd, char *buf, size_t blen,
969 u64 err)
970 {
971 int iserr = 1;
972
973 *buf = '\0';
974 if (err & QLOGIC_IB_E_PKTERRS) {
975 if (!(err & ~QLOGIC_IB_E_PKTERRS))
976 iserr = 0;
977 if ((err & ERR_MASK(RcvICRCErr)) &&
978 !(err & (ERR_MASK(RcvVCRCErr) | ERR_MASK(RcvEBPErr))))
979 strlcat(buf, "CRC ", blen);
980 if (!iserr)
981 goto done;
982 }
983 if (err & ERR_MASK(RcvHdrLenErr))
984 strlcat(buf, "rhdrlen ", blen);
985 if (err & ERR_MASK(RcvBadTidErr))
986 strlcat(buf, "rbadtid ", blen);
987 if (err & ERR_MASK(RcvBadVersionErr))
988 strlcat(buf, "rbadversion ", blen);
989 if (err & ERR_MASK(RcvHdrErr))
990 strlcat(buf, "rhdr ", blen);
991 if (err & ERR_MASK(SendSpecialTriggerErr))
992 strlcat(buf, "sendspecialtrigger ", blen);
993 if (err & ERR_MASK(RcvLongPktLenErr))
994 strlcat(buf, "rlongpktlen ", blen);
995 if (err & ERR_MASK(RcvMaxPktLenErr))
996 strlcat(buf, "rmaxpktlen ", blen);
997 if (err & ERR_MASK(RcvMinPktLenErr))
998 strlcat(buf, "rminpktlen ", blen);
999 if (err & ERR_MASK(SendMinPktLenErr))
1000 strlcat(buf, "sminpktlen ", blen);
1001 if (err & ERR_MASK(RcvFormatErr))
1002 strlcat(buf, "rformaterr ", blen);
1003 if (err & ERR_MASK(RcvUnsupportedVLErr))
1004 strlcat(buf, "runsupvl ", blen);
1005 if (err & ERR_MASK(RcvUnexpectedCharErr))
1006 strlcat(buf, "runexpchar ", blen);
1007 if (err & ERR_MASK(RcvIBFlowErr))
1008 strlcat(buf, "ribflow ", blen);
1009 if (err & ERR_MASK(SendUnderRunErr))
1010 strlcat(buf, "sunderrun ", blen);
1011 if (err & ERR_MASK(SendPioArmLaunchErr))
1012 strlcat(buf, "spioarmlaunch ", blen);
1013 if (err & ERR_MASK(SendUnexpectedPktNumErr))
1014 strlcat(buf, "sunexperrpktnum ", blen);
1015 if (err & ERR_MASK(SendDroppedSmpPktErr))
1016 strlcat(buf, "sdroppedsmppkt ", blen);
1017 if (err & ERR_MASK(SendMaxPktLenErr))
1018 strlcat(buf, "smaxpktlen ", blen);
1019 if (err & ERR_MASK(SendUnsupportedVLErr))
1020 strlcat(buf, "sunsupVL ", blen);
1021 if (err & ERR_MASK(InvalidAddrErr))
1022 strlcat(buf, "invalidaddr ", blen);
1023 if (err & ERR_MASK(RcvEgrFullErr))
1024 strlcat(buf, "rcvegrfull ", blen);
1025 if (err & ERR_MASK(RcvHdrFullErr))
1026 strlcat(buf, "rcvhdrfull ", blen);
1027 if (err & ERR_MASK(IBStatusChanged))
1028 strlcat(buf, "ibcstatuschg ", blen);
1029 if (err & ERR_MASK(RcvIBLostLinkErr))
1030 strlcat(buf, "riblostlink ", blen);
1031 if (err & ERR_MASK(HardwareErr))
1032 strlcat(buf, "hardware ", blen);
1033 if (err & ERR_MASK(ResetNegated))
1034 strlcat(buf, "reset ", blen);
1035 if (err & QLOGIC_IB_E_SDMAERRS)
1036 qib_decode_7220_sdma_errs(dd->pport, err, buf, blen);
1037 if (err & ERR_MASK(InvalidEEPCmd))
1038 strlcat(buf, "invalideepromcmd ", blen);
1039 done:
1040 return iserr;
1041 }
1042
1043 static void reenable_7220_chase(unsigned long opaque)
1044 {
1045 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1046 ppd->cpspec->chase_timer.expires = 0;
1047 qib_set_ib_7220_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1048 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1049 }
1050
1051 static void handle_7220_chase(struct qib_pportdata *ppd, u64 ibcst)
1052 {
1053 u8 ibclt;
1054 unsigned long tnow;
1055
1056 ibclt = (u8)SYM_FIELD(ibcst, IBCStatus, LinkTrainingState);
1057
1058 /*
1059 * Detect and handle the state chase issue, where we can
1060 * get stuck if we are unlucky on timing on both sides of
1061 * the link. If we are, we disable, set a timer, and
1062 * then re-enable.
1063 */
1064 switch (ibclt) {
1065 case IB_7220_LT_STATE_CFGRCVFCFG:
1066 case IB_7220_LT_STATE_CFGWAITRMT:
1067 case IB_7220_LT_STATE_TXREVLANES:
1068 case IB_7220_LT_STATE_CFGENH:
1069 tnow = jiffies;
1070 if (ppd->cpspec->chase_end &&
1071 time_after(tnow, ppd->cpspec->chase_end)) {
1072 ppd->cpspec->chase_end = 0;
1073 qib_set_ib_7220_lstate(ppd,
1074 QLOGIC_IB_IBCC_LINKCMD_DOWN,
1075 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1076 ppd->cpspec->chase_timer.expires = jiffies +
1077 QIB_CHASE_DIS_TIME;
1078 add_timer(&ppd->cpspec->chase_timer);
1079 } else if (!ppd->cpspec->chase_end)
1080 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1081 break;
1082
1083 default:
1084 ppd->cpspec->chase_end = 0;
1085 break;
1086 }
1087 }
1088
1089 static void handle_7220_errors(struct qib_devdata *dd, u64 errs)
1090 {
1091 char *msg;
1092 u64 ignore_this_time = 0;
1093 u64 iserr = 0;
1094 int log_idx;
1095 struct qib_pportdata *ppd = dd->pport;
1096 u64 mask;
1097
1098 /* don't report errors that are masked */
1099 errs &= dd->cspec->errormask;
1100 msg = dd->cspec->emsgbuf;
1101
1102 /* do these first, they are most important */
1103 if (errs & ERR_MASK(HardwareErr))
1104 qib_7220_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1105 else
1106 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1107 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1108 qib_inc_eeprom_err(dd, log_idx, 1);
1109
1110 if (errs & QLOGIC_IB_E_SDMAERRS)
1111 sdma_7220_errors(ppd, errs);
1112
1113 if (errs & ~IB_E_BITSEXTANT)
1114 qib_dev_err(dd,
1115 "error interrupt with unknown errors %llx set\n",
1116 (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1117
1118 if (errs & E_SUM_ERRS) {
1119 qib_disarm_7220_senderrbufs(ppd);
1120 if ((errs & E_SUM_LINK_PKTERRS) &&
1121 !(ppd->lflags & QIBL_LINKACTIVE)) {
1122 /*
1123 * This can happen when trying to bring the link
1124 * up, but the IB link changes state at the "wrong"
1125 * time. The IB logic then complains that the packet
1126 * isn't valid. We don't want to confuse people, so
1127 * we just don't print them, except at debug
1128 */
1129 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1130 }
1131 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1132 !(ppd->lflags & QIBL_LINKACTIVE)) {
1133 /*
1134 * This can happen when SMA is trying to bring the link
1135 * up, but the IB link changes state at the "wrong" time.
1136 * The IB logic then complains that the packet isn't
1137 * valid. We don't want to confuse people, so we just
1138 * don't print them, except at debug
1139 */
1140 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1141 }
1142
1143 qib_write_kreg(dd, kr_errclear, errs);
1144
1145 errs &= ~ignore_this_time;
1146 if (!errs)
1147 goto done;
1148
1149 /*
1150 * The ones we mask off are handled specially below
1151 * or above. Also mask SDMADISABLED by default as it
1152 * is too chatty.
1153 */
1154 mask = ERR_MASK(IBStatusChanged) |
1155 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) |
1156 ERR_MASK(HardwareErr) | ERR_MASK(SDmaDisabledErr);
1157
1158 qib_decode_7220_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1159
1160 if (errs & E_SUM_PKTERRS)
1161 qib_stats.sps_rcverrs++;
1162 if (errs & E_SUM_ERRS)
1163 qib_stats.sps_txerrs++;
1164 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS |
1165 ERR_MASK(SDmaDisabledErr));
1166
1167 if (errs & ERR_MASK(IBStatusChanged)) {
1168 u64 ibcs;
1169
1170 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1171 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1172 handle_7220_chase(ppd, ibcs);
1173
1174 /* Update our picture of width and speed from chip */
1175 ppd->link_width_active =
1176 ((ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1) ?
1177 IB_WIDTH_4X : IB_WIDTH_1X;
1178 ppd->link_speed_active =
1179 ((ibcs >> IBA7220_LINKSPEED_SHIFT) & 1) ?
1180 QIB_IB_DDR : QIB_IB_SDR;
1181
1182 /*
1183 * Since going into a recovery state causes the link state
1184 * to go down and since recovery is transitory, it is better
1185 * if we "miss" ever seeing the link training state go into
1186 * recovery (i.e., ignore this transition for link state
1187 * special handling purposes) without updating lastibcstat.
1188 */
1189 if (qib_7220_phys_portstate(ibcs) !=
1190 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1191 qib_handle_e_ibstatuschanged(ppd, ibcs);
1192 }
1193
1194 if (errs & ERR_MASK(ResetNegated)) {
1195 qib_dev_err(dd,
1196 "Got reset, requires re-init (unload and reload driver)\n");
1197 dd->flags &= ~QIB_INITTED; /* needs re-init */
1198 /* mark as having had error */
1199 *dd->devstatusp |= QIB_STATUS_HWERROR;
1200 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1201 }
1202
1203 if (*msg && iserr)
1204 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1205
1206 if (ppd->state_wanted & ppd->lflags)
1207 wake_up_interruptible(&ppd->state_wait);
1208
1209 /*
1210 * If there were hdrq or egrfull errors, wake up any processes
1211 * waiting in poll. We used to try to check which contexts had
1212 * the overflow, but given the cost of that and the chip reads
1213 * to support it, it's better to just wake everybody up if we
1214 * get an overflow; waiters can poll again if it's not them.
1215 */
1216 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1217 qib_handle_urcv(dd, ~0U);
1218 if (errs & ERR_MASK(RcvEgrFullErr))
1219 qib_stats.sps_buffull++;
1220 else
1221 qib_stats.sps_hdrfull++;
1222 }
1223 done:
1224 return;
1225 }
1226
1227 /* enable/disable chip from delivering interrupts */
1228 static void qib_7220_set_intr_state(struct qib_devdata *dd, u32 enable)
1229 {
1230 if (enable) {
1231 if (dd->flags & QIB_BADINTR)
1232 return;
1233 qib_write_kreg(dd, kr_intmask, ~0ULL);
1234 /* force re-interrupt of any pending interrupts. */
1235 qib_write_kreg(dd, kr_intclear, 0ULL);
1236 } else
1237 qib_write_kreg(dd, kr_intmask, 0ULL);
1238 }
1239
1240 /*
1241 * Try to cleanup as much as possible for anything that might have gone
1242 * wrong while in freeze mode, such as pio buffers being written by user
1243 * processes (causing armlaunch), send errors due to going into freeze mode,
1244 * etc., and try to avoid causing extra interrupts while doing so.
1245 * Forcibly update the in-memory pioavail register copies after cleanup
1246 * because the chip won't do it while in freeze mode (the register values
1247 * themselves are kept correct).
1248 * Make sure that we don't lose any important interrupts by using the chip
1249 * feature that says that writing 0 to a bit in *clear that is set in
1250 * *status will cause an interrupt to be generated again (if allowed by
1251 * the *mask value).
1252 * This is in chip-specific code because of all of the register accesses,
1253 * even though the details are similar on most chips.
1254 */
1255 static void qib_7220_clear_freeze(struct qib_devdata *dd)
1256 {
1257 /* disable error interrupts, to avoid confusion */
1258 qib_write_kreg(dd, kr_errmask, 0ULL);
1259
1260 /* also disable interrupts; errormask is sometimes overwriten */
1261 qib_7220_set_intr_state(dd, 0);
1262
1263 qib_cancel_sends(dd->pport);
1264
1265 /* clear the freeze, and be sure chip saw it */
1266 qib_write_kreg(dd, kr_control, dd->control);
1267 qib_read_kreg32(dd, kr_scratch);
1268
1269 /* force in-memory update now we are out of freeze */
1270 qib_force_pio_avail_update(dd);
1271
1272 /*
1273 * force new interrupt if any hwerr, error or interrupt bits are
1274 * still set, and clear "safe" send packet errors related to freeze
1275 * and cancelling sends. Re-enable error interrupts before possible
1276 * force of re-interrupt on pending interrupts.
1277 */
1278 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1279 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1280 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1281 qib_7220_set_intr_state(dd, 1);
1282 }
1283
1284 /**
1285 * qib_7220_handle_hwerrors - display hardware errors.
1286 * @dd: the qlogic_ib device
1287 * @msg: the output buffer
1288 * @msgl: the size of the output buffer
1289 *
1290 * Use same msg buffer as regular errors to avoid excessive stack
1291 * use. Most hardware errors are catastrophic, but for right now,
1292 * we'll print them and continue. We reuse the same message buffer as
1293 * handle_7220_errors() to avoid excessive stack usage.
1294 */
1295 static void qib_7220_handle_hwerrors(struct qib_devdata *dd, char *msg,
1296 size_t msgl)
1297 {
1298 u64 hwerrs;
1299 u32 bits, ctrl;
1300 int isfatal = 0;
1301 char *bitsmsg;
1302 int log_idx;
1303
1304 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1305 if (!hwerrs)
1306 goto bail;
1307 if (hwerrs == ~0ULL) {
1308 qib_dev_err(dd,
1309 "Read of hardware error status failed (all bits set); ignoring\n");
1310 goto bail;
1311 }
1312 qib_stats.sps_hwerrs++;
1313
1314 /*
1315 * Always clear the error status register, except MEMBISTFAIL,
1316 * regardless of whether we continue or stop using the chip.
1317 * We want that set so we know it failed, even across driver reload.
1318 * We'll still ignore it in the hwerrmask. We do this partly for
1319 * diagnostics, but also for support.
1320 */
1321 qib_write_kreg(dd, kr_hwerrclear,
1322 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
1323
1324 hwerrs &= dd->cspec->hwerrmask;
1325
1326 /* We log some errors to EEPROM, check if we have any of those. */
1327 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1328 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
1329 qib_inc_eeprom_err(dd, log_idx, 1);
1330 if (hwerrs & ~(TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC |
1331 RXE_PARITY))
1332 qib_devinfo(dd->pcidev,
1333 "Hardware error: hwerr=0x%llx (cleared)\n",
1334 (unsigned long long) hwerrs);
1335
1336 if (hwerrs & ~IB_HWE_BITSEXTANT)
1337 qib_dev_err(dd,
1338 "hwerror interrupt with unknown errors %llx set\n",
1339 (unsigned long long) (hwerrs & ~IB_HWE_BITSEXTANT));
1340
1341 if (hwerrs & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR)
1342 qib_sd7220_clr_ibpar(dd);
1343
1344 ctrl = qib_read_kreg32(dd, kr_control);
1345 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
1346 /*
1347 * Parity errors in send memory are recoverable by h/w
1348 * just do housekeeping, exit freeze mode and continue.
1349 */
1350 if (hwerrs & (TXEMEMPARITYERR_PIOBUF |
1351 TXEMEMPARITYERR_PIOPBC)) {
1352 qib_7220_txe_recover(dd);
1353 hwerrs &= ~(TXEMEMPARITYERR_PIOBUF |
1354 TXEMEMPARITYERR_PIOPBC);
1355 }
1356 if (hwerrs)
1357 isfatal = 1;
1358 else
1359 qib_7220_clear_freeze(dd);
1360 }
1361
1362 *msg = '\0';
1363
1364 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
1365 isfatal = 1;
1366 strlcat(msg,
1367 "[Memory BIST test failed, InfiniPath hardware unusable]",
1368 msgl);
1369 /* ignore from now on, so disable until driver reloaded */
1370 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
1371 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1372 }
1373
1374 qib_format_hwerrors(hwerrs, qib_7220_hwerror_msgs,
1375 ARRAY_SIZE(qib_7220_hwerror_msgs), msg, msgl);
1376
1377 bitsmsg = dd->cspec->bitsmsgbuf;
1378 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
1379 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
1380 bits = (u32) ((hwerrs >>
1381 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
1382 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
1383 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1384 "[PCIe Mem Parity Errs %x] ", bits);
1385 strlcat(msg, bitsmsg, msgl);
1386 }
1387
1388 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
1389 QLOGIC_IB_HWE_COREPLL_RFSLIP)
1390
1391 if (hwerrs & _QIB_PLL_FAIL) {
1392 isfatal = 1;
1393 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1394 "[PLL failed (%llx), InfiniPath hardware unusable]",
1395 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
1396 strlcat(msg, bitsmsg, msgl);
1397 /* ignore from now on, so disable until driver reloaded */
1398 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
1399 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1400 }
1401
1402 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
1403 /*
1404 * If it occurs, it is left masked since the eternal
1405 * interface is unused.
1406 */
1407 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
1408 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1409 }
1410
1411 qib_dev_err(dd, "%s hardware error\n", msg);
1412
1413 if (isfatal && !dd->diag_client) {
1414 qib_dev_err(dd,
1415 "Fatal Hardware Error, no longer usable, SN %.16s\n",
1416 dd->serial);
1417 /*
1418 * For /sys status file and user programs to print; if no
1419 * trailing brace is copied, we'll know it was truncated.
1420 */
1421 if (dd->freezemsg)
1422 snprintf(dd->freezemsg, dd->freezelen,
1423 "{%s}", msg);
1424 qib_disable_after_error(dd);
1425 }
1426 bail:;
1427 }
1428
1429 /**
1430 * qib_7220_init_hwerrors - enable hardware errors
1431 * @dd: the qlogic_ib device
1432 *
1433 * now that we have finished initializing everything that might reasonably
1434 * cause a hardware error, and cleared those errors bits as they occur,
1435 * we can enable hardware errors in the mask (potentially enabling
1436 * freeze mode), and enable hardware errors as errors (along with
1437 * everything else) in errormask
1438 */
1439 static void qib_7220_init_hwerrors(struct qib_devdata *dd)
1440 {
1441 u64 val;
1442 u64 extsval;
1443
1444 extsval = qib_read_kreg64(dd, kr_extstatus);
1445
1446 if (!(extsval & (QLOGIC_IB_EXTS_MEMBIST_ENDTEST |
1447 QLOGIC_IB_EXTS_MEMBIST_DISABLED)))
1448 qib_dev_err(dd, "MemBIST did not complete!\n");
1449 if (extsval & QLOGIC_IB_EXTS_MEMBIST_DISABLED)
1450 qib_devinfo(dd->pcidev, "MemBIST is disabled.\n");
1451
1452 val = ~0ULL; /* default to all hwerrors become interrupts, */
1453
1454 val &= ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
1455 dd->cspec->hwerrmask = val;
1456
1457 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1458 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1459
1460 /* clear all */
1461 qib_write_kreg(dd, kr_errclear, ~0ULL);
1462 /* enable errors that are masked, at least this first time. */
1463 qib_write_kreg(dd, kr_errmask, ~0ULL);
1464 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1465 /* clear any interrupts up to this point (ints still not enabled) */
1466 qib_write_kreg(dd, kr_intclear, ~0ULL);
1467 }
1468
1469 /*
1470 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1471 * on chips that are count-based, rather than trigger-based. There is no
1472 * reference counting, but that's also fine, given the intended use.
1473 * Only chip-specific because it's all register accesses
1474 */
1475 static void qib_set_7220_armlaunch(struct qib_devdata *dd, u32 enable)
1476 {
1477 if (enable) {
1478 qib_write_kreg(dd, kr_errclear, ERR_MASK(SendPioArmLaunchErr));
1479 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1480 } else
1481 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1482 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1483 }
1484
1485 /*
1486 * Formerly took parameter <which> in pre-shifted,
1487 * pre-merged form with LinkCmd and LinkInitCmd
1488 * together, and assuming the zero was NOP.
1489 */
1490 static void qib_set_ib_7220_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1491 u16 linitcmd)
1492 {
1493 u64 mod_wd;
1494 struct qib_devdata *dd = ppd->dd;
1495 unsigned long flags;
1496
1497 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1498 /*
1499 * If we are told to disable, note that so link-recovery
1500 * code does not attempt to bring us back up.
1501 */
1502 spin_lock_irqsave(&ppd->lflags_lock, flags);
1503 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1504 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1505 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1506 /*
1507 * Any other linkinitcmd will lead to LINKDOWN and then
1508 * to INIT (if all is well), so clear flag to let
1509 * link-recovery code attempt to bring us back up.
1510 */
1511 spin_lock_irqsave(&ppd->lflags_lock, flags);
1512 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1513 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1514 }
1515
1516 mod_wd = (linkcmd << IBA7220_IBCC_LINKCMD_SHIFT) |
1517 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1518
1519 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl | mod_wd);
1520 /* write to chip to prevent back-to-back writes of ibc reg */
1521 qib_write_kreg(dd, kr_scratch, 0);
1522 }
1523
1524 /*
1525 * All detailed interaction with the SerDes has been moved to qib_sd7220.c
1526 *
1527 * The portion of IBA7220-specific bringup_serdes() that actually deals with
1528 * registers and memory within the SerDes itself is qib_sd7220_init().
1529 */
1530
1531 /**
1532 * qib_7220_bringup_serdes - bring up the serdes
1533 * @ppd: physical port on the qlogic_ib device
1534 */
1535 static int qib_7220_bringup_serdes(struct qib_pportdata *ppd)
1536 {
1537 struct qib_devdata *dd = ppd->dd;
1538 u64 val, prev_val, guid, ibc;
1539 int ret = 0;
1540
1541 /* Put IBC in reset, sends disabled */
1542 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1543 qib_write_kreg(dd, kr_control, 0ULL);
1544
1545 if (qib_compat_ddr_negotiate) {
1546 ppd->cpspec->ibdeltainprog = 1;
1547 ppd->cpspec->ibsymsnap = read_7220_creg32(dd, cr_ibsymbolerr);
1548 ppd->cpspec->iblnkerrsnap =
1549 read_7220_creg32(dd, cr_iblinkerrrecov);
1550 }
1551
1552 /* flowcontrolwatermark is in units of KBytes */
1553 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1554 /*
1555 * How often flowctrl sent. More or less in usecs; balance against
1556 * watermark value, so that in theory senders always get a flow
1557 * control update in time to not let the IB link go idle.
1558 */
1559 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1560 /* max error tolerance */
1561 ibc |= 0xfULL << SYM_LSB(IBCCtrl, PhyerrThreshold);
1562 /* use "real" buffer space for */
1563 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1564 /* IB credit flow control. */
1565 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1566 /*
1567 * set initial max size pkt IBC will send, including ICRC; it's the
1568 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1569 */
1570 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1571 ppd->cpspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1572
1573 /* initially come up waiting for TS1, without sending anything. */
1574 val = ppd->cpspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1575 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1576 qib_write_kreg(dd, kr_ibcctrl, val);
1577
1578 if (!ppd->cpspec->ibcddrctrl) {
1579 /* not on re-init after reset */
1580 ppd->cpspec->ibcddrctrl = qib_read_kreg64(dd, kr_ibcddrctrl);
1581
1582 if (ppd->link_speed_enabled == (QIB_IB_SDR | QIB_IB_DDR))
1583 ppd->cpspec->ibcddrctrl |=
1584 IBA7220_IBC_SPEED_AUTONEG_MASK |
1585 IBA7220_IBC_IBTA_1_2_MASK;
1586 else
1587 ppd->cpspec->ibcddrctrl |=
1588 ppd->link_speed_enabled == QIB_IB_DDR ?
1589 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
1590 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
1591 (IB_WIDTH_1X | IB_WIDTH_4X))
1592 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
1593 else
1594 ppd->cpspec->ibcddrctrl |=
1595 ppd->link_width_enabled == IB_WIDTH_4X ?
1596 IBA7220_IBC_WIDTH_4X_ONLY :
1597 IBA7220_IBC_WIDTH_1X_ONLY;
1598
1599 /* always enable these on driver reload, not sticky */
1600 ppd->cpspec->ibcddrctrl |=
1601 IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
1602 ppd->cpspec->ibcddrctrl |=
1603 IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
1604
1605 /* enable automatic lane reversal detection for receive */
1606 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_LANE_REV_SUPPORTED;
1607 } else
1608 /* write to chip to prevent back-to-back writes of ibc reg */
1609 qib_write_kreg(dd, kr_scratch, 0);
1610
1611 qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
1612 qib_write_kreg(dd, kr_scratch, 0);
1613
1614 qib_write_kreg(dd, kr_ncmodectrl, 0Ull);
1615 qib_write_kreg(dd, kr_scratch, 0);
1616
1617 ret = qib_sd7220_init(dd);
1618
1619 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1620 prev_val = val;
1621 val |= QLOGIC_IB_XGXS_FC_SAFE;
1622 if (val != prev_val) {
1623 qib_write_kreg(dd, kr_xgxs_cfg, val);
1624 qib_read_kreg32(dd, kr_scratch);
1625 }
1626 if (val & QLOGIC_IB_XGXS_RESET)
1627 val &= ~QLOGIC_IB_XGXS_RESET;
1628 if (val != prev_val)
1629 qib_write_kreg(dd, kr_xgxs_cfg, val);
1630
1631 /* first time through, set port guid */
1632 if (!ppd->guid)
1633 ppd->guid = dd->base_guid;
1634 guid = be64_to_cpu(ppd->guid);
1635
1636 qib_write_kreg(dd, kr_hrtbt_guid, guid);
1637 if (!ret) {
1638 dd->control |= QLOGIC_IB_C_LINKENABLE;
1639 qib_write_kreg(dd, kr_control, dd->control);
1640 } else
1641 /* write to chip to prevent back-to-back writes of ibc reg */
1642 qib_write_kreg(dd, kr_scratch, 0);
1643 return ret;
1644 }
1645
1646 /**
1647 * qib_7220_quiet_serdes - set serdes to txidle
1648 * @ppd: physical port of the qlogic_ib device
1649 * Called when driver is being unloaded
1650 */
1651 static void qib_7220_quiet_serdes(struct qib_pportdata *ppd)
1652 {
1653 u64 val;
1654 struct qib_devdata *dd = ppd->dd;
1655 unsigned long flags;
1656
1657 /* disable IBC */
1658 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1659 qib_write_kreg(dd, kr_control,
1660 dd->control | QLOGIC_IB_C_FREEZEMODE);
1661
1662 ppd->cpspec->chase_end = 0;
1663 if (ppd->cpspec->chase_timer.data) /* if initted */
1664 del_timer_sync(&ppd->cpspec->chase_timer);
1665
1666 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
1667 ppd->cpspec->ibdeltainprog) {
1668 u64 diagc;
1669
1670 /* enable counter writes */
1671 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1672 qib_write_kreg(dd, kr_hwdiagctrl,
1673 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1674
1675 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
1676 val = read_7220_creg32(dd, cr_ibsymbolerr);
1677 if (ppd->cpspec->ibdeltainprog)
1678 val -= val - ppd->cpspec->ibsymsnap;
1679 val -= ppd->cpspec->ibsymdelta;
1680 write_7220_creg(dd, cr_ibsymbolerr, val);
1681 }
1682 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
1683 val = read_7220_creg32(dd, cr_iblinkerrrecov);
1684 if (ppd->cpspec->ibdeltainprog)
1685 val -= val - ppd->cpspec->iblnkerrsnap;
1686 val -= ppd->cpspec->iblnkerrdelta;
1687 write_7220_creg(dd, cr_iblinkerrrecov, val);
1688 }
1689
1690 /* and disable counter writes */
1691 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1692 }
1693 qib_set_ib_7220_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1694
1695 spin_lock_irqsave(&ppd->lflags_lock, flags);
1696 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
1697 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1698 wake_up(&ppd->cpspec->autoneg_wait);
1699 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
1700
1701 shutdown_7220_relock_poll(ppd->dd);
1702 val = qib_read_kreg64(ppd->dd, kr_xgxs_cfg);
1703 val |= QLOGIC_IB_XGXS_RESET;
1704 qib_write_kreg(ppd->dd, kr_xgxs_cfg, val);
1705 }
1706
1707 /**
1708 * qib_setup_7220_setextled - set the state of the two external LEDs
1709 * @dd: the qlogic_ib device
1710 * @on: whether the link is up or not
1711 *
1712 * The exact combo of LEDs if on is true is determined by looking
1713 * at the ibcstatus.
1714 *
1715 * These LEDs indicate the physical and logical state of IB link.
1716 * For this chip (at least with recommended board pinouts), LED1
1717 * is Yellow (logical state) and LED2 is Green (physical state),
1718 *
1719 * Note: We try to match the Mellanox HCA LED behavior as best
1720 * we can. Green indicates physical link state is OK (something is
1721 * plugged in, and we can train).
1722 * Amber indicates the link is logically up (ACTIVE).
1723 * Mellanox further blinks the amber LED to indicate data packet
1724 * activity, but we have no hardware support for that, so it would
1725 * require waking up every 10-20 msecs and checking the counters
1726 * on the chip, and then turning the LED off if appropriate. That's
1727 * visible overhead, so not something we will do.
1728 *
1729 */
1730 static void qib_setup_7220_setextled(struct qib_pportdata *ppd, u32 on)
1731 {
1732 struct qib_devdata *dd = ppd->dd;
1733 u64 extctl, ledblink = 0, val, lst, ltst;
1734 unsigned long flags;
1735
1736 /*
1737 * The diags use the LED to indicate diag info, so we leave
1738 * the external LED alone when the diags are running.
1739 */
1740 if (dd->diag_client)
1741 return;
1742
1743 if (ppd->led_override) {
1744 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1745 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1746 lst = (ppd->led_override & QIB_LED_LOG) ?
1747 IB_PORT_ACTIVE : IB_PORT_DOWN;
1748 } else if (on) {
1749 val = qib_read_kreg64(dd, kr_ibcstatus);
1750 ltst = qib_7220_phys_portstate(val);
1751 lst = qib_7220_iblink_state(val);
1752 } else {
1753 ltst = 0;
1754 lst = 0;
1755 }
1756
1757 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1758 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1759 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1760 if (ltst == IB_PHYSPORTSTATE_LINKUP) {
1761 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1762 /*
1763 * counts are in chip clock (4ns) periods.
1764 * This is 1/16 sec (66.6ms) on,
1765 * 3/16 sec (187.5 ms) off, with packets rcvd
1766 */
1767 ledblink = ((66600 * 1000UL / 4) << IBA7220_LEDBLINK_ON_SHIFT)
1768 | ((187500 * 1000UL / 4) << IBA7220_LEDBLINK_OFF_SHIFT);
1769 }
1770 if (lst == IB_PORT_ACTIVE)
1771 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1772 dd->cspec->extctrl = extctl;
1773 qib_write_kreg(dd, kr_extctrl, extctl);
1774 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1775
1776 if (ledblink) /* blink the LED on packet receive */
1777 qib_write_kreg(dd, kr_rcvpktledcnt, ledblink);
1778 }
1779
1780 static void qib_7220_free_irq(struct qib_devdata *dd)
1781 {
1782 if (dd->cspec->irq) {
1783 free_irq(dd->cspec->irq, dd);
1784 dd->cspec->irq = 0;
1785 }
1786 qib_nomsi(dd);
1787 }
1788
1789 /*
1790 * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1791 * @dd: the qlogic_ib device
1792 *
1793 * This is called during driver unload.
1794 *
1795 */
1796 static void qib_setup_7220_cleanup(struct qib_devdata *dd)
1797 {
1798 qib_7220_free_irq(dd);
1799 kfree(dd->cspec->cntrs);
1800 kfree(dd->cspec->portcntrs);
1801 }
1802
1803 /*
1804 * This is only called for SDmaInt.
1805 * SDmaDisabled is handled on the error path.
1806 */
1807 static void sdma_7220_intr(struct qib_pportdata *ppd, u64 istat)
1808 {
1809 unsigned long flags;
1810
1811 spin_lock_irqsave(&ppd->sdma_lock, flags);
1812
1813 switch (ppd->sdma_state.current_state) {
1814 case qib_sdma_state_s00_hw_down:
1815 break;
1816
1817 case qib_sdma_state_s10_hw_start_up_wait:
1818 __qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
1819 break;
1820
1821 case qib_sdma_state_s20_idle:
1822 break;
1823
1824 case qib_sdma_state_s30_sw_clean_up_wait:
1825 break;
1826
1827 case qib_sdma_state_s40_hw_clean_up_wait:
1828 break;
1829
1830 case qib_sdma_state_s50_hw_halt_wait:
1831 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1832 break;
1833
1834 case qib_sdma_state_s99_running:
1835 /* too chatty to print here */
1836 __qib_sdma_intr(ppd);
1837 break;
1838 }
1839 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1840 }
1841
1842 static void qib_wantpiobuf_7220_intr(struct qib_devdata *dd, u32 needint)
1843 {
1844 unsigned long flags;
1845
1846 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1847 if (needint) {
1848 if (!(dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
1849 goto done;
1850 /*
1851 * blip the availupd off, next write will be on, so
1852 * we ensure an avail update, regardless of threshold or
1853 * buffers becoming free, whenever we want an interrupt
1854 */
1855 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl &
1856 ~SYM_MASK(SendCtrl, SendBufAvailUpd));
1857 qib_write_kreg(dd, kr_scratch, 0ULL);
1858 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
1859 } else
1860 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
1861 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1862 qib_write_kreg(dd, kr_scratch, 0ULL);
1863 done:
1864 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1865 }
1866
1867 /*
1868 * Handle errors and unusual events first, separate function
1869 * to improve cache hits for fast path interrupt handling.
1870 */
1871 static noinline void unlikely_7220_intr(struct qib_devdata *dd, u64 istat)
1872 {
1873 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1874 qib_dev_err(dd,
1875 "interrupt with unknown interrupts %Lx set\n",
1876 istat & ~QLOGIC_IB_I_BITSEXTANT);
1877
1878 if (istat & QLOGIC_IB_I_GPIO) {
1879 u32 gpiostatus;
1880
1881 /*
1882 * Boards for this chip currently don't use GPIO interrupts,
1883 * so clear by writing GPIOstatus to GPIOclear, and complain
1884 * to alert developer. To avoid endless repeats, clear
1885 * the bits in the mask, since there is some kind of
1886 * programming error or chip problem.
1887 */
1888 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1889 /*
1890 * In theory, writing GPIOstatus to GPIOclear could
1891 * have a bad side-effect on some diagnostic that wanted
1892 * to poll for a status-change, but the various shadows
1893 * make that problematic at best. Diags will just suppress
1894 * all GPIO interrupts during such tests.
1895 */
1896 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
1897
1898 if (gpiostatus) {
1899 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1900 u32 gpio_irq = mask & gpiostatus;
1901
1902 /*
1903 * A bit set in status and (chip) Mask register
1904 * would cause an interrupt. Since we are not
1905 * expecting any, report it. Also check that the
1906 * chip reflects our shadow, report issues,
1907 * and refresh from the shadow.
1908 */
1909 /*
1910 * Clear any troublemakers, and update chip
1911 * from shadow
1912 */
1913 dd->cspec->gpio_mask &= ~gpio_irq;
1914 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1915 }
1916 }
1917
1918 if (istat & QLOGIC_IB_I_ERROR) {
1919 u64 estat;
1920
1921 qib_stats.sps_errints++;
1922 estat = qib_read_kreg64(dd, kr_errstatus);
1923 if (!estat)
1924 qib_devinfo(dd->pcidev,
1925 "error interrupt (%Lx), but no error bits set!\n",
1926 istat);
1927 else
1928 handle_7220_errors(dd, estat);
1929 }
1930 }
1931
1932 static irqreturn_t qib_7220intr(int irq, void *data)
1933 {
1934 struct qib_devdata *dd = data;
1935 irqreturn_t ret;
1936 u64 istat;
1937 u64 ctxtrbits;
1938 u64 rmask;
1939 unsigned i;
1940
1941 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1942 /*
1943 * This return value is not great, but we do not want the
1944 * interrupt core code to remove our interrupt handler
1945 * because we don't appear to be handling an interrupt
1946 * during a chip reset.
1947 */
1948 ret = IRQ_HANDLED;
1949 goto bail;
1950 }
1951
1952 istat = qib_read_kreg64(dd, kr_intstatus);
1953
1954 if (unlikely(!istat)) {
1955 ret = IRQ_NONE; /* not our interrupt, or already handled */
1956 goto bail;
1957 }
1958 if (unlikely(istat == -1)) {
1959 qib_bad_intrstatus(dd);
1960 /* don't know if it was our interrupt or not */
1961 ret = IRQ_NONE;
1962 goto bail;
1963 }
1964
1965 this_cpu_inc(*dd->int_counter);
1966 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1967 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1968 unlikely_7220_intr(dd, istat);
1969
1970 /*
1971 * Clear the interrupt bits we found set, relatively early, so we
1972 * "know" know the chip will have seen this by the time we process
1973 * the queue, and will re-interrupt if necessary. The processor
1974 * itself won't take the interrupt again until we return.
1975 */
1976 qib_write_kreg(dd, kr_intclear, istat);
1977
1978 /*
1979 * Handle kernel receive queues before checking for pio buffers
1980 * available since receives can overflow; piobuf waiters can afford
1981 * a few extra cycles, since they were waiting anyway.
1982 */
1983 ctxtrbits = istat &
1984 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1985 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1986 if (ctxtrbits) {
1987 rmask = (1ULL << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1988 (1ULL << QLOGIC_IB_I_RCVURG_SHIFT);
1989 for (i = 0; i < dd->first_user_ctxt; i++) {
1990 if (ctxtrbits & rmask) {
1991 ctxtrbits &= ~rmask;
1992 qib_kreceive(dd->rcd[i], NULL, NULL);
1993 }
1994 rmask <<= 1;
1995 }
1996 if (ctxtrbits) {
1997 ctxtrbits =
1998 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1999 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
2000 qib_handle_urcv(dd, ctxtrbits);
2001 }
2002 }
2003
2004 /* only call for SDmaInt */
2005 if (istat & QLOGIC_IB_I_SDMAINT)
2006 sdma_7220_intr(dd->pport, istat);
2007
2008 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2009 qib_ib_piobufavail(dd);
2010
2011 ret = IRQ_HANDLED;
2012 bail:
2013 return ret;
2014 }
2015
2016 /*
2017 * Set up our chip-specific interrupt handler.
2018 * The interrupt type has already been setup, so
2019 * we just need to do the registration and error checking.
2020 * If we are using MSI interrupts, we may fall back to
2021 * INTx later, if the interrupt handler doesn't get called
2022 * within 1/2 second (see verify_interrupt()).
2023 */
2024 static void qib_setup_7220_interrupt(struct qib_devdata *dd)
2025 {
2026 if (!dd->cspec->irq)
2027 qib_dev_err(dd,
2028 "irq is 0, BIOS error? Interrupts won't work\n");
2029 else {
2030 int ret = request_irq(dd->cspec->irq, qib_7220intr,
2031 dd->msi_lo ? 0 : IRQF_SHARED,
2032 QIB_DRV_NAME, dd);
2033
2034 if (ret)
2035 qib_dev_err(dd,
2036 "Couldn't setup %s interrupt (irq=%d): %d\n",
2037 dd->msi_lo ? "MSI" : "INTx",
2038 dd->cspec->irq, ret);
2039 }
2040 }
2041
2042 /**
2043 * qib_7220_boardname - fill in the board name
2044 * @dd: the qlogic_ib device
2045 *
2046 * info is based on the board revision register
2047 */
2048 static void qib_7220_boardname(struct qib_devdata *dd)
2049 {
2050 char *n;
2051 u32 boardid, namelen;
2052
2053 boardid = SYM_FIELD(dd->revision, Revision,
2054 BoardID);
2055
2056 switch (boardid) {
2057 case 1:
2058 n = "InfiniPath_QLE7240";
2059 break;
2060 case 2:
2061 n = "InfiniPath_QLE7280";
2062 break;
2063 default:
2064 qib_dev_err(dd, "Unknown 7220 board with ID %u\n", boardid);
2065 n = "Unknown_InfiniPath_7220";
2066 break;
2067 }
2068
2069 namelen = strlen(n) + 1;
2070 dd->boardname = kmalloc(namelen, GFP_KERNEL);
2071 if (!dd->boardname)
2072 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
2073 else
2074 snprintf(dd->boardname, namelen, "%s", n);
2075
2076 if (dd->majrev != 5 || !dd->minrev || dd->minrev > 2)
2077 qib_dev_err(dd,
2078 "Unsupported InfiniPath hardware revision %u.%u!\n",
2079 dd->majrev, dd->minrev);
2080
2081 snprintf(dd->boardversion, sizeof(dd->boardversion),
2082 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
2083 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
2084 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
2085 dd->majrev, dd->minrev,
2086 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
2087 }
2088
2089 /*
2090 * This routine sleeps, so it can only be called from user context, not
2091 * from interrupt context.
2092 */
2093 static int qib_setup_7220_reset(struct qib_devdata *dd)
2094 {
2095 u64 val;
2096 int i;
2097 int ret;
2098 u16 cmdval;
2099 u8 int_line, clinesz;
2100 unsigned long flags;
2101
2102 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
2103
2104 /* Use dev_err so it shows up in logs, etc. */
2105 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
2106
2107 /* no interrupts till re-initted */
2108 qib_7220_set_intr_state(dd, 0);
2109
2110 dd->pport->cpspec->ibdeltainprog = 0;
2111 dd->pport->cpspec->ibsymdelta = 0;
2112 dd->pport->cpspec->iblnkerrdelta = 0;
2113
2114 /*
2115 * Keep chip from being accessed until we are ready. Use
2116 * writeq() directly, to allow the write even though QIB_PRESENT
2117 * isn't set.
2118 */
2119 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
2120 /* so we check interrupts work again */
2121 dd->z_int_counter = qib_int_counter(dd);
2122 val = dd->control | QLOGIC_IB_C_RESET;
2123 writeq(val, &dd->kregbase[kr_control]);
2124 mb(); /* prevent compiler reordering around actual reset */
2125
2126 for (i = 1; i <= 5; i++) {
2127 /*
2128 * Allow MBIST, etc. to complete; longer on each retry.
2129 * We sometimes get machine checks from bus timeout if no
2130 * response, so for now, make it *really* long.
2131 */
2132 msleep(1000 + (1 + i) * 2000);
2133
2134 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
2135
2136 /*
2137 * Use readq directly, so we don't need to mark it as PRESENT
2138 * until we get a successful indication that all is well.
2139 */
2140 val = readq(&dd->kregbase[kr_revision]);
2141 if (val == dd->revision) {
2142 dd->flags |= QIB_PRESENT; /* it's back */
2143 ret = qib_reinit_intr(dd);
2144 goto bail;
2145 }
2146 }
2147 ret = 0; /* failed */
2148
2149 bail:
2150 if (ret) {
2151 if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
2152 qib_dev_err(dd,
2153 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
2154
2155 /* hold IBC in reset, no sends, etc till later */
2156 qib_write_kreg(dd, kr_control, 0ULL);
2157
2158 /* clear the reset error, init error/hwerror mask */
2159 qib_7220_init_hwerrors(dd);
2160
2161 /* do setup similar to speed or link-width changes */
2162 if (dd->pport->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK)
2163 dd->cspec->presets_needed = 1;
2164 spin_lock_irqsave(&dd->pport->lflags_lock, flags);
2165 dd->pport->lflags |= QIBL_IB_FORCE_NOTIFY;
2166 dd->pport->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2167 spin_unlock_irqrestore(&dd->pport->lflags_lock, flags);
2168 }
2169
2170 return ret;
2171 }
2172
2173 /**
2174 * qib_7220_put_tid - write a TID to the chip
2175 * @dd: the qlogic_ib device
2176 * @tidptr: pointer to the expected TID (in chip) to update
2177 * @tidtype: 0 for eager, 1 for expected
2178 * @pa: physical address of in memory buffer; tidinvalid if freeing
2179 */
2180 static void qib_7220_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
2181 u32 type, unsigned long pa)
2182 {
2183 if (pa != dd->tidinvalid) {
2184 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
2185
2186 /* paranoia checks */
2187 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
2188 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
2189 pa);
2190 return;
2191 }
2192 if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
2193 qib_dev_err(dd,
2194 "Physical page address 0x%lx larger than supported\n",
2195 pa);
2196 return;
2197 }
2198
2199 if (type == RCVHQ_RCV_TYPE_EAGER)
2200 chippa |= dd->tidtemplate;
2201 else /* for now, always full 4KB page */
2202 chippa |= IBA7220_TID_SZ_4K;
2203 pa = chippa;
2204 }
2205 writeq(pa, tidptr);
2206 mmiowb();
2207 }
2208
2209 /**
2210 * qib_7220_clear_tids - clear all TID entries for a ctxt, expected and eager
2211 * @dd: the qlogic_ib device
2212 * @ctxt: the ctxt
2213 *
2214 * clear all TID entries for a ctxt, expected and eager.
2215 * Used from qib_close(). On this chip, TIDs are only 32 bits,
2216 * not 64, but they are still on 64 bit boundaries, so tidbase
2217 * is declared as u64 * for the pointer math, even though we write 32 bits
2218 */
2219 static void qib_7220_clear_tids(struct qib_devdata *dd,
2220 struct qib_ctxtdata *rcd)
2221 {
2222 u64 __iomem *tidbase;
2223 unsigned long tidinv;
2224 u32 ctxt;
2225 int i;
2226
2227 if (!dd->kregbase || !rcd)
2228 return;
2229
2230 ctxt = rcd->ctxt;
2231
2232 tidinv = dd->tidinvalid;
2233 tidbase = (u64 __iomem *)
2234 ((char __iomem *)(dd->kregbase) +
2235 dd->rcvtidbase +
2236 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
2237
2238 for (i = 0; i < dd->rcvtidcnt; i++)
2239 qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
2240 tidinv);
2241
2242 tidbase = (u64 __iomem *)
2243 ((char __iomem *)(dd->kregbase) +
2244 dd->rcvegrbase +
2245 rcd->rcvegr_tid_base * sizeof(*tidbase));
2246
2247 for (i = 0; i < rcd->rcvegrcnt; i++)
2248 qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2249 tidinv);
2250 }
2251
2252 /**
2253 * qib_7220_tidtemplate - setup constants for TID updates
2254 * @dd: the qlogic_ib device
2255 *
2256 * We setup stuff that we use a lot, to avoid calculating each time
2257 */
2258 static void qib_7220_tidtemplate(struct qib_devdata *dd)
2259 {
2260 if (dd->rcvegrbufsize == 2048)
2261 dd->tidtemplate = IBA7220_TID_SZ_2K;
2262 else if (dd->rcvegrbufsize == 4096)
2263 dd->tidtemplate = IBA7220_TID_SZ_4K;
2264 dd->tidinvalid = 0;
2265 }
2266
2267 /**
2268 * qib_init_7220_get_base_info - set chip-specific flags for user code
2269 * @rcd: the qlogic_ib ctxt
2270 * @kbase: qib_base_info pointer
2271 *
2272 * We set the PCIE flag because the lower bandwidth on PCIe vs
2273 * HyperTransport can affect some user packet algorithims.
2274 */
2275 static int qib_7220_get_base_info(struct qib_ctxtdata *rcd,
2276 struct qib_base_info *kinfo)
2277 {
2278 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2279 QIB_RUNTIME_NODMA_RTAIL | QIB_RUNTIME_SDMA;
2280
2281 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
2282 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
2283
2284 return 0;
2285 }
2286
2287 static struct qib_message_header *
2288 qib_7220_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2289 {
2290 u32 offset = qib_hdrget_offset(rhf_addr);
2291
2292 return (struct qib_message_header *)
2293 (rhf_addr - dd->rhf_offset + offset);
2294 }
2295
2296 static void qib_7220_config_ctxts(struct qib_devdata *dd)
2297 {
2298 unsigned long flags;
2299 u32 nchipctxts;
2300
2301 nchipctxts = qib_read_kreg32(dd, kr_portcnt);
2302 dd->cspec->numctxts = nchipctxts;
2303 if (qib_n_krcv_queues > 1) {
2304 dd->qpn_mask = 0x3e;
2305 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2306 if (dd->first_user_ctxt > nchipctxts)
2307 dd->first_user_ctxt = nchipctxts;
2308 } else
2309 dd->first_user_ctxt = dd->num_pports;
2310 dd->n_krcv_queues = dd->first_user_ctxt;
2311
2312 if (!qib_cfgctxts) {
2313 int nctxts = dd->first_user_ctxt + num_online_cpus();
2314
2315 if (nctxts <= 5)
2316 dd->ctxtcnt = 5;
2317 else if (nctxts <= 9)
2318 dd->ctxtcnt = 9;
2319 else if (nctxts <= nchipctxts)
2320 dd->ctxtcnt = nchipctxts;
2321 } else if (qib_cfgctxts <= nchipctxts)
2322 dd->ctxtcnt = qib_cfgctxts;
2323 if (!dd->ctxtcnt) /* none of the above, set to max */
2324 dd->ctxtcnt = nchipctxts;
2325
2326 /*
2327 * Chip can be configured for 5, 9, or 17 ctxts, and choice
2328 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
2329 * Lock to be paranoid about later motion, etc.
2330 */
2331 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2332 if (dd->ctxtcnt > 9)
2333 dd->rcvctrl |= 2ULL << IBA7220_R_CTXTCFG_SHIFT;
2334 else if (dd->ctxtcnt > 5)
2335 dd->rcvctrl |= 1ULL << IBA7220_R_CTXTCFG_SHIFT;
2336 /* else configure for default 5 receive ctxts */
2337 if (dd->qpn_mask)
2338 dd->rcvctrl |= 1ULL << QIB_7220_RcvCtrl_RcvQPMapEnable_LSB;
2339 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2340 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2341
2342 /* kr_rcvegrcnt changes based on the number of contexts enabled */
2343 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
2344 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, IBA7220_KRCVEGRCNT);
2345 }
2346
2347 static int qib_7220_get_ib_cfg(struct qib_pportdata *ppd, int which)
2348 {
2349 int lsb, ret = 0;
2350 u64 maskr; /* right-justified mask */
2351
2352 switch (which) {
2353 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
2354 ret = ppd->link_width_enabled;
2355 goto done;
2356
2357 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
2358 ret = ppd->link_width_active;
2359 goto done;
2360
2361 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
2362 ret = ppd->link_speed_enabled;
2363 goto done;
2364
2365 case QIB_IB_CFG_SPD: /* Get current Link spd */
2366 ret = ppd->link_speed_active;
2367 goto done;
2368
2369 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
2370 lsb = IBA7220_IBC_RXPOL_SHIFT;
2371 maskr = IBA7220_IBC_RXPOL_MASK;
2372 break;
2373
2374 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
2375 lsb = IBA7220_IBC_LREV_SHIFT;
2376 maskr = IBA7220_IBC_LREV_MASK;
2377 break;
2378
2379 case QIB_IB_CFG_LINKLATENCY:
2380 ret = qib_read_kreg64(ppd->dd, kr_ibcddrstatus)
2381 & IBA7220_DDRSTAT_LINKLAT_MASK;
2382 goto done;
2383
2384 case QIB_IB_CFG_OP_VLS:
2385 ret = ppd->vls_operational;
2386 goto done;
2387
2388 case QIB_IB_CFG_VL_HIGH_CAP:
2389 ret = 0;
2390 goto done;
2391
2392 case QIB_IB_CFG_VL_LOW_CAP:
2393 ret = 0;
2394 goto done;
2395
2396 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2397 ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2398 OverrunThreshold);
2399 goto done;
2400
2401 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2402 ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2403 PhyerrThreshold);
2404 goto done;
2405
2406 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2407 /* will only take effect when the link state changes */
2408 ret = (ppd->cpspec->ibcctrl &
2409 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2410 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2411 goto done;
2412
2413 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2414 lsb = IBA7220_IBC_HRTBT_SHIFT;
2415 maskr = IBA7220_IBC_HRTBT_MASK;
2416 break;
2417
2418 case QIB_IB_CFG_PMA_TICKS:
2419 /*
2420 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
2421 * Since the clock is always 250MHz, the value is 1 or 0.
2422 */
2423 ret = (ppd->link_speed_active == QIB_IB_DDR);
2424 goto done;
2425
2426 default:
2427 ret = -EINVAL;
2428 goto done;
2429 }
2430 ret = (int)((ppd->cpspec->ibcddrctrl >> lsb) & maskr);
2431 done:
2432 return ret;
2433 }
2434
2435 static int qib_7220_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2436 {
2437 struct qib_devdata *dd = ppd->dd;
2438 u64 maskr; /* right-justified mask */
2439 int lsb, ret = 0, setforce = 0;
2440 u16 lcmd, licmd;
2441 unsigned long flags;
2442 u32 tmp = 0;
2443
2444 switch (which) {
2445 case QIB_IB_CFG_LIDLMC:
2446 /*
2447 * Set LID and LMC. Combined to avoid possible hazard
2448 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2449 */
2450 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2451 maskr = IBA7220_IBC_DLIDLMC_MASK;
2452 break;
2453
2454 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
2455 /*
2456 * As with speed, only write the actual register if
2457 * the link is currently down, otherwise takes effect
2458 * on next link change.
2459 */
2460 ppd->link_width_enabled = val;
2461 if (!(ppd->lflags & QIBL_LINKDOWN))
2462 goto bail;
2463 /*
2464 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2465 * will get called because we want update
2466 * link_width_active, and the change may not take
2467 * effect for some time (if we are in POLL), so this
2468 * flag will force the updown routine to be called
2469 * on the next ibstatuschange down interrupt, even
2470 * if it's not an down->up transition.
2471 */
2472 val--; /* convert from IB to chip */
2473 maskr = IBA7220_IBC_WIDTH_MASK;
2474 lsb = IBA7220_IBC_WIDTH_SHIFT;
2475 setforce = 1;
2476 break;
2477
2478 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2479 /*
2480 * If we turn off IB1.2, need to preset SerDes defaults,
2481 * but not right now. Set a flag for the next time
2482 * we command the link down. As with width, only write the
2483 * actual register if the link is currently down, otherwise
2484 * takes effect on next link change. Since setting is being
2485 * explicitly requested (via MAD or sysfs), clear autoneg
2486 * failure status if speed autoneg is enabled.
2487 */
2488 ppd->link_speed_enabled = val;
2489 if ((ppd->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK) &&
2490 !(val & (val - 1)))
2491 dd->cspec->presets_needed = 1;
2492 if (!(ppd->lflags & QIBL_LINKDOWN))
2493 goto bail;
2494 /*
2495 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2496 * will get called because we want update
2497 * link_speed_active, and the change may not take
2498 * effect for some time (if we are in POLL), so this
2499 * flag will force the updown routine to be called
2500 * on the next ibstatuschange down interrupt, even
2501 * if it's not an down->up transition.
2502 */
2503 if (val == (QIB_IB_SDR | QIB_IB_DDR)) {
2504 val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2505 IBA7220_IBC_IBTA_1_2_MASK;
2506 spin_lock_irqsave(&ppd->lflags_lock, flags);
2507 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2508 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2509 } else
2510 val = val == QIB_IB_DDR ?
2511 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2512 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2513 IBA7220_IBC_IBTA_1_2_MASK;
2514 /* IBTA 1.2 mode + speed bits are contiguous */
2515 lsb = SYM_LSB(IBCDDRCtrl, IB_ENHANCED_MODE);
2516 setforce = 1;
2517 break;
2518
2519 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2520 lsb = IBA7220_IBC_RXPOL_SHIFT;
2521 maskr = IBA7220_IBC_RXPOL_MASK;
2522 break;
2523
2524 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2525 lsb = IBA7220_IBC_LREV_SHIFT;
2526 maskr = IBA7220_IBC_LREV_MASK;
2527 break;
2528
2529 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2530 maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2531 OverrunThreshold);
2532 if (maskr != val) {
2533 ppd->cpspec->ibcctrl &=
2534 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2535 ppd->cpspec->ibcctrl |= (u64) val <<
2536 SYM_LSB(IBCCtrl, OverrunThreshold);
2537 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2538 qib_write_kreg(dd, kr_scratch, 0);
2539 }
2540 goto bail;
2541
2542 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2543 maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2544 PhyerrThreshold);
2545 if (maskr != val) {
2546 ppd->cpspec->ibcctrl &=
2547 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2548 ppd->cpspec->ibcctrl |= (u64) val <<
2549 SYM_LSB(IBCCtrl, PhyerrThreshold);
2550 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2551 qib_write_kreg(dd, kr_scratch, 0);
2552 }
2553 goto bail;
2554
2555 case QIB_IB_CFG_PKEYS: /* update pkeys */
2556 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2557 ((u64) ppd->pkeys[2] << 32) |
2558 ((u64) ppd->pkeys[3] << 48);
2559 qib_write_kreg(dd, kr_partitionkey, maskr);
2560 goto bail;
2561
2562 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2563 /* will only take effect when the link state changes */
2564 if (val == IB_LINKINITCMD_POLL)
2565 ppd->cpspec->ibcctrl &=
2566 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2567 else /* SLEEP */
2568 ppd->cpspec->ibcctrl |=
2569 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2570 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2571 qib_write_kreg(dd, kr_scratch, 0);
2572 goto bail;
2573
2574 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2575 /*
2576 * Update our housekeeping variables, and set IBC max
2577 * size, same as init code; max IBC is max we allow in
2578 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2579 * Set even if it's unchanged, print debug message only
2580 * on changes.
2581 */
2582 val = (ppd->ibmaxlen >> 2) + 1;
2583 ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2584 ppd->cpspec->ibcctrl |= (u64)val << SYM_LSB(IBCCtrl, MaxPktLen);
2585 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2586 qib_write_kreg(dd, kr_scratch, 0);
2587 goto bail;
2588
2589 case QIB_IB_CFG_LSTATE: /* set the IB link state */
2590 switch (val & 0xffff0000) {
2591 case IB_LINKCMD_DOWN:
2592 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2593 if (!ppd->cpspec->ibdeltainprog &&
2594 qib_compat_ddr_negotiate) {
2595 ppd->cpspec->ibdeltainprog = 1;
2596 ppd->cpspec->ibsymsnap =
2597 read_7220_creg32(dd, cr_ibsymbolerr);
2598 ppd->cpspec->iblnkerrsnap =
2599 read_7220_creg32(dd, cr_iblinkerrrecov);
2600 }
2601 break;
2602
2603 case IB_LINKCMD_ARMED:
2604 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2605 break;
2606
2607 case IB_LINKCMD_ACTIVE:
2608 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2609 break;
2610
2611 default:
2612 ret = -EINVAL;
2613 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2614 goto bail;
2615 }
2616 switch (val & 0xffff) {
2617 case IB_LINKINITCMD_NOP:
2618 licmd = 0;
2619 break;
2620
2621 case IB_LINKINITCMD_POLL:
2622 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2623 break;
2624
2625 case IB_LINKINITCMD_SLEEP:
2626 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2627 break;
2628
2629 case IB_LINKINITCMD_DISABLE:
2630 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2631 ppd->cpspec->chase_end = 0;
2632 /*
2633 * stop state chase counter and timer, if running.
2634 * wait forpending timer, but don't clear .data (ppd)!
2635 */
2636 if (ppd->cpspec->chase_timer.expires) {
2637 del_timer_sync(&ppd->cpspec->chase_timer);
2638 ppd->cpspec->chase_timer.expires = 0;
2639 }
2640 break;
2641
2642 default:
2643 ret = -EINVAL;
2644 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2645 val & 0xffff);
2646 goto bail;
2647 }
2648 qib_set_ib_7220_lstate(ppd, lcmd, licmd);
2649
2650 maskr = IBA7220_IBC_WIDTH_MASK;
2651 lsb = IBA7220_IBC_WIDTH_SHIFT;
2652 tmp = (ppd->cpspec->ibcddrctrl >> lsb) & maskr;
2653 /* If the width active on the chip does not match the
2654 * width in the shadow register, write the new active
2655 * width to the chip.
2656 * We don't have to worry about speed as the speed is taken
2657 * care of by set_7220_ibspeed_fast called by ib_updown.
2658 */
2659 if (ppd->link_width_enabled-1 != tmp) {
2660 ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2661 ppd->cpspec->ibcddrctrl |=
2662 (((u64)(ppd->link_width_enabled-1) & maskr) <<
2663 lsb);
2664 qib_write_kreg(dd, kr_ibcddrctrl,
2665 ppd->cpspec->ibcddrctrl);
2666 qib_write_kreg(dd, kr_scratch, 0);
2667 spin_lock_irqsave(&ppd->lflags_lock, flags);
2668 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2669 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2670 }
2671 goto bail;
2672
2673 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2674 if (val > IBA7220_IBC_HRTBT_MASK) {
2675 ret = -EINVAL;
2676 goto bail;
2677 }
2678 lsb = IBA7220_IBC_HRTBT_SHIFT;
2679 maskr = IBA7220_IBC_HRTBT_MASK;
2680 break;
2681
2682 default:
2683 ret = -EINVAL;
2684 goto bail;
2685 }
2686 ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2687 ppd->cpspec->ibcddrctrl |= (((u64) val & maskr) << lsb);
2688 qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
2689 qib_write_kreg(dd, kr_scratch, 0);
2690 if (setforce) {
2691 spin_lock_irqsave(&ppd->lflags_lock, flags);
2692 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2693 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2694 }
2695 bail:
2696 return ret;
2697 }
2698
2699 static int qib_7220_set_loopback(struct qib_pportdata *ppd, const char *what)
2700 {
2701 int ret = 0;
2702 u64 val, ddr;
2703
2704 if (!strncmp(what, "ibc", 3)) {
2705 ppd->cpspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2706 val = 0; /* disable heart beat, so link will come up */
2707 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2708 ppd->dd->unit, ppd->port);
2709 } else if (!strncmp(what, "off", 3)) {
2710 ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2711 /* enable heart beat again */
2712 val = IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
2713 qib_devinfo(ppd->dd->pcidev,
2714 "Disabling IB%u:%u IBC loopback (normal)\n",
2715 ppd->dd->unit, ppd->port);
2716 } else
2717 ret = -EINVAL;
2718 if (!ret) {
2719 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2720 ddr = ppd->cpspec->ibcddrctrl & ~(IBA7220_IBC_HRTBT_MASK
2721 << IBA7220_IBC_HRTBT_SHIFT);
2722 ppd->cpspec->ibcddrctrl = ddr | val;
2723 qib_write_kreg(ppd->dd, kr_ibcddrctrl,
2724 ppd->cpspec->ibcddrctrl);
2725 qib_write_kreg(ppd->dd, kr_scratch, 0);
2726 }
2727 return ret;
2728 }
2729
2730 static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2731 u32 updegr, u32 egrhd, u32 npkts)
2732 {
2733 if (updegr)
2734 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2735 mmiowb();
2736 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2737 mmiowb();
2738 }
2739
2740 static u32 qib_7220_hdrqempty(struct qib_ctxtdata *rcd)
2741 {
2742 u32 head, tail;
2743
2744 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2745 if (rcd->rcvhdrtail_kvaddr)
2746 tail = qib_get_rcvhdrtail(rcd);
2747 else
2748 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2749 return head == tail;
2750 }
2751
2752 /*
2753 * Modify the RCVCTRL register in chip-specific way. This
2754 * is a function because bit positions and (future) register
2755 * location is chip-specifc, but the needed operations are
2756 * generic. <op> is a bit-mask because we often want to
2757 * do multiple modifications.
2758 */
2759 static void rcvctrl_7220_mod(struct qib_pportdata *ppd, unsigned int op,
2760 int ctxt)
2761 {
2762 struct qib_devdata *dd = ppd->dd;
2763 u64 mask, val;
2764 unsigned long flags;
2765
2766 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2767 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2768 dd->rcvctrl |= (1ULL << IBA7220_R_TAILUPD_SHIFT);
2769 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2770 dd->rcvctrl &= ~(1ULL << IBA7220_R_TAILUPD_SHIFT);
2771 if (op & QIB_RCVCTRL_PKEY_ENB)
2772 dd->rcvctrl &= ~(1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2773 if (op & QIB_RCVCTRL_PKEY_DIS)
2774 dd->rcvctrl |= (1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2775 if (ctxt < 0)
2776 mask = (1ULL << dd->ctxtcnt) - 1;
2777 else
2778 mask = (1ULL << ctxt);
2779 if (op & QIB_RCVCTRL_CTXT_ENB) {
2780 /* always done for specific ctxt */
2781 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2782 if (!(dd->flags & QIB_NODMA_RTAIL))
2783 dd->rcvctrl |= 1ULL << IBA7220_R_TAILUPD_SHIFT;
2784 /* Write these registers before the context is enabled. */
2785 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2786 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2787 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2788 dd->rcd[ctxt]->rcvhdrq_phys);
2789 dd->rcd[ctxt]->seq_cnt = 1;
2790 }
2791 if (op & QIB_RCVCTRL_CTXT_DIS)
2792 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2793 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2794 dd->rcvctrl |= (mask << IBA7220_R_INTRAVAIL_SHIFT);
2795 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2796 dd->rcvctrl &= ~(mask << IBA7220_R_INTRAVAIL_SHIFT);
2797 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2798 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2799 /* arm rcv interrupt */
2800 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2801 dd->rhdrhead_intr_off;
2802 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2803 }
2804 if (op & QIB_RCVCTRL_CTXT_ENB) {
2805 /*
2806 * Init the context registers also; if we were
2807 * disabled, tail and head should both be zero
2808 * already from the enable, but since we don't
2809 * know, we have to do it explicitly.
2810 */
2811 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2812 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2813
2814 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2815 dd->rcd[ctxt]->head = val;
2816 /* If kctxt, interrupt on next receive. */
2817 if (ctxt < dd->first_user_ctxt)
2818 val |= dd->rhdrhead_intr_off;
2819 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2820 }
2821 if (op & QIB_RCVCTRL_CTXT_DIS) {
2822 if (ctxt >= 0) {
2823 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, 0);
2824 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, 0);
2825 } else {
2826 unsigned i;
2827
2828 for (i = 0; i < dd->cfgctxts; i++) {
2829 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2830 i, 0);
2831 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, i, 0);
2832 }
2833 }
2834 }
2835 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2836 }
2837
2838 /*
2839 * Modify the SENDCTRL register in chip-specific way. This
2840 * is a function there may be multiple such registers with
2841 * slightly different layouts. To start, we assume the
2842 * "canonical" register layout of the first chips.
2843 * Chip requires no back-back sendctrl writes, so write
2844 * scratch register after writing sendctrl
2845 */
2846 static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op)
2847 {
2848 struct qib_devdata *dd = ppd->dd;
2849 u64 tmp_dd_sendctrl;
2850 unsigned long flags;
2851
2852 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2853
2854 /* First the ones that are "sticky", saved in shadow */
2855 if (op & QIB_SENDCTRL_CLEAR)
2856 dd->sendctrl = 0;
2857 if (op & QIB_SENDCTRL_SEND_DIS)
2858 dd->sendctrl &= ~SYM_MASK(SendCtrl, SPioEnable);
2859 else if (op & QIB_SENDCTRL_SEND_ENB) {
2860 dd->sendctrl |= SYM_MASK(SendCtrl, SPioEnable);
2861 if (dd->flags & QIB_USE_SPCL_TRIG)
2862 dd->sendctrl |= SYM_MASK(SendCtrl,
2863 SSpecialTriggerEn);
2864 }
2865 if (op & QIB_SENDCTRL_AVAIL_DIS)
2866 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2867 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2868 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
2869
2870 if (op & QIB_SENDCTRL_DISARM_ALL) {
2871 u32 i, last;
2872
2873 tmp_dd_sendctrl = dd->sendctrl;
2874 /*
2875 * disarm any that are not yet launched, disabling sends
2876 * and updates until done.
2877 */
2878 last = dd->piobcnt2k + dd->piobcnt4k;
2879 tmp_dd_sendctrl &=
2880 ~(SYM_MASK(SendCtrl, SPioEnable) |
2881 SYM_MASK(SendCtrl, SendBufAvailUpd));
2882 for (i = 0; i < last; i++) {
2883 qib_write_kreg(dd, kr_sendctrl,
2884 tmp_dd_sendctrl |
2885 SYM_MASK(SendCtrl, Disarm) | i);
2886 qib_write_kreg(dd, kr_scratch, 0);
2887 }
2888 }
2889
2890 tmp_dd_sendctrl = dd->sendctrl;
2891
2892 if (op & QIB_SENDCTRL_FLUSH)
2893 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2894 if (op & QIB_SENDCTRL_DISARM)
2895 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2896 ((op & QIB_7220_SendCtrl_DisarmPIOBuf_RMASK) <<
2897 SYM_LSB(SendCtrl, DisarmPIOBuf));
2898 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
2899 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
2900 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2901
2902 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2903 qib_write_kreg(dd, kr_scratch, 0);
2904
2905 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2906 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2907 qib_write_kreg(dd, kr_scratch, 0);
2908 }
2909
2910 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2911
2912 if (op & QIB_SENDCTRL_FLUSH) {
2913 u32 v;
2914 /*
2915 * ensure writes have hit chip, then do a few
2916 * more reads, to allow DMA of pioavail registers
2917 * to occur, so in-memory copy is in sync with
2918 * the chip. Not always safe to sleep.
2919 */
2920 v = qib_read_kreg32(dd, kr_scratch);
2921 qib_write_kreg(dd, kr_scratch, v);
2922 v = qib_read_kreg32(dd, kr_scratch);
2923 qib_write_kreg(dd, kr_scratch, v);
2924 qib_read_kreg32(dd, kr_scratch);
2925 }
2926 }
2927
2928 /**
2929 * qib_portcntr_7220 - read a per-port counter
2930 * @dd: the qlogic_ib device
2931 * @creg: the counter to snapshot
2932 */
2933 static u64 qib_portcntr_7220(struct qib_pportdata *ppd, u32 reg)
2934 {
2935 u64 ret = 0ULL;
2936 struct qib_devdata *dd = ppd->dd;
2937 u16 creg;
2938 /* 0xffff for unimplemented or synthesized counters */
2939 static const u16 xlator[] = {
2940 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2941 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2942 [QIBPORTCNTR_PSXMITDATA] = cr_psxmitdatacount,
2943 [QIBPORTCNTR_PSXMITPKTS] = cr_psxmitpktscount,
2944 [QIBPORTCNTR_PSXMITWAIT] = cr_psxmitwaitcount,
2945 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2946 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2947 [QIBPORTCNTR_PSRCVDATA] = cr_psrcvdatacount,
2948 [QIBPORTCNTR_PSRCVPKTS] = cr_psrcvpktscount,
2949 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2950 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2951 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2952 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2953 [QIBPORTCNTR_RXLOCALPHYERR] = cr_rxotherlocalphyerr,
2954 [QIBPORTCNTR_RXVLERR] = cr_rxvlerr,
2955 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2956 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2957 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2958 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2959 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2960 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2961 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2962 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2963 [QIBPORTCNTR_EXCESSBUFOVFL] = cr_excessbufferovfl,
2964 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2965 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2966 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2967 [QIBPORTCNTR_LLI] = cr_locallinkintegrityerr,
2968 [QIBPORTCNTR_PSINTERVAL] = cr_psinterval,
2969 [QIBPORTCNTR_PSSTART] = cr_psstart,
2970 [QIBPORTCNTR_PSSTAT] = cr_psstat,
2971 [QIBPORTCNTR_VL15PKTDROP] = cr_vl15droppedpkt,
2972 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2973 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2974 };
2975
2976 if (reg >= ARRAY_SIZE(xlator)) {
2977 qib_devinfo(ppd->dd->pcidev,
2978 "Unimplemented portcounter %u\n", reg);
2979 goto done;
2980 }
2981 creg = xlator[reg];
2982
2983 if (reg == QIBPORTCNTR_KHDROVFL) {
2984 int i;
2985
2986 /* sum over all kernel contexts */
2987 for (i = 0; i < dd->first_user_ctxt; i++)
2988 ret += read_7220_creg32(dd, cr_portovfl + i);
2989 }
2990 if (creg == 0xffff)
2991 goto done;
2992
2993 /*
2994 * only fast incrementing counters are 64bit; use 32 bit reads to
2995 * avoid two independent reads when on opteron
2996 */
2997 if ((creg == cr_wordsend || creg == cr_wordrcv ||
2998 creg == cr_pktsend || creg == cr_pktrcv))
2999 ret = read_7220_creg(dd, creg);
3000 else
3001 ret = read_7220_creg32(dd, creg);
3002 if (creg == cr_ibsymbolerr) {
3003 if (dd->pport->cpspec->ibdeltainprog)
3004 ret -= ret - ppd->cpspec->ibsymsnap;
3005 ret -= dd->pport->cpspec->ibsymdelta;
3006 } else if (creg == cr_iblinkerrrecov) {
3007 if (dd->pport->cpspec->ibdeltainprog)
3008 ret -= ret - ppd->cpspec->iblnkerrsnap;
3009 ret -= dd->pport->cpspec->iblnkerrdelta;
3010 }
3011 done:
3012 return ret;
3013 }
3014
3015 /*
3016 * Device counter names (not port-specific), one line per stat,
3017 * single string. Used by utilities like ipathstats to print the stats
3018 * in a way which works for different versions of drivers, without changing
3019 * the utility. Names need to be 12 chars or less (w/o newline), for proper
3020 * display by utility.
3021 * Non-error counters are first.
3022 * Start of "error" conters is indicated by a leading "E " on the first
3023 * "error" counter, and doesn't count in label length.
3024 * The EgrOvfl list needs to be last so we truncate them at the configured
3025 * context count for the device.
3026 * cntr7220indices contains the corresponding register indices.
3027 */
3028 static const char cntr7220names[] =
3029 "Interrupts\n"
3030 "HostBusStall\n"
3031 "E RxTIDFull\n"
3032 "RxTIDInvalid\n"
3033 "Ctxt0EgrOvfl\n"
3034 "Ctxt1EgrOvfl\n"
3035 "Ctxt2EgrOvfl\n"
3036 "Ctxt3EgrOvfl\n"
3037 "Ctxt4EgrOvfl\n"
3038 "Ctxt5EgrOvfl\n"
3039 "Ctxt6EgrOvfl\n"
3040 "Ctxt7EgrOvfl\n"
3041 "Ctxt8EgrOvfl\n"
3042 "Ctxt9EgrOvfl\n"
3043 "Ctx10EgrOvfl\n"
3044 "Ctx11EgrOvfl\n"
3045 "Ctx12EgrOvfl\n"
3046 "Ctx13EgrOvfl\n"
3047 "Ctx14EgrOvfl\n"
3048 "Ctx15EgrOvfl\n"
3049 "Ctx16EgrOvfl\n";
3050
3051 static const size_t cntr7220indices[] = {
3052 cr_lbint,
3053 cr_lbflowstall,
3054 cr_errtidfull,
3055 cr_errtidvalid,
3056 cr_portovfl + 0,
3057 cr_portovfl + 1,
3058 cr_portovfl + 2,
3059 cr_portovfl + 3,
3060 cr_portovfl + 4,
3061 cr_portovfl + 5,
3062 cr_portovfl + 6,
3063 cr_portovfl + 7,
3064 cr_portovfl + 8,
3065 cr_portovfl + 9,
3066 cr_portovfl + 10,
3067 cr_portovfl + 11,
3068 cr_portovfl + 12,
3069 cr_portovfl + 13,
3070 cr_portovfl + 14,
3071 cr_portovfl + 15,
3072 cr_portovfl + 16,
3073 };
3074
3075 /*
3076 * same as cntr7220names and cntr7220indices, but for port-specific counters.
3077 * portcntr7220indices is somewhat complicated by some registers needing
3078 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
3079 */
3080 static const char portcntr7220names[] =
3081 "TxPkt\n"
3082 "TxFlowPkt\n"
3083 "TxWords\n"
3084 "RxPkt\n"
3085 "RxFlowPkt\n"
3086 "RxWords\n"
3087 "TxFlowStall\n"
3088 "TxDmaDesc\n" /* 7220 and 7322-only */
3089 "E RxDlidFltr\n" /* 7220 and 7322-only */
3090 "IBStatusChng\n"
3091 "IBLinkDown\n"
3092 "IBLnkRecov\n"
3093 "IBRxLinkErr\n"
3094 "IBSymbolErr\n"
3095 "RxLLIErr\n"
3096 "RxBadFormat\n"
3097 "RxBadLen\n"
3098 "RxBufOvrfl\n"
3099 "RxEBP\n"
3100 "RxFlowCtlErr\n"
3101 "RxICRCerr\n"
3102 "RxLPCRCerr\n"
3103 "RxVCRCerr\n"
3104 "RxInvalLen\n"
3105 "RxInvalPKey\n"
3106 "RxPktDropped\n"
3107 "TxBadLength\n"
3108 "TxDropped\n"
3109 "TxInvalLen\n"
3110 "TxUnderrun\n"
3111 "TxUnsupVL\n"
3112 "RxLclPhyErr\n" /* 7220 and 7322-only */
3113 "RxVL15Drop\n" /* 7220 and 7322-only */
3114 "RxVlErr\n" /* 7220 and 7322-only */
3115 "XcessBufOvfl\n" /* 7220 and 7322-only */
3116 ;
3117
3118 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
3119 static const size_t portcntr7220indices[] = {
3120 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
3121 cr_pktsendflow,
3122 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
3123 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
3124 cr_pktrcvflowctrl,
3125 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
3126 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
3127 cr_txsdmadesc,
3128 cr_rxdlidfltr,
3129 cr_ibstatuschange,
3130 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
3131 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
3132 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
3133 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
3134 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
3135 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
3136 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
3137 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
3138 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
3139 cr_rcvflowctrl_err,
3140 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
3141 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
3142 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
3143 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
3144 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
3145 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
3146 cr_invalidslen,
3147 cr_senddropped,
3148 cr_errslen,
3149 cr_sendunderrun,
3150 cr_txunsupvl,
3151 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
3152 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
3153 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
3154 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
3155 };
3156
3157 /* do all the setup to make the counter reads efficient later */
3158 static void init_7220_cntrnames(struct qib_devdata *dd)
3159 {
3160 int i, j = 0;
3161 char *s;
3162
3163 for (i = 0, s = (char *)cntr7220names; s && j <= dd->cfgctxts;
3164 i++) {
3165 /* we always have at least one counter before the egrovfl */
3166 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
3167 j = 1;
3168 s = strchr(s + 1, '\n');
3169 if (s && j)
3170 j++;
3171 }
3172 dd->cspec->ncntrs = i;
3173 if (!s)
3174 /* full list; size is without terminating null */
3175 dd->cspec->cntrnamelen = sizeof(cntr7220names) - 1;
3176 else
3177 dd->cspec->cntrnamelen = 1 + s - cntr7220names;
3178 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
3179 * sizeof(u64), GFP_KERNEL);
3180 if (!dd->cspec->cntrs)
3181 qib_dev_err(dd, "Failed allocation for counters\n");
3182
3183 for (i = 0, s = (char *)portcntr7220names; s; i++)
3184 s = strchr(s + 1, '\n');
3185 dd->cspec->nportcntrs = i - 1;
3186 dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1;
3187 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
3188 * sizeof(u64), GFP_KERNEL);
3189 if (!dd->cspec->portcntrs)
3190 qib_dev_err(dd, "Failed allocation for portcounters\n");
3191 }
3192
3193 static u32 qib_read_7220cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
3194 u64 **cntrp)
3195 {
3196 u32 ret;
3197
3198 if (!dd->cspec->cntrs) {
3199 ret = 0;
3200 goto done;
3201 }
3202
3203 if (namep) {
3204 *namep = (char *)cntr7220names;
3205 ret = dd->cspec->cntrnamelen;
3206 if (pos >= ret)
3207 ret = 0; /* final read after getting everything */
3208 } else {
3209 u64 *cntr = dd->cspec->cntrs;
3210 int i;
3211
3212 ret = dd->cspec->ncntrs * sizeof(u64);
3213 if (!cntr || pos >= ret) {
3214 /* everything read, or couldn't get memory */
3215 ret = 0;
3216 goto done;
3217 }
3218
3219 *cntrp = cntr;
3220 for (i = 0; i < dd->cspec->ncntrs; i++)
3221 *cntr++ = read_7220_creg32(dd, cntr7220indices[i]);
3222 }
3223 done:
3224 return ret;
3225 }
3226
3227 static u32 qib_read_7220portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
3228 char **namep, u64 **cntrp)
3229 {
3230 u32 ret;
3231
3232 if (!dd->cspec->portcntrs) {
3233 ret = 0;
3234 goto done;
3235 }
3236 if (namep) {
3237 *namep = (char *)portcntr7220names;
3238 ret = dd->cspec->portcntrnamelen;
3239 if (pos >= ret)
3240 ret = 0; /* final read after getting everything */
3241 } else {
3242 u64 *cntr = dd->cspec->portcntrs;
3243 struct qib_pportdata *ppd = &dd->pport[port];
3244 int i;
3245
3246 ret = dd->cspec->nportcntrs * sizeof(u64);
3247 if (!cntr || pos >= ret) {
3248 /* everything read, or couldn't get memory */
3249 ret = 0;
3250 goto done;
3251 }
3252 *cntrp = cntr;
3253 for (i = 0; i < dd->cspec->nportcntrs; i++) {
3254 if (portcntr7220indices[i] & _PORT_VIRT_FLAG)
3255 *cntr++ = qib_portcntr_7220(ppd,
3256 portcntr7220indices[i] &
3257 ~_PORT_VIRT_FLAG);
3258 else
3259 *cntr++ = read_7220_creg32(dd,
3260 portcntr7220indices[i]);
3261 }
3262 }
3263 done:
3264 return ret;
3265 }
3266
3267 /**
3268 * qib_get_7220_faststats - get word counters from chip before they overflow
3269 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
3270 *
3271 * This needs more work; in particular, decision on whether we really
3272 * need traffic_wds done the way it is
3273 * called from add_timer
3274 */
3275 static void qib_get_7220_faststats(unsigned long opaque)
3276 {
3277 struct qib_devdata *dd = (struct qib_devdata *) opaque;
3278 struct qib_pportdata *ppd = dd->pport;
3279 unsigned long flags;
3280 u64 traffic_wds;
3281
3282 /*
3283 * don't access the chip while running diags, or memory diags can
3284 * fail
3285 */
3286 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
3287 /* but re-arm the timer, for diags case; won't hurt other */
3288 goto done;
3289
3290 /*
3291 * We now try to maintain an activity timer, based on traffic
3292 * exceeding a threshold, so we need to check the word-counts
3293 * even if they are 64-bit.
3294 */
3295 traffic_wds = qib_portcntr_7220(ppd, cr_wordsend) +
3296 qib_portcntr_7220(ppd, cr_wordrcv);
3297 spin_lock_irqsave(&dd->eep_st_lock, flags);
3298 traffic_wds -= dd->traffic_wds;
3299 dd->traffic_wds += traffic_wds;
3300 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
3301 atomic_add(5, &dd->active_time); /* S/B #define */
3302 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
3303 done:
3304 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
3305 }
3306
3307 /*
3308 * If we are using MSI, try to fallback to INTx.
3309 */
3310 static int qib_7220_intr_fallback(struct qib_devdata *dd)
3311 {
3312 if (!dd->msi_lo)
3313 return 0;
3314
3315 qib_devinfo(dd->pcidev,
3316 "MSI interrupt not detected, trying INTx interrupts\n");
3317 qib_7220_free_irq(dd);
3318 qib_enable_intx(dd->pcidev);
3319 /*
3320 * Some newer kernels require free_irq before disable_msi,
3321 * and irq can be changed during disable and INTx enable
3322 * and we need to therefore use the pcidev->irq value,
3323 * not our saved MSI value.
3324 */
3325 dd->cspec->irq = dd->pcidev->irq;
3326 qib_setup_7220_interrupt(dd);
3327 return 1;
3328 }
3329
3330 /*
3331 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
3332 * than resetting the IBC or external link state, and useful in some
3333 * cases to cause some retraining. To do this right, we reset IBC
3334 * as well.
3335 */
3336 static void qib_7220_xgxs_reset(struct qib_pportdata *ppd)
3337 {
3338 u64 val, prev_val;
3339 struct qib_devdata *dd = ppd->dd;
3340
3341 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
3342 val = prev_val | QLOGIC_IB_XGXS_RESET;
3343 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
3344 qib_write_kreg(dd, kr_control,
3345 dd->control & ~QLOGIC_IB_C_LINKENABLE);
3346 qib_write_kreg(dd, kr_xgxs_cfg, val);
3347 qib_read_kreg32(dd, kr_scratch);
3348 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
3349 qib_write_kreg(dd, kr_control, dd->control);
3350 }
3351
3352 /*
3353 * For this chip, we want to use the same buffer every time
3354 * when we are trying to bring the link up (they are always VL15
3355 * packets). At that link state the packet should always go out immediately
3356 * (or at least be discarded at the tx interface if the link is down).
3357 * If it doesn't, and the buffer isn't available, that means some other
3358 * sender has gotten ahead of us, and is preventing our packet from going
3359 * out. In that case, we flush all packets, and try again. If that still
3360 * fails, we fail the request, and hope things work the next time around.
3361 *
3362 * We don't need very complicated heuristics on whether the packet had
3363 * time to go out or not, since even at SDR 1X, it goes out in very short
3364 * time periods, covered by the chip reads done here and as part of the
3365 * flush.
3366 */
3367 static u32 __iomem *get_7220_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3368 {
3369 u32 __iomem *buf;
3370 u32 lbuf = ppd->dd->cspec->lastbuf_for_pio;
3371 int do_cleanup;
3372 unsigned long flags;
3373
3374 /*
3375 * always blip to get avail list updated, since it's almost
3376 * always needed, and is fairly cheap.
3377 */
3378 sendctrl_7220_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3379 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3380 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3381 if (buf)
3382 goto done;
3383
3384 spin_lock_irqsave(&ppd->sdma_lock, flags);
3385 if (ppd->sdma_state.current_state == qib_sdma_state_s20_idle &&
3386 ppd->sdma_state.current_state != qib_sdma_state_s00_hw_down) {
3387 __qib_sdma_process_event(ppd, qib_sdma_event_e00_go_hw_down);
3388 do_cleanup = 0;
3389 } else {
3390 do_cleanup = 1;
3391 qib_7220_sdma_hw_clean_up(ppd);
3392 }
3393 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3394
3395 if (do_cleanup) {
3396 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3397 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3398 }
3399 done:
3400 return buf;
3401 }
3402
3403 /*
3404 * This code for non-IBTA-compliant IB speed negotiation is only known to
3405 * work for the SDR to DDR transition, and only between an HCA and a switch
3406 * with recent firmware. It is based on observed heuristics, rather than
3407 * actual knowledge of the non-compliant speed negotiation.
3408 * It has a number of hard-coded fields, since the hope is to rewrite this
3409 * when a spec is available on how the negoation is intended to work.
3410 */
3411 static void autoneg_7220_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
3412 u32 dcnt, u32 *data)
3413 {
3414 int i;
3415 u64 pbc;
3416 u32 __iomem *piobuf;
3417 u32 pnum;
3418 struct qib_devdata *dd = ppd->dd;
3419
3420 i = 0;
3421 pbc = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
3422 pbc |= PBC_7220_VL15_SEND;
3423 while (!(piobuf = get_7220_link_buf(ppd, &pnum))) {
3424 if (i++ > 5)
3425 return;
3426 udelay(2);
3427 }
3428 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_DISARM_BUF(pnum));
3429 writeq(pbc, piobuf);
3430 qib_flush_wc();
3431 qib_pio_copy(piobuf + 2, hdr, 7);
3432 qib_pio_copy(piobuf + 9, data, dcnt);
3433 if (dd->flags & QIB_USE_SPCL_TRIG) {
3434 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
3435
3436 qib_flush_wc();
3437 __raw_writel(0xaebecede, piobuf + spcl_off);
3438 }
3439 qib_flush_wc();
3440 qib_sendbuf_done(dd, pnum);
3441 }
3442
3443 /*
3444 * _start packet gets sent twice at start, _done gets sent twice at end
3445 */
3446 static void autoneg_7220_send(struct qib_pportdata *ppd, int which)
3447 {
3448 struct qib_devdata *dd = ppd->dd;
3449 static u32 swapped;
3450 u32 dw, i, hcnt, dcnt, *data;
3451 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
3452 static u32 madpayload_start[0x40] = {
3453 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3454 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3455 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
3456 };
3457 static u32 madpayload_done[0x40] = {
3458 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3459 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3460 0x40000001, 0x1388, 0x15e, /* rest 0's */
3461 };
3462
3463 dcnt = ARRAY_SIZE(madpayload_start);
3464 hcnt = ARRAY_SIZE(hdr);
3465 if (!swapped) {
3466 /* for maintainability, do it at runtime */
3467 for (i = 0; i < hcnt; i++) {
3468 dw = (__force u32) cpu_to_be32(hdr[i]);
3469 hdr[i] = dw;
3470 }
3471 for (i = 0; i < dcnt; i++) {
3472 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
3473 madpayload_start[i] = dw;
3474 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
3475 madpayload_done[i] = dw;
3476 }
3477 swapped = 1;
3478 }
3479
3480 data = which ? madpayload_done : madpayload_start;
3481
3482 autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3483 qib_read_kreg64(dd, kr_scratch);
3484 udelay(2);
3485 autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3486 qib_read_kreg64(dd, kr_scratch);
3487 udelay(2);
3488 }
3489
3490 /*
3491 * Do the absolute minimum to cause an IB speed change, and make it
3492 * ready, but don't actually trigger the change. The caller will
3493 * do that when ready (if link is in Polling training state, it will
3494 * happen immediately, otherwise when link next goes down)
3495 *
3496 * This routine should only be used as part of the DDR autonegotation
3497 * code for devices that are not compliant with IB 1.2 (or code that
3498 * fixes things up for same).
3499 *
3500 * When link has gone down, and autoneg enabled, or autoneg has
3501 * failed and we give up until next time we set both speeds, and
3502 * then we want IBTA enabled as well as "use max enabled speed.
3503 */
3504 static void set_7220_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
3505 {
3506 ppd->cpspec->ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
3507 IBA7220_IBC_IBTA_1_2_MASK);
3508
3509 if (speed == (QIB_IB_SDR | QIB_IB_DDR))
3510 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
3511 IBA7220_IBC_IBTA_1_2_MASK;
3512 else
3513 ppd->cpspec->ibcddrctrl |= speed == QIB_IB_DDR ?
3514 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
3515
3516 qib_write_kreg(ppd->dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
3517 qib_write_kreg(ppd->dd, kr_scratch, 0);
3518 }
3519
3520 /*
3521 * This routine is only used when we are not talking to another
3522 * IB 1.2-compliant device that we think can do DDR.
3523 * (This includes all existing switch chips as of Oct 2007.)
3524 * 1.2-compliant devices go directly to DDR prior to reaching INIT
3525 */
3526 static void try_7220_autoneg(struct qib_pportdata *ppd)
3527 {
3528 unsigned long flags;
3529
3530 /*
3531 * Required for older non-IB1.2 DDR switches. Newer
3532 * non-IB-compliant switches don't need it, but so far,
3533 * aren't bothered by it either. "Magic constant"
3534 */
3535 qib_write_kreg(ppd->dd, kr_ncmodectrl, 0x3b9dc07);
3536
3537 spin_lock_irqsave(&ppd->lflags_lock, flags);
3538 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
3539 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3540 autoneg_7220_send(ppd, 0);
3541 set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3542
3543 toggle_7220_rclkrls(ppd->dd);
3544 /* 2 msec is minimum length of a poll cycle */
3545 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
3546 msecs_to_jiffies(2));
3547 }
3548
3549 /*
3550 * Handle the empirically determined mechanism for auto-negotiation
3551 * of DDR speed with switches.
3552 */
3553 static void autoneg_7220_work(struct work_struct *work)
3554 {
3555 struct qib_pportdata *ppd;
3556 struct qib_devdata *dd;
3557 u64 startms;
3558 u32 i;
3559 unsigned long flags;
3560
3561 ppd = &container_of(work, struct qib_chippport_specific,
3562 autoneg_work.work)->pportdata;
3563 dd = ppd->dd;
3564
3565 startms = jiffies_to_msecs(jiffies);
3566
3567 /*
3568 * Busy wait for this first part, it should be at most a
3569 * few hundred usec, since we scheduled ourselves for 2msec.
3570 */
3571 for (i = 0; i < 25; i++) {
3572 if (SYM_FIELD(ppd->lastibcstat, IBCStatus, LinkTrainingState)
3573 == IB_7220_LT_STATE_POLLQUIET) {
3574 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
3575 break;
3576 }
3577 udelay(100);
3578 }
3579
3580 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3581 goto done; /* we got there early or told to stop */
3582
3583 /* we expect this to timeout */
3584 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3585 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3586 msecs_to_jiffies(90)))
3587 goto done;
3588
3589 toggle_7220_rclkrls(dd);
3590
3591 /* we expect this to timeout */
3592 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3593 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3594 msecs_to_jiffies(1700)))
3595 goto done;
3596
3597 set_7220_ibspeed_fast(ppd, QIB_IB_SDR);
3598 toggle_7220_rclkrls(dd);
3599
3600 /*
3601 * Wait up to 250 msec for link to train and get to INIT at DDR;
3602 * this should terminate early.
3603 */
3604 wait_event_timeout(ppd->cpspec->autoneg_wait,
3605 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3606 msecs_to_jiffies(250));
3607 done:
3608 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
3609 spin_lock_irqsave(&ppd->lflags_lock, flags);
3610 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
3611 if (dd->cspec->autoneg_tries == AUTONEG_TRIES) {
3612 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
3613 dd->cspec->autoneg_tries = 0;
3614 }
3615 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3616 set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3617 }
3618 }
3619
3620 static u32 qib_7220_iblink_state(u64 ibcs)
3621 {
3622 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
3623
3624 switch (state) {
3625 case IB_7220_L_STATE_INIT:
3626 state = IB_PORT_INIT;
3627 break;
3628 case IB_7220_L_STATE_ARM:
3629 state = IB_PORT_ARMED;
3630 break;
3631 case IB_7220_L_STATE_ACTIVE:
3632 /* fall through */
3633 case IB_7220_L_STATE_ACT_DEFER:
3634 state = IB_PORT_ACTIVE;
3635 break;
3636 default: /* fall through */
3637 case IB_7220_L_STATE_DOWN:
3638 state = IB_PORT_DOWN;
3639 break;
3640 }
3641 return state;
3642 }
3643
3644 /* returns the IBTA port state, rather than the IBC link training state */
3645 static u8 qib_7220_phys_portstate(u64 ibcs)
3646 {
3647 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3648 return qib_7220_physportstate[state];
3649 }
3650
3651 static int qib_7220_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3652 {
3653 int ret = 0, symadj = 0;
3654 struct qib_devdata *dd = ppd->dd;
3655 unsigned long flags;
3656
3657 spin_lock_irqsave(&ppd->lflags_lock, flags);
3658 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3659 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3660
3661 if (!ibup) {
3662 /*
3663 * When the link goes down we don't want AEQ running, so it
3664 * won't interfere with IBC training, etc., and we need
3665 * to go back to the static SerDes preset values.
3666 */
3667 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3668 QIBL_IB_AUTONEG_INPROG)))
3669 set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3670 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3671 qib_sd7220_presets(dd);
3672 qib_cancel_sends(ppd); /* initial disarm, etc. */
3673 spin_lock_irqsave(&ppd->sdma_lock, flags);
3674 if (__qib_sdma_running(ppd))
3675 __qib_sdma_process_event(ppd,
3676 qib_sdma_event_e70_go_idle);
3677 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3678 }
3679 /* this might better in qib_sd7220_presets() */
3680 set_7220_relock_poll(dd, ibup);
3681 } else {
3682 if (qib_compat_ddr_negotiate &&
3683 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3684 QIBL_IB_AUTONEG_INPROG)) &&
3685 ppd->link_speed_active == QIB_IB_SDR &&
3686 (ppd->link_speed_enabled & (QIB_IB_DDR | QIB_IB_SDR)) ==
3687 (QIB_IB_DDR | QIB_IB_SDR) &&
3688 dd->cspec->autoneg_tries < AUTONEG_TRIES) {
3689 /* we are SDR, and DDR auto-negotiation enabled */
3690 ++dd->cspec->autoneg_tries;
3691 if (!ppd->cpspec->ibdeltainprog) {
3692 ppd->cpspec->ibdeltainprog = 1;
3693 ppd->cpspec->ibsymsnap = read_7220_creg32(dd,
3694 cr_ibsymbolerr);
3695 ppd->cpspec->iblnkerrsnap = read_7220_creg32(dd,
3696 cr_iblinkerrrecov);
3697 }
3698 try_7220_autoneg(ppd);
3699 ret = 1; /* no other IB status change processing */
3700 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3701 ppd->link_speed_active == QIB_IB_SDR) {
3702 autoneg_7220_send(ppd, 1);
3703 set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3704 udelay(2);
3705 toggle_7220_rclkrls(dd);
3706 ret = 1; /* no other IB status change processing */
3707 } else {
3708 if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3709 (ppd->link_speed_active & QIB_IB_DDR)) {
3710 spin_lock_irqsave(&ppd->lflags_lock, flags);
3711 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
3712 QIBL_IB_AUTONEG_FAILED);
3713 spin_unlock_irqrestore(&ppd->lflags_lock,
3714 flags);
3715 dd->cspec->autoneg_tries = 0;
3716 /* re-enable SDR, for next link down */
3717 set_7220_ibspeed_fast(ppd,
3718 ppd->link_speed_enabled);
3719 wake_up(&ppd->cpspec->autoneg_wait);
3720 symadj = 1;
3721 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
3722 /*
3723 * Clear autoneg failure flag, and do setup
3724 * so we'll try next time link goes down and
3725 * back to INIT (possibly connected to a
3726 * different device).
3727 */
3728 spin_lock_irqsave(&ppd->lflags_lock, flags);
3729 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3730 spin_unlock_irqrestore(&ppd->lflags_lock,
3731 flags);
3732 ppd->cpspec->ibcddrctrl |=
3733 IBA7220_IBC_IBTA_1_2_MASK;
3734 qib_write_kreg(dd, kr_ncmodectrl, 0);
3735 symadj = 1;
3736 }
3737 }
3738
3739 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3740 symadj = 1;
3741
3742 if (!ret) {
3743 ppd->delay_mult = rate_to_delay
3744 [(ibcs >> IBA7220_LINKSPEED_SHIFT) & 1]
3745 [(ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1];
3746
3747 set_7220_relock_poll(dd, ibup);
3748 spin_lock_irqsave(&ppd->sdma_lock, flags);
3749 /*
3750 * Unlike 7322, the 7220 needs this, due to lack of
3751 * interrupt in some cases when we have sdma active
3752 * when the link goes down.
3753 */
3754 if (ppd->sdma_state.current_state !=
3755 qib_sdma_state_s20_idle)
3756 __qib_sdma_process_event(ppd,
3757 qib_sdma_event_e00_go_hw_down);
3758 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3759 }
3760 }
3761
3762 if (symadj) {
3763 if (ppd->cpspec->ibdeltainprog) {
3764 ppd->cpspec->ibdeltainprog = 0;
3765 ppd->cpspec->ibsymdelta += read_7220_creg32(ppd->dd,
3766 cr_ibsymbolerr) - ppd->cpspec->ibsymsnap;
3767 ppd->cpspec->iblnkerrdelta += read_7220_creg32(ppd->dd,
3768 cr_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
3769 }
3770 } else if (!ibup && qib_compat_ddr_negotiate &&
3771 !ppd->cpspec->ibdeltainprog &&
3772 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3773 ppd->cpspec->ibdeltainprog = 1;
3774 ppd->cpspec->ibsymsnap = read_7220_creg32(ppd->dd,
3775 cr_ibsymbolerr);
3776 ppd->cpspec->iblnkerrsnap = read_7220_creg32(ppd->dd,
3777 cr_iblinkerrrecov);
3778 }
3779
3780 if (!ret)
3781 qib_setup_7220_setextled(ppd, ibup);
3782 return ret;
3783 }
3784
3785 /*
3786 * Does read/modify/write to appropriate registers to
3787 * set output and direction bits selected by mask.
3788 * these are in their canonical postions (e.g. lsb of
3789 * dir will end up in D48 of extctrl on existing chips).
3790 * returns contents of GP Inputs.
3791 */
3792 static int gpio_7220_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3793 {
3794 u64 read_val, new_out;
3795 unsigned long flags;
3796
3797 if (mask) {
3798 /* some bits being written, lock access to GPIO */
3799 dir &= mask;
3800 out &= mask;
3801 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3802 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3803 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3804 new_out = (dd->cspec->gpio_out & ~mask) | out;
3805
3806 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3807 qib_write_kreg(dd, kr_gpio_out, new_out);
3808 dd->cspec->gpio_out = new_out;
3809 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3810 }
3811 /*
3812 * It is unlikely that a read at this time would get valid
3813 * data on a pin whose direction line was set in the same
3814 * call to this function. We include the read here because
3815 * that allows us to potentially combine a change on one pin with
3816 * a read on another, and because the old code did something like
3817 * this.
3818 */
3819 read_val = qib_read_kreg64(dd, kr_extstatus);
3820 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3821 }
3822
3823 /*
3824 * Read fundamental info we need to use the chip. These are
3825 * the registers that describe chip capabilities, and are
3826 * saved in shadow registers.
3827 */
3828 static void get_7220_chip_params(struct qib_devdata *dd)
3829 {
3830 u64 val;
3831 u32 piobufs;
3832 int mtu;
3833
3834 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3835
3836 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3837 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3838 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3839 dd->palign = qib_read_kreg32(dd, kr_palign);
3840 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3841 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3842
3843 val = qib_read_kreg64(dd, kr_sendpiosize);
3844 dd->piosize2k = val & ~0U;
3845 dd->piosize4k = val >> 32;
3846
3847 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3848 if (mtu == -1)
3849 mtu = QIB_DEFAULT_MTU;
3850 dd->pport->ibmtu = (u32)mtu;
3851
3852 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3853 dd->piobcnt2k = val & ~0U;
3854 dd->piobcnt4k = val >> 32;
3855 /* these may be adjusted in init_chip_wc_pat() */
3856 dd->pio2kbase = (u32 __iomem *)
3857 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
3858 if (dd->piobcnt4k) {
3859 dd->pio4kbase = (u32 __iomem *)
3860 ((char __iomem *) dd->kregbase +
3861 (dd->piobufbase >> 32));
3862 /*
3863 * 4K buffers take 2 pages; we use roundup just to be
3864 * paranoid; we calculate it once here, rather than on
3865 * ever buf allocate
3866 */
3867 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3868 }
3869
3870 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3871
3872 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3873 (sizeof(u64) * BITS_PER_BYTE / 2);
3874 }
3875
3876 /*
3877 * The chip base addresses in cspec and cpspec have to be set
3878 * after possible init_chip_wc_pat(), rather than in
3879 * qib_get_7220_chip_params(), so split out as separate function
3880 */
3881 static void set_7220_baseaddrs(struct qib_devdata *dd)
3882 {
3883 u32 cregbase;
3884 /* init after possible re-map in init_chip_wc_pat() */
3885 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3886 dd->cspec->cregbase = (u64 __iomem *)
3887 ((char __iomem *) dd->kregbase + cregbase);
3888
3889 dd->egrtidbase = (u64 __iomem *)
3890 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3891 }
3892
3893
3894 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl, SendIntBufAvail) | \
3895 SYM_MASK(SendCtrl, SPioEnable) | \
3896 SYM_MASK(SendCtrl, SSpecialTriggerEn) | \
3897 SYM_MASK(SendCtrl, SendBufAvailUpd) | \
3898 SYM_MASK(SendCtrl, AvailUpdThld) | \
3899 SYM_MASK(SendCtrl, SDmaEnable) | \
3900 SYM_MASK(SendCtrl, SDmaIntEnable) | \
3901 SYM_MASK(SendCtrl, SDmaHalt) | \
3902 SYM_MASK(SendCtrl, SDmaSingleDescriptor))
3903
3904 static int sendctrl_hook(struct qib_devdata *dd,
3905 const struct diag_observer *op,
3906 u32 offs, u64 *data, u64 mask, int only_32)
3907 {
3908 unsigned long flags;
3909 unsigned idx = offs / sizeof(u64);
3910 u64 local_data, all_bits;
3911
3912 if (idx != kr_sendctrl) {
3913 qib_dev_err(dd, "SendCtrl Hook called with offs %X, %s-bit\n",
3914 offs, only_32 ? "32" : "64");
3915 return 0;
3916 }
3917
3918 all_bits = ~0ULL;
3919 if (only_32)
3920 all_bits >>= 32;
3921 spin_lock_irqsave(&dd->sendctrl_lock, flags);
3922 if ((mask & all_bits) != all_bits) {
3923 /*
3924 * At least some mask bits are zero, so we need
3925 * to read. The judgement call is whether from
3926 * reg or shadow. First-cut: read reg, and complain
3927 * if any bits which should be shadowed are different
3928 * from their shadowed value.
3929 */
3930 if (only_32)
3931 local_data = (u64)qib_read_kreg32(dd, idx);
3932 else
3933 local_data = qib_read_kreg64(dd, idx);
3934 qib_dev_err(dd, "Sendctrl -> %X, Shad -> %X\n",
3935 (u32)local_data, (u32)dd->sendctrl);
3936 if ((local_data & SENDCTRL_SHADOWED) !=
3937 (dd->sendctrl & SENDCTRL_SHADOWED))
3938 qib_dev_err(dd, "Sendctrl read: %X shadow is %X\n",
3939 (u32)local_data, (u32) dd->sendctrl);
3940 *data = (local_data & ~mask) | (*data & mask);
3941 }
3942 if (mask) {
3943 /*
3944 * At least some mask bits are one, so we need
3945 * to write, but only shadow some bits.
3946 */
3947 u64 sval, tval; /* Shadowed, transient */
3948
3949 /*
3950 * New shadow val is bits we don't want to touch,
3951 * ORed with bits we do, that are intended for shadow.
3952 */
3953 sval = (dd->sendctrl & ~mask);
3954 sval |= *data & SENDCTRL_SHADOWED & mask;
3955 dd->sendctrl = sval;
3956 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
3957 qib_dev_err(dd, "Sendctrl <- %X, Shad <- %X\n",
3958 (u32)tval, (u32)sval);
3959 qib_write_kreg(dd, kr_sendctrl, tval);
3960 qib_write_kreg(dd, kr_scratch, 0Ull);
3961 }
3962 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
3963
3964 return only_32 ? 4 : 8;
3965 }
3966
3967 static const struct diag_observer sendctrl_observer = {
3968 sendctrl_hook, kr_sendctrl * sizeof(u64),
3969 kr_sendctrl * sizeof(u64)
3970 };
3971
3972 /*
3973 * write the final few registers that depend on some of the
3974 * init setup. Done late in init, just before bringing up
3975 * the serdes.
3976 */
3977 static int qib_late_7220_initreg(struct qib_devdata *dd)
3978 {
3979 int ret = 0;
3980 u64 val;
3981
3982 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3983 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3984 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3985 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3986 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3987 if (val != dd->pioavailregs_phys) {
3988 qib_dev_err(dd,
3989 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3990 (unsigned long) dd->pioavailregs_phys,
3991 (unsigned long long) val);
3992 ret = -EINVAL;
3993 }
3994 qib_register_observer(dd, &sendctrl_observer);
3995 return ret;
3996 }
3997
3998 static int qib_init_7220_variables(struct qib_devdata *dd)
3999 {
4000 struct qib_chippport_specific *cpspec;
4001 struct qib_pportdata *ppd;
4002 int ret = 0;
4003 u32 sbufs, updthresh;
4004
4005 cpspec = (struct qib_chippport_specific *)(dd + 1);
4006 ppd = &cpspec->pportdata;
4007 dd->pport = ppd;
4008 dd->num_pports = 1;
4009
4010 dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports);
4011 ppd->cpspec = cpspec;
4012
4013 spin_lock_init(&dd->cspec->sdepb_lock);
4014 spin_lock_init(&dd->cspec->rcvmod_lock);
4015 spin_lock_init(&dd->cspec->gpio_lock);
4016
4017 /* we haven't yet set QIB_PRESENT, so use read directly */
4018 dd->revision = readq(&dd->kregbase[kr_revision]);
4019
4020 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
4021 qib_dev_err(dd,
4022 "Revision register read failure, giving up initialization\n");
4023 ret = -ENODEV;
4024 goto bail;
4025 }
4026 dd->flags |= QIB_PRESENT; /* now register routines work */
4027
4028 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4029 ChipRevMajor);
4030 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4031 ChipRevMinor);
4032
4033 get_7220_chip_params(dd);
4034 qib_7220_boardname(dd);
4035
4036 /*
4037 * GPIO bits for TWSI data and clock,
4038 * used for serial EEPROM.
4039 */
4040 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
4041 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
4042 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
4043
4044 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
4045 QIB_NODMA_RTAIL | QIB_HAS_THRESH_UPDATE;
4046 dd->flags |= qib_special_trigger ?
4047 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
4048
4049 /*
4050 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
4051 * 2 is Some Misc, 3 is reserved for future.
4052 */
4053 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
4054
4055 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
4056
4057 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
4058
4059 init_waitqueue_head(&cpspec->autoneg_wait);
4060 INIT_DELAYED_WORK(&cpspec->autoneg_work, autoneg_7220_work);
4061
4062 ret = qib_init_pportdata(ppd, dd, 0, 1);
4063 if (ret)
4064 goto bail;
4065 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
4066 ppd->link_speed_supported = QIB_IB_SDR | QIB_IB_DDR;
4067
4068 ppd->link_width_enabled = ppd->link_width_supported;
4069 ppd->link_speed_enabled = ppd->link_speed_supported;
4070 /*
4071 * Set the initial values to reasonable default, will be set
4072 * for real when link is up.
4073 */
4074 ppd->link_width_active = IB_WIDTH_4X;
4075 ppd->link_speed_active = QIB_IB_SDR;
4076 ppd->delay_mult = rate_to_delay[0][1];
4077 ppd->vls_supported = IB_VL_VL0;
4078 ppd->vls_operational = ppd->vls_supported;
4079
4080 if (!qib_mini_init)
4081 qib_write_kreg(dd, kr_rcvbthqp, QIB_KD_QP);
4082
4083 init_timer(&ppd->cpspec->chase_timer);
4084 ppd->cpspec->chase_timer.function = reenable_7220_chase;
4085 ppd->cpspec->chase_timer.data = (unsigned long)ppd;
4086
4087 qib_num_cfg_vls = 1; /* if any 7220's, only one VL */
4088
4089 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
4090 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
4091 dd->rhf_offset =
4092 dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
4093
4094 /* we always allocate at least 2048 bytes for eager buffers */
4095 ret = ib_mtu_enum_to_int(qib_ibmtu);
4096 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
4097 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
4098 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
4099
4100 qib_7220_tidtemplate(dd);
4101
4102 /*
4103 * We can request a receive interrupt for 1 or
4104 * more packets from current offset. For now, we set this
4105 * up for a single packet.
4106 */
4107 dd->rhdrhead_intr_off = 1ULL << 32;
4108
4109 /* setup the stats timer; the add_timer is done at end of init */
4110 init_timer(&dd->stats_timer);
4111 dd->stats_timer.function = qib_get_7220_faststats;
4112 dd->stats_timer.data = (unsigned long) dd;
4113 dd->stats_timer.expires = jiffies + ACTIVITY_TIMER * HZ;
4114
4115 /*
4116 * Control[4] has been added to change the arbitration within
4117 * the SDMA engine between favoring data fetches over descriptor
4118 * fetches. qib_sdma_fetch_arb==0 gives data fetches priority.
4119 */
4120 if (qib_sdma_fetch_arb)
4121 dd->control |= 1 << 4;
4122
4123 dd->ureg_align = 0x10000; /* 64KB alignment */
4124
4125 dd->piosize2kmax_dwords = (dd->piosize2k >> 2)-1;
4126 qib_7220_config_ctxts(dd);
4127 qib_set_ctxtcnt(dd); /* needed for PAT setup */
4128
4129 if (qib_wc_pat) {
4130 ret = init_chip_wc_pat(dd, 0);
4131 if (ret)
4132 goto bail;
4133 }
4134 set_7220_baseaddrs(dd); /* set chip access pointers now */
4135
4136 ret = 0;
4137 if (qib_mini_init)
4138 goto bail;
4139
4140 ret = qib_create_ctxts(dd);
4141 init_7220_cntrnames(dd);
4142
4143 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
4144 * reserve the update threshold amount for other kernel use, such
4145 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
4146 * unless we aren't enabling SDMA, in which case we want to use
4147 * all the 4k bufs for the kernel.
4148 * if this was less than the update threshold, we could wait
4149 * a long time for an update. Coded this way because we
4150 * sometimes change the update threshold for various reasons,
4151 * and we want this to remain robust.
4152 */
4153 updthresh = 8U; /* update threshold */
4154 if (dd->flags & QIB_HAS_SEND_DMA) {
4155 dd->cspec->sdmabufcnt = dd->piobcnt4k;
4156 sbufs = updthresh > 3 ? updthresh : 3;
4157 } else {
4158 dd->cspec->sdmabufcnt = 0;
4159 sbufs = dd->piobcnt4k;
4160 }
4161
4162 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
4163 dd->cspec->sdmabufcnt;
4164 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
4165 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
4166 dd->last_pio = dd->cspec->lastbuf_for_pio;
4167 dd->pbufsctxt = dd->lastctxt_piobuf /
4168 (dd->cfgctxts - dd->first_user_ctxt);
4169
4170 /*
4171 * if we are at 16 user contexts, we will have one 7 sbufs
4172 * per context, so drop the update threshold to match. We
4173 * want to update before we actually run out, at low pbufs/ctxt
4174 * so give ourselves some margin
4175 */
4176 if ((dd->pbufsctxt - 2) < updthresh)
4177 updthresh = dd->pbufsctxt - 2;
4178
4179 dd->cspec->updthresh_dflt = updthresh;
4180 dd->cspec->updthresh = updthresh;
4181
4182 /* before full enable, no interrupts, no locking needed */
4183 dd->sendctrl |= (updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
4184 << SYM_LSB(SendCtrl, AvailUpdThld);
4185
4186 dd->psxmitwait_supported = 1;
4187 dd->psxmitwait_check_rate = QIB_7220_PSXMITWAIT_CHECK_RATE;
4188 bail:
4189 return ret;
4190 }
4191
4192 static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
4193 u32 *pbufnum)
4194 {
4195 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
4196 struct qib_devdata *dd = ppd->dd;
4197 u32 __iomem *buf;
4198
4199 if (((pbc >> 32) & PBC_7220_VL15_SEND_CTRL) &&
4200 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
4201 buf = get_7220_link_buf(ppd, pbufnum);
4202 else {
4203 if ((plen + 1) > dd->piosize2kmax_dwords)
4204 first = dd->piobcnt2k;
4205 else
4206 first = 0;
4207 /* try 4k if all 2k busy, so same last for both sizes */
4208 last = dd->cspec->lastbuf_for_pio;
4209 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
4210 }
4211 return buf;
4212 }
4213
4214 /* these 2 "counters" are really control registers, and are always RW */
4215 static void qib_set_cntr_7220_sample(struct qib_pportdata *ppd, u32 intv,
4216 u32 start)
4217 {
4218 write_7220_creg(ppd->dd, cr_psinterval, intv);
4219 write_7220_creg(ppd->dd, cr_psstart, start);
4220 }
4221
4222 /*
4223 * NOTE: no real attempt is made to generalize the SDMA stuff.
4224 * At some point "soon" we will have a new more generalized
4225 * set of sdma interface, and then we'll clean this up.
4226 */
4227
4228 /* Must be called with sdma_lock held, or before init finished */
4229 static void qib_sdma_update_7220_tail(struct qib_pportdata *ppd, u16 tail)
4230 {
4231 /* Commit writes to memory and advance the tail on the chip */
4232 wmb();
4233 ppd->sdma_descq_tail = tail;
4234 qib_write_kreg(ppd->dd, kr_senddmatail, tail);
4235 }
4236
4237 static void qib_sdma_set_7220_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
4238 {
4239 }
4240
4241 static struct sdma_set_state_action sdma_7220_action_table[] = {
4242 [qib_sdma_state_s00_hw_down] = {
4243 .op_enable = 0,
4244 .op_intenable = 0,
4245 .op_halt = 0,
4246 .go_s99_running_tofalse = 1,
4247 },
4248 [qib_sdma_state_s10_hw_start_up_wait] = {
4249 .op_enable = 1,
4250 .op_intenable = 1,
4251 .op_halt = 1,
4252 },
4253 [qib_sdma_state_s20_idle] = {
4254 .op_enable = 1,
4255 .op_intenable = 1,
4256 .op_halt = 1,
4257 },
4258 [qib_sdma_state_s30_sw_clean_up_wait] = {
4259 .op_enable = 0,
4260 .op_intenable = 1,
4261 .op_halt = 0,
4262 },
4263 [qib_sdma_state_s40_hw_clean_up_wait] = {
4264 .op_enable = 1,
4265 .op_intenable = 1,
4266 .op_halt = 1,
4267 },
4268 [qib_sdma_state_s50_hw_halt_wait] = {
4269 .op_enable = 1,
4270 .op_intenable = 1,
4271 .op_halt = 1,
4272 },
4273 [qib_sdma_state_s99_running] = {
4274 .op_enable = 1,
4275 .op_intenable = 1,
4276 .op_halt = 0,
4277 .go_s99_running_totrue = 1,
4278 },
4279 };
4280
4281 static void qib_7220_sdma_init_early(struct qib_pportdata *ppd)
4282 {
4283 ppd->sdma_state.set_state_action = sdma_7220_action_table;
4284 }
4285
4286 static int init_sdma_7220_regs(struct qib_pportdata *ppd)
4287 {
4288 struct qib_devdata *dd = ppd->dd;
4289 unsigned i, n;
4290 u64 senddmabufmask[3] = { 0 };
4291
4292 /* Set SendDmaBase */
4293 qib_write_kreg(dd, kr_senddmabase, ppd->sdma_descq_phys);
4294 qib_sdma_7220_setlengen(ppd);
4295 qib_sdma_update_7220_tail(ppd, 0); /* Set SendDmaTail */
4296 /* Set SendDmaHeadAddr */
4297 qib_write_kreg(dd, kr_senddmaheadaddr, ppd->sdma_head_phys);
4298
4299 /*
4300 * Reserve all the former "kernel" piobufs, using high number range
4301 * so we get as many 4K buffers as possible
4302 */
4303 n = dd->piobcnt2k + dd->piobcnt4k;
4304 i = n - dd->cspec->sdmabufcnt;
4305
4306 for (; i < n; ++i) {
4307 unsigned word = i / 64;
4308 unsigned bit = i & 63;
4309
4310 BUG_ON(word >= 3);
4311 senddmabufmask[word] |= 1ULL << bit;
4312 }
4313 qib_write_kreg(dd, kr_senddmabufmask0, senddmabufmask[0]);
4314 qib_write_kreg(dd, kr_senddmabufmask1, senddmabufmask[1]);
4315 qib_write_kreg(dd, kr_senddmabufmask2, senddmabufmask[2]);
4316
4317 ppd->sdma_state.first_sendbuf = i;
4318 ppd->sdma_state.last_sendbuf = n;
4319
4320 return 0;
4321 }
4322
4323 /* sdma_lock must be held */
4324 static u16 qib_sdma_7220_gethead(struct qib_pportdata *ppd)
4325 {
4326 struct qib_devdata *dd = ppd->dd;
4327 int sane;
4328 int use_dmahead;
4329 u16 swhead;
4330 u16 swtail;
4331 u16 cnt;
4332 u16 hwhead;
4333
4334 use_dmahead = __qib_sdma_running(ppd) &&
4335 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
4336 retry:
4337 hwhead = use_dmahead ?
4338 (u16)le64_to_cpu(*ppd->sdma_head_dma) :
4339 (u16)qib_read_kreg32(dd, kr_senddmahead);
4340
4341 swhead = ppd->sdma_descq_head;
4342 swtail = ppd->sdma_descq_tail;
4343 cnt = ppd->sdma_descq_cnt;
4344
4345 if (swhead < swtail) {
4346 /* not wrapped */
4347 sane = (hwhead >= swhead) & (hwhead <= swtail);
4348 } else if (swhead > swtail) {
4349 /* wrapped around */
4350 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
4351 (hwhead <= swtail);
4352 } else {
4353 /* empty */
4354 sane = (hwhead == swhead);
4355 }
4356
4357 if (unlikely(!sane)) {
4358 if (use_dmahead) {
4359 /* try one more time, directly from the register */
4360 use_dmahead = 0;
4361 goto retry;
4362 }
4363 /* assume no progress */
4364 hwhead = swhead;
4365 }
4366
4367 return hwhead;
4368 }
4369
4370 static int qib_sdma_7220_busy(struct qib_pportdata *ppd)
4371 {
4372 u64 hwstatus = qib_read_kreg64(ppd->dd, kr_senddmastatus);
4373
4374 return (hwstatus & SYM_MASK(SendDmaStatus, ScoreBoardDrainInProg)) ||
4375 (hwstatus & SYM_MASK(SendDmaStatus, AbortInProg)) ||
4376 (hwstatus & SYM_MASK(SendDmaStatus, InternalSDmaEnable)) ||
4377 !(hwstatus & SYM_MASK(SendDmaStatus, ScbEmpty));
4378 }
4379
4380 /*
4381 * Compute the amount of delay before sending the next packet if the
4382 * port's send rate differs from the static rate set for the QP.
4383 * Since the delay affects this packet but the amount of the delay is
4384 * based on the length of the previous packet, use the last delay computed
4385 * and save the delay count for this packet to be used next time
4386 * we get here.
4387 */
4388 static u32 qib_7220_setpbc_control(struct qib_pportdata *ppd, u32 plen,
4389 u8 srate, u8 vl)
4390 {
4391 u8 snd_mult = ppd->delay_mult;
4392 u8 rcv_mult = ib_rate_to_delay[srate];
4393 u32 ret = ppd->cpspec->last_delay_mult;
4394
4395 ppd->cpspec->last_delay_mult = (rcv_mult > snd_mult) ?
4396 (plen * (rcv_mult - snd_mult) + 1) >> 1 : 0;
4397
4398 /* Indicate VL15, if necessary */
4399 if (vl == 15)
4400 ret |= PBC_7220_VL15_SEND_CTRL;
4401 return ret;
4402 }
4403
4404 static void qib_7220_initvl15_bufs(struct qib_devdata *dd)
4405 {
4406 }
4407
4408 static void qib_7220_init_ctxt(struct qib_ctxtdata *rcd)
4409 {
4410 if (!rcd->ctxt) {
4411 rcd->rcvegrcnt = IBA7220_KRCVEGRCNT;
4412 rcd->rcvegr_tid_base = 0;
4413 } else {
4414 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
4415 rcd->rcvegr_tid_base = IBA7220_KRCVEGRCNT +
4416 (rcd->ctxt - 1) * rcd->rcvegrcnt;
4417 }
4418 }
4419
4420 static void qib_7220_txchk_change(struct qib_devdata *dd, u32 start,
4421 u32 len, u32 which, struct qib_ctxtdata *rcd)
4422 {
4423 int i;
4424 unsigned long flags;
4425
4426 switch (which) {
4427 case TXCHK_CHG_TYPE_KERN:
4428 /* see if we need to raise avail update threshold */
4429 spin_lock_irqsave(&dd->uctxt_lock, flags);
4430 for (i = dd->first_user_ctxt;
4431 dd->cspec->updthresh != dd->cspec->updthresh_dflt
4432 && i < dd->cfgctxts; i++)
4433 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
4434 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
4435 < dd->cspec->updthresh_dflt)
4436 break;
4437 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
4438 if (i == dd->cfgctxts) {
4439 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4440 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
4441 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4442 dd->sendctrl |= (dd->cspec->updthresh &
4443 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
4444 SYM_LSB(SendCtrl, AvailUpdThld);
4445 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4446 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4447 }
4448 break;
4449 case TXCHK_CHG_TYPE_USER:
4450 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4451 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
4452 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
4453 dd->cspec->updthresh = (rcd->piocnt /
4454 rcd->subctxt_cnt) - 1;
4455 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4456 dd->sendctrl |= (dd->cspec->updthresh &
4457 SYM_RMASK(SendCtrl, AvailUpdThld))
4458 << SYM_LSB(SendCtrl, AvailUpdThld);
4459 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4460 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4461 } else
4462 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4463 break;
4464 }
4465 }
4466
4467 static void writescratch(struct qib_devdata *dd, u32 val)
4468 {
4469 qib_write_kreg(dd, kr_scratch, val);
4470 }
4471
4472 #define VALID_TS_RD_REG_MASK 0xBF
4473 /**
4474 * qib_7220_tempsense_read - read register of temp sensor via TWSI
4475 * @dd: the qlogic_ib device
4476 * @regnum: register to read from
4477 *
4478 * returns reg contents (0..255) or < 0 for error
4479 */
4480 static int qib_7220_tempsense_rd(struct qib_devdata *dd, int regnum)
4481 {
4482 int ret;
4483 u8 rdata;
4484
4485 if (regnum > 7) {
4486 ret = -EINVAL;
4487 goto bail;
4488 }
4489
4490 /* return a bogus value for (the one) register we do not have */
4491 if (!((1 << regnum) & VALID_TS_RD_REG_MASK)) {
4492 ret = 0;
4493 goto bail;
4494 }
4495
4496 ret = mutex_lock_interruptible(&dd->eep_lock);
4497 if (ret)
4498 goto bail;
4499
4500 ret = qib_twsi_blk_rd(dd, QIB_TWSI_TEMP_DEV, regnum, &rdata, 1);
4501 if (!ret)
4502 ret = rdata;
4503
4504 mutex_unlock(&dd->eep_lock);
4505
4506 /*
4507 * There are three possibilities here:
4508 * ret is actual value (0..255)
4509 * ret is -ENXIO or -EINVAL from twsi code or this file
4510 * ret is -EINTR from mutex_lock_interruptible.
4511 */
4512 bail:
4513 return ret;
4514 }
4515
4516 #ifdef CONFIG_INFINIBAND_QIB_DCA
4517 static int qib_7220_notify_dca(struct qib_devdata *dd, unsigned long event)
4518 {
4519 return 0;
4520 }
4521 #endif
4522
4523 /* Dummy function, as 7220 boards never disable EEPROM Write */
4524 static int qib_7220_eeprom_wen(struct qib_devdata *dd, int wen)
4525 {
4526 return 1;
4527 }
4528
4529 /**
4530 * qib_init_iba7220_funcs - set up the chip-specific function pointers
4531 * @dev: the pci_dev for qlogic_ib device
4532 * @ent: pci_device_id struct for this dev
4533 *
4534 * This is global, and is called directly at init to set up the
4535 * chip-specific function pointers for later use.
4536 */
4537 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *pdev,
4538 const struct pci_device_id *ent)
4539 {
4540 struct qib_devdata *dd;
4541 int ret;
4542 u32 boardid, minwidth;
4543
4544 dd = qib_alloc_devdata(pdev, sizeof(struct qib_chip_specific) +
4545 sizeof(struct qib_chippport_specific));
4546 if (IS_ERR(dd))
4547 goto bail;
4548
4549 dd->f_bringup_serdes = qib_7220_bringup_serdes;
4550 dd->f_cleanup = qib_setup_7220_cleanup;
4551 dd->f_clear_tids = qib_7220_clear_tids;
4552 dd->f_free_irq = qib_7220_free_irq;
4553 dd->f_get_base_info = qib_7220_get_base_info;
4554 dd->f_get_msgheader = qib_7220_get_msgheader;
4555 dd->f_getsendbuf = qib_7220_getsendbuf;
4556 dd->f_gpio_mod = gpio_7220_mod;
4557 dd->f_eeprom_wen = qib_7220_eeprom_wen;
4558 dd->f_hdrqempty = qib_7220_hdrqempty;
4559 dd->f_ib_updown = qib_7220_ib_updown;
4560 dd->f_init_ctxt = qib_7220_init_ctxt;
4561 dd->f_initvl15_bufs = qib_7220_initvl15_bufs;
4562 dd->f_intr_fallback = qib_7220_intr_fallback;
4563 dd->f_late_initreg = qib_late_7220_initreg;
4564 dd->f_setpbc_control = qib_7220_setpbc_control;
4565 dd->f_portcntr = qib_portcntr_7220;
4566 dd->f_put_tid = qib_7220_put_tid;
4567 dd->f_quiet_serdes = qib_7220_quiet_serdes;
4568 dd->f_rcvctrl = rcvctrl_7220_mod;
4569 dd->f_read_cntrs = qib_read_7220cntrs;
4570 dd->f_read_portcntrs = qib_read_7220portcntrs;
4571 dd->f_reset = qib_setup_7220_reset;
4572 dd->f_init_sdma_regs = init_sdma_7220_regs;
4573 dd->f_sdma_busy = qib_sdma_7220_busy;
4574 dd->f_sdma_gethead = qib_sdma_7220_gethead;
4575 dd->f_sdma_sendctrl = qib_7220_sdma_sendctrl;
4576 dd->f_sdma_set_desc_cnt = qib_sdma_set_7220_desc_cnt;
4577 dd->f_sdma_update_tail = qib_sdma_update_7220_tail;
4578 dd->f_sdma_hw_clean_up = qib_7220_sdma_hw_clean_up;
4579 dd->f_sdma_hw_start_up = qib_7220_sdma_hw_start_up;
4580 dd->f_sdma_init_early = qib_7220_sdma_init_early;
4581 dd->f_sendctrl = sendctrl_7220_mod;
4582 dd->f_set_armlaunch = qib_set_7220_armlaunch;
4583 dd->f_set_cntr_sample = qib_set_cntr_7220_sample;
4584 dd->f_iblink_state = qib_7220_iblink_state;
4585 dd->f_ibphys_portstate = qib_7220_phys_portstate;
4586 dd->f_get_ib_cfg = qib_7220_get_ib_cfg;
4587 dd->f_set_ib_cfg = qib_7220_set_ib_cfg;
4588 dd->f_set_ib_loopback = qib_7220_set_loopback;
4589 dd->f_set_intr_state = qib_7220_set_intr_state;
4590 dd->f_setextled = qib_setup_7220_setextled;
4591 dd->f_txchk_change = qib_7220_txchk_change;
4592 dd->f_update_usrhead = qib_update_7220_usrhead;
4593 dd->f_wantpiobuf_intr = qib_wantpiobuf_7220_intr;
4594 dd->f_xgxs_reset = qib_7220_xgxs_reset;
4595 dd->f_writescratch = writescratch;
4596 dd->f_tempsense_rd = qib_7220_tempsense_rd;
4597 #ifdef CONFIG_INFINIBAND_QIB_DCA
4598 dd->f_notify_dca = qib_7220_notify_dca;
4599 #endif
4600 /*
4601 * Do remaining pcie setup and save pcie values in dd.
4602 * Any error printing is already done by the init code.
4603 * On return, we have the chip mapped, but chip registers
4604 * are not set up until start of qib_init_7220_variables.
4605 */
4606 ret = qib_pcie_ddinit(dd, pdev, ent);
4607 if (ret < 0)
4608 goto bail_free;
4609
4610 /* initialize chip-specific variables */
4611 ret = qib_init_7220_variables(dd);
4612 if (ret)
4613 goto bail_cleanup;
4614
4615 if (qib_mini_init)
4616 goto bail;
4617
4618 boardid = SYM_FIELD(dd->revision, Revision,
4619 BoardID);
4620 switch (boardid) {
4621 case 0:
4622 case 2:
4623 case 10:
4624 case 12:
4625 minwidth = 16; /* x16 capable boards */
4626 break;
4627 default:
4628 minwidth = 8; /* x8 capable boards */
4629 break;
4630 }
4631 if (qib_pcie_params(dd, minwidth, NULL, NULL))
4632 qib_dev_err(dd,
4633 "Failed to setup PCIe or interrupts; continuing anyway\n");
4634
4635 /* save IRQ for possible later use */
4636 dd->cspec->irq = pdev->irq;
4637
4638 if (qib_read_kreg64(dd, kr_hwerrstatus) &
4639 QLOGIC_IB_HWE_SERDESPLLFAILED)
4640 qib_write_kreg(dd, kr_hwerrclear,
4641 QLOGIC_IB_HWE_SERDESPLLFAILED);
4642
4643 /* setup interrupt handler (interrupt type handled above) */
4644 qib_setup_7220_interrupt(dd);
4645 qib_7220_init_hwerrors(dd);
4646
4647 /* clear diagctrl register, in case diags were running and crashed */
4648 qib_write_kreg(dd, kr_hwdiagctrl, 0);
4649
4650 goto bail;
4651
4652 bail_cleanup:
4653 qib_pcie_ddcleanup(dd);
4654 bail_free:
4655 qib_free_devdata(dd);
4656 dd = ERR_PTR(ret);
4657 bail:
4658 return dd;
4659 }
Linux with added FPC-III support