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m68k/defconfig: Enable automounting of devtmpfs at /dev
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci.c
blob03427755b9029b297393d1d43851b4f678f2bbae
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/mmc/sdhci-pci-data.h>
29
30 #include "sdhci.h"
31 #include "sdhci-pci.h"
32 #include "sdhci-pci-o2micro.h"
33
34 /*****************************************************************************\
35 * *
36 * Hardware specific quirk handling *
37 * *
38 \*****************************************************************************/
39
40 static int ricoh_probe(struct sdhci_pci_chip *chip)
41 {
42 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
43 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
44 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
45 return 0;
46 }
47
48 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
49 {
50 slot->host->caps =
51 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
52 & SDHCI_TIMEOUT_CLK_MASK) |
53
54 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
55 & SDHCI_CLOCK_BASE_MASK) |
56
57 SDHCI_TIMEOUT_CLK_UNIT |
58 SDHCI_CAN_VDD_330 |
59 SDHCI_CAN_DO_HISPD |
60 SDHCI_CAN_DO_SDMA;
61 return 0;
62 }
63
64 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
65 {
66 /* Apply a delay to allow controller to settle */
67 /* Otherwise it becomes confused if card state changed
68 during suspend */
69 msleep(500);
70 return 0;
71 }
72
73 static const struct sdhci_pci_fixes sdhci_ricoh = {
74 .probe = ricoh_probe,
75 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
76 SDHCI_QUIRK_FORCE_DMA |
77 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
78 };
79
80 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
81 .probe_slot = ricoh_mmc_probe_slot,
82 .resume = ricoh_mmc_resume,
83 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
84 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
85 SDHCI_QUIRK_NO_CARD_NO_RESET |
86 SDHCI_QUIRK_MISSING_CAPS
87 };
88
89 static const struct sdhci_pci_fixes sdhci_ene_712 = {
90 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_BROKEN_DMA,
92 };
93
94 static const struct sdhci_pci_fixes sdhci_ene_714 = {
95 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
96 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
97 SDHCI_QUIRK_BROKEN_DMA,
98 };
99
100 static const struct sdhci_pci_fixes sdhci_cafe = {
101 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
102 SDHCI_QUIRK_NO_BUSY_IRQ |
103 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
104 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
105 };
106
107 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
108 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
109 };
110
111 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
112 {
113 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
114 return 0;
115 }
116
117 /*
118 * ADMA operation is disabled for Moorestown platform due to
119 * hardware bugs.
120 */
121 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
122 {
123 /*
124 * slots number is fixed here for MRST as SDIO3/5 are never used and
125 * have hardware bugs.
126 */
127 chip->num_slots = 1;
128 return 0;
129 }
130
131 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
132 {
133 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
134 return 0;
135 }
136
137 #ifdef CONFIG_PM
138
139 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
140 {
141 struct sdhci_pci_slot *slot = dev_id;
142 struct sdhci_host *host = slot->host;
143
144 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
145 return IRQ_HANDLED;
146 }
147
148 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
149 {
150 int err, irq, gpio = slot->cd_gpio;
151
152 slot->cd_gpio = -EINVAL;
153 slot->cd_irq = -EINVAL;
154
155 if (!gpio_is_valid(gpio))
156 return;
157
158 err = gpio_request(gpio, "sd_cd");
159 if (err < 0)
160 goto out;
161
162 err = gpio_direction_input(gpio);
163 if (err < 0)
164 goto out_free;
165
166 irq = gpio_to_irq(gpio);
167 if (irq < 0)
168 goto out_free;
169
170 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
171 IRQF_TRIGGER_FALLING, "sd_cd", slot);
172 if (err)
173 goto out_free;
174
175 slot->cd_gpio = gpio;
176 slot->cd_irq = irq;
177
178 return;
179
180 out_free:
181 gpio_free(gpio);
182 out:
183 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
184 }
185
186 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
187 {
188 if (slot->cd_irq >= 0)
189 free_irq(slot->cd_irq, slot);
190 if (gpio_is_valid(slot->cd_gpio))
191 gpio_free(slot->cd_gpio);
192 }
193
194 #else
195
196 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
197 {
198 }
199
200 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
201 {
202 }
203
204 #endif
205
206 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
207 {
208 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
209 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
210 MMC_CAP2_HC_ERASE_SZ;
211 return 0;
212 }
213
214 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
215 {
216 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
217 return 0;
218 }
219
220 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
221 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
222 .probe_slot = mrst_hc_probe_slot,
223 };
224
225 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
226 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
227 .probe = mrst_hc_probe,
228 };
229
230 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
231 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
232 .allow_runtime_pm = true,
233 .own_cd_for_runtime_pm = true,
234 };
235
236 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
237 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
238 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
239 .allow_runtime_pm = true,
240 .probe_slot = mfd_sdio_probe_slot,
241 };
242
243 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
245 .allow_runtime_pm = true,
246 .probe_slot = mfd_emmc_probe_slot,
247 };
248
249 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
250 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
251 .probe_slot = pch_hc_probe_slot,
252 };
253
254 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
255 {
256 u8 reg;
257
258 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
259 reg |= 0x10;
260 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
261 /* For eMMC, minimum is 1us but give it 9us for good measure */
262 udelay(9);
263 reg &= ~0x10;
264 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
265 /* For eMMC, minimum is 200us but give it 300us for good measure */
266 usleep_range(300, 1000);
267 }
268
269 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
270 {
271 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
272 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
273 MMC_CAP_BUS_WIDTH_TEST |
274 MMC_CAP_WAIT_WHILE_BUSY;
275 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
276 slot->hw_reset = sdhci_pci_int_hw_reset;
277 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
278 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
279 return 0;
280 }
281
282 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
283 {
284 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
285 MMC_CAP_BUS_WIDTH_TEST |
286 MMC_CAP_WAIT_WHILE_BUSY;
287 return 0;
288 }
289
290 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
291 {
292 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
293 MMC_CAP_WAIT_WHILE_BUSY;
294 slot->cd_con_id = NULL;
295 slot->cd_idx = 0;
296 slot->cd_override_level = true;
297 return 0;
298 }
299
300 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
301 .allow_runtime_pm = true,
302 .probe_slot = byt_emmc_probe_slot,
303 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
304 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
305 SDHCI_QUIRK2_STOP_WITH_TC,
306 };
307
308 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
309 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
310 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
311 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
312 .allow_runtime_pm = true,
313 .probe_slot = byt_sdio_probe_slot,
314 };
315
316 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
317 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
318 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
319 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
320 SDHCI_QUIRK2_STOP_WITH_TC,
321 .allow_runtime_pm = true,
322 .own_cd_for_runtime_pm = true,
323 .probe_slot = byt_sd_probe_slot,
324 };
325
326 /* Define Host controllers for Intel Merrifield platform */
327 #define INTEL_MRFL_EMMC_0 0
328 #define INTEL_MRFL_EMMC_1 1
329
330 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
331 {
332 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
333 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
334 /* SD support is not ready yet */
335 return -ENODEV;
336
337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
338 MMC_CAP_1_8V_DDR;
339
340 return 0;
341 }
342
343 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
344 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
345 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
346 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
347 .allow_runtime_pm = true,
348 .probe_slot = intel_mrfl_mmc_probe_slot,
349 };
350
351 /* O2Micro extra registers */
352 #define O2_SD_LOCK_WP 0xD3
353 #define O2_SD_MULTI_VCC3V 0xEE
354 #define O2_SD_CLKREQ 0xEC
355 #define O2_SD_CAPS 0xE0
356 #define O2_SD_ADMA1 0xE2
357 #define O2_SD_ADMA2 0xE7
358 #define O2_SD_INF_MOD 0xF1
359
360 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
361 {
362 u8 scratch;
363 int ret;
364
365 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
366 if (ret)
367 return ret;
368
369 /*
370 * Turn PMOS on [bit 0], set over current detection to 2.4 V
371 * [bit 1:2] and enable over current debouncing [bit 6].
372 */
373 if (on)
374 scratch |= 0x47;
375 else
376 scratch &= ~0x47;
377
378 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
379 if (ret)
380 return ret;
381
382 return 0;
383 }
384
385 static int jmicron_probe(struct sdhci_pci_chip *chip)
386 {
387 int ret;
388 u16 mmcdev = 0;
389
390 if (chip->pdev->revision == 0) {
391 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
392 SDHCI_QUIRK_32BIT_DMA_SIZE |
393 SDHCI_QUIRK_32BIT_ADMA_SIZE |
394 SDHCI_QUIRK_RESET_AFTER_REQUEST |
395 SDHCI_QUIRK_BROKEN_SMALL_PIO;
396 }
397
398 /*
399 * JMicron chips can have two interfaces to the same hardware
400 * in order to work around limitations in Microsoft's driver.
401 * We need to make sure we only bind to one of them.
402 *
403 * This code assumes two things:
404 *
405 * 1. The PCI code adds subfunctions in order.
406 *
407 * 2. The MMC interface has a lower subfunction number
408 * than the SD interface.
409 */
410 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
411 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
412 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
413 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
414
415 if (mmcdev) {
416 struct pci_dev *sd_dev;
417
418 sd_dev = NULL;
419 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
420 mmcdev, sd_dev)) != NULL) {
421 if ((PCI_SLOT(chip->pdev->devfn) ==
422 PCI_SLOT(sd_dev->devfn)) &&
423 (chip->pdev->bus == sd_dev->bus))
424 break;
425 }
426
427 if (sd_dev) {
428 pci_dev_put(sd_dev);
429 dev_info(&chip->pdev->dev, "Refusing to bind to "
430 "secondary interface.\n");
431 return -ENODEV;
432 }
433 }
434
435 /*
436 * JMicron chips need a bit of a nudge to enable the power
437 * output pins.
438 */
439 ret = jmicron_pmos(chip, 1);
440 if (ret) {
441 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
442 return ret;
443 }
444
445 /* quirk for unsable RO-detection on JM388 chips */
446 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
447 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
448 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
449
450 return 0;
451 }
452
453 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
454 {
455 u8 scratch;
456
457 scratch = readb(host->ioaddr + 0xC0);
458
459 if (on)
460 scratch |= 0x01;
461 else
462 scratch &= ~0x01;
463
464 writeb(scratch, host->ioaddr + 0xC0);
465 }
466
467 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
468 {
469 if (slot->chip->pdev->revision == 0) {
470 u16 version;
471
472 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
473 version = (version & SDHCI_VENDOR_VER_MASK) >>
474 SDHCI_VENDOR_VER_SHIFT;
475
476 /*
477 * Older versions of the chip have lots of nasty glitches
478 * in the ADMA engine. It's best just to avoid it
479 * completely.
480 */
481 if (version < 0xAC)
482 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
483 }
484
485 /* JM388 MMC doesn't support 1.8V while SD supports it */
486 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
487 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
488 MMC_VDD_29_30 | MMC_VDD_30_31 |
489 MMC_VDD_165_195; /* allow 1.8V */
490 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
491 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
492 }
493
494 /*
495 * The secondary interface requires a bit set to get the
496 * interrupts.
497 */
498 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
499 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
500 jmicron_enable_mmc(slot->host, 1);
501
502 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
503
504 return 0;
505 }
506
507 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
508 {
509 if (dead)
510 return;
511
512 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
514 jmicron_enable_mmc(slot->host, 0);
515 }
516
517 static int jmicron_suspend(struct sdhci_pci_chip *chip)
518 {
519 int i;
520
521 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
522 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
523 for (i = 0; i < chip->num_slots; i++)
524 jmicron_enable_mmc(chip->slots[i]->host, 0);
525 }
526
527 return 0;
528 }
529
530 static int jmicron_resume(struct sdhci_pci_chip *chip)
531 {
532 int ret, i;
533
534 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
535 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
536 for (i = 0; i < chip->num_slots; i++)
537 jmicron_enable_mmc(chip->slots[i]->host, 1);
538 }
539
540 ret = jmicron_pmos(chip, 1);
541 if (ret) {
542 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
543 return ret;
544 }
545
546 return 0;
547 }
548
549 static const struct sdhci_pci_fixes sdhci_o2 = {
550 .probe = sdhci_pci_o2_probe,
551 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
552 .probe_slot = sdhci_pci_o2_probe_slot,
553 .resume = sdhci_pci_o2_resume,
554 };
555
556 static const struct sdhci_pci_fixes sdhci_jmicron = {
557 .probe = jmicron_probe,
558
559 .probe_slot = jmicron_probe_slot,
560 .remove_slot = jmicron_remove_slot,
561
562 .suspend = jmicron_suspend,
563 .resume = jmicron_resume,
564 };
565
566 /* SysKonnect CardBus2SDIO extra registers */
567 #define SYSKT_CTRL 0x200
568 #define SYSKT_RDFIFO_STAT 0x204
569 #define SYSKT_WRFIFO_STAT 0x208
570 #define SYSKT_POWER_DATA 0x20c
571 #define SYSKT_POWER_330 0xef
572 #define SYSKT_POWER_300 0xf8
573 #define SYSKT_POWER_184 0xcc
574 #define SYSKT_POWER_CMD 0x20d
575 #define SYSKT_POWER_START (1 << 7)
576 #define SYSKT_POWER_STATUS 0x20e
577 #define SYSKT_POWER_STATUS_OK (1 << 0)
578 #define SYSKT_BOARD_REV 0x210
579 #define SYSKT_CHIP_REV 0x211
580 #define SYSKT_CONF_DATA 0x212
581 #define SYSKT_CONF_DATA_1V8 (1 << 2)
582 #define SYSKT_CONF_DATA_2V5 (1 << 1)
583 #define SYSKT_CONF_DATA_3V3 (1 << 0)
584
585 static int syskt_probe(struct sdhci_pci_chip *chip)
586 {
587 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
588 chip->pdev->class &= ~0x0000FF;
589 chip->pdev->class |= PCI_SDHCI_IFDMA;
590 }
591 return 0;
592 }
593
594 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
595 {
596 int tm, ps;
597
598 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
599 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
600 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
601 "board rev %d.%d, chip rev %d.%d\n",
602 board_rev >> 4, board_rev & 0xf,
603 chip_rev >> 4, chip_rev & 0xf);
604 if (chip_rev >= 0x20)
605 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
606
607 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
608 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
609 udelay(50);
610 tm = 10; /* Wait max 1 ms */
611 do {
612 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
613 if (ps & SYSKT_POWER_STATUS_OK)
614 break;
615 udelay(100);
616 } while (--tm);
617 if (!tm) {
618 dev_err(&slot->chip->pdev->dev,
619 "power regulator never stabilized");
620 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
621 return -ENODEV;
622 }
623
624 return 0;
625 }
626
627 static const struct sdhci_pci_fixes sdhci_syskt = {
628 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
629 .probe = syskt_probe,
630 .probe_slot = syskt_probe_slot,
631 };
632
633 static int via_probe(struct sdhci_pci_chip *chip)
634 {
635 if (chip->pdev->revision == 0x10)
636 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
637
638 return 0;
639 }
640
641 static const struct sdhci_pci_fixes sdhci_via = {
642 .probe = via_probe,
643 };
644
645 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
646 {
647 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
648 return 0;
649 }
650
651 static const struct sdhci_pci_fixes sdhci_rtsx = {
652 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
653 SDHCI_QUIRK2_BROKEN_DDR50,
654 .probe_slot = rtsx_probe_slot,
655 };
656
657 static int amd_probe(struct sdhci_pci_chip *chip)
658 {
659 struct pci_dev *smbus_dev;
660
661 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
662 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
663
664 if (smbus_dev && (smbus_dev->revision < 0x51)) {
665 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
666 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
667 }
668
669 return 0;
670 }
671
672 static const struct sdhci_pci_fixes sdhci_amd = {
673 .probe = amd_probe,
674 };
675
676 static const struct pci_device_id pci_ids[] = {
677 {
678 .vendor = PCI_VENDOR_ID_RICOH,
679 .device = PCI_DEVICE_ID_RICOH_R5C822,
680 .subvendor = PCI_ANY_ID,
681 .subdevice = PCI_ANY_ID,
682 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
683 },
684
685 {
686 .vendor = PCI_VENDOR_ID_RICOH,
687 .device = 0x843,
688 .subvendor = PCI_ANY_ID,
689 .subdevice = PCI_ANY_ID,
690 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
691 },
692
693 {
694 .vendor = PCI_VENDOR_ID_RICOH,
695 .device = 0xe822,
696 .subvendor = PCI_ANY_ID,
697 .subdevice = PCI_ANY_ID,
698 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
699 },
700
701 {
702 .vendor = PCI_VENDOR_ID_RICOH,
703 .device = 0xe823,
704 .subvendor = PCI_ANY_ID,
705 .subdevice = PCI_ANY_ID,
706 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
707 },
708
709 {
710 .vendor = PCI_VENDOR_ID_ENE,
711 .device = PCI_DEVICE_ID_ENE_CB712_SD,
712 .subvendor = PCI_ANY_ID,
713 .subdevice = PCI_ANY_ID,
714 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
715 },
716
717 {
718 .vendor = PCI_VENDOR_ID_ENE,
719 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
720 .subvendor = PCI_ANY_ID,
721 .subdevice = PCI_ANY_ID,
722 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
723 },
724
725 {
726 .vendor = PCI_VENDOR_ID_ENE,
727 .device = PCI_DEVICE_ID_ENE_CB714_SD,
728 .subvendor = PCI_ANY_ID,
729 .subdevice = PCI_ANY_ID,
730 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
731 },
732
733 {
734 .vendor = PCI_VENDOR_ID_ENE,
735 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
736 .subvendor = PCI_ANY_ID,
737 .subdevice = PCI_ANY_ID,
738 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
739 },
740
741 {
742 .vendor = PCI_VENDOR_ID_MARVELL,
743 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
744 .subvendor = PCI_ANY_ID,
745 .subdevice = PCI_ANY_ID,
746 .driver_data = (kernel_ulong_t)&sdhci_cafe,
747 },
748
749 {
750 .vendor = PCI_VENDOR_ID_JMICRON,
751 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
752 .subvendor = PCI_ANY_ID,
753 .subdevice = PCI_ANY_ID,
754 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
755 },
756
757 {
758 .vendor = PCI_VENDOR_ID_JMICRON,
759 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
760 .subvendor = PCI_ANY_ID,
761 .subdevice = PCI_ANY_ID,
762 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
763 },
764
765 {
766 .vendor = PCI_VENDOR_ID_JMICRON,
767 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
768 .subvendor = PCI_ANY_ID,
769 .subdevice = PCI_ANY_ID,
770 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
771 },
772
773 {
774 .vendor = PCI_VENDOR_ID_JMICRON,
775 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
776 .subvendor = PCI_ANY_ID,
777 .subdevice = PCI_ANY_ID,
778 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
779 },
780
781 {
782 .vendor = PCI_VENDOR_ID_SYSKONNECT,
783 .device = 0x8000,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .driver_data = (kernel_ulong_t)&sdhci_syskt,
787 },
788
789 {
790 .vendor = PCI_VENDOR_ID_VIA,
791 .device = 0x95d0,
792 .subvendor = PCI_ANY_ID,
793 .subdevice = PCI_ANY_ID,
794 .driver_data = (kernel_ulong_t)&sdhci_via,
795 },
796
797 {
798 .vendor = PCI_VENDOR_ID_REALTEK,
799 .device = 0x5250,
800 .subvendor = PCI_ANY_ID,
801 .subdevice = PCI_ANY_ID,
802 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
803 },
804
805 {
806 .vendor = PCI_VENDOR_ID_INTEL,
807 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
808 .subvendor = PCI_ANY_ID,
809 .subdevice = PCI_ANY_ID,
810 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
811 },
812
813 {
814 .vendor = PCI_VENDOR_ID_INTEL,
815 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
819 },
820
821 {
822 .vendor = PCI_VENDOR_ID_INTEL,
823 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
824 .subvendor = PCI_ANY_ID,
825 .subdevice = PCI_ANY_ID,
826 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
827 },
828
829 {
830 .vendor = PCI_VENDOR_ID_INTEL,
831 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
832 .subvendor = PCI_ANY_ID,
833 .subdevice = PCI_ANY_ID,
834 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
835 },
836
837 {
838 .vendor = PCI_VENDOR_ID_INTEL,
839 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
840 .subvendor = PCI_ANY_ID,
841 .subdevice = PCI_ANY_ID,
842 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
843 },
844
845 {
846 .vendor = PCI_VENDOR_ID_INTEL,
847 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
848 .subvendor = PCI_ANY_ID,
849 .subdevice = PCI_ANY_ID,
850 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
851 },
852
853 {
854 .vendor = PCI_VENDOR_ID_INTEL,
855 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
856 .subvendor = PCI_ANY_ID,
857 .subdevice = PCI_ANY_ID,
858 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
859 },
860
861 {
862 .vendor = PCI_VENDOR_ID_INTEL,
863 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
864 .subvendor = PCI_ANY_ID,
865 .subdevice = PCI_ANY_ID,
866 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
867 },
868
869 {
870 .vendor = PCI_VENDOR_ID_INTEL,
871 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
872 .subvendor = PCI_ANY_ID,
873 .subdevice = PCI_ANY_ID,
874 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
875 },
876
877 {
878 .vendor = PCI_VENDOR_ID_INTEL,
879 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
880 .subvendor = PCI_ANY_ID,
881 .subdevice = PCI_ANY_ID,
882 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
883 },
884
885 {
886 .vendor = PCI_VENDOR_ID_INTEL,
887 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
888 .subvendor = PCI_ANY_ID,
889 .subdevice = PCI_ANY_ID,
890 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
891 },
892
893 {
894 .vendor = PCI_VENDOR_ID_INTEL,
895 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
896 .subvendor = PCI_ANY_ID,
897 .subdevice = PCI_ANY_ID,
898 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
899 },
900
901 {
902 .vendor = PCI_VENDOR_ID_INTEL,
903 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
904 .subvendor = PCI_ANY_ID,
905 .subdevice = PCI_ANY_ID,
906 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
907 },
908
909 {
910 .vendor = PCI_VENDOR_ID_INTEL,
911 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
912 .subvendor = PCI_ANY_ID,
913 .subdevice = PCI_ANY_ID,
914 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
915 },
916
917 {
918 .vendor = PCI_VENDOR_ID_INTEL,
919 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
920 .subvendor = PCI_ANY_ID,
921 .subdevice = PCI_ANY_ID,
922 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
923 },
924
925 {
926 .vendor = PCI_VENDOR_ID_INTEL,
927 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
928 .subvendor = PCI_ANY_ID,
929 .subdevice = PCI_ANY_ID,
930 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
931 },
932
933 {
934 .vendor = PCI_VENDOR_ID_INTEL,
935 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
936 .subvendor = PCI_ANY_ID,
937 .subdevice = PCI_ANY_ID,
938 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
939 },
940
941 {
942 .vendor = PCI_VENDOR_ID_INTEL,
943 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
944 .subvendor = PCI_ANY_ID,
945 .subdevice = PCI_ANY_ID,
946 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
947 },
948
949 {
950 .vendor = PCI_VENDOR_ID_INTEL,
951 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
952 .subvendor = PCI_ANY_ID,
953 .subdevice = PCI_ANY_ID,
954 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
955 },
956
957 {
958 .vendor = PCI_VENDOR_ID_INTEL,
959 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
960 .subvendor = PCI_ANY_ID,
961 .subdevice = PCI_ANY_ID,
962 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
963 },
964
965 {
966 .vendor = PCI_VENDOR_ID_INTEL,
967 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
968 .subvendor = PCI_ANY_ID,
969 .subdevice = PCI_ANY_ID,
970 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
971 },
972
973 {
974 .vendor = PCI_VENDOR_ID_INTEL,
975 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
976 .subvendor = PCI_ANY_ID,
977 .subdevice = PCI_ANY_ID,
978 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
979 },
980
981 {
982 .vendor = PCI_VENDOR_ID_INTEL,
983 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
984 .subvendor = PCI_ANY_ID,
985 .subdevice = PCI_ANY_ID,
986 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
987 },
988
989 {
990 .vendor = PCI_VENDOR_ID_INTEL,
991 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
992 .subvendor = PCI_ANY_ID,
993 .subdevice = PCI_ANY_ID,
994 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
995 },
996 {
997 .vendor = PCI_VENDOR_ID_O2,
998 .device = PCI_DEVICE_ID_O2_8120,
999 .subvendor = PCI_ANY_ID,
1000 .subdevice = PCI_ANY_ID,
1001 .driver_data = (kernel_ulong_t)&sdhci_o2,
1002 },
1003
1004 {
1005 .vendor = PCI_VENDOR_ID_O2,
1006 .device = PCI_DEVICE_ID_O2_8220,
1007 .subvendor = PCI_ANY_ID,
1008 .subdevice = PCI_ANY_ID,
1009 .driver_data = (kernel_ulong_t)&sdhci_o2,
1010 },
1011
1012 {
1013 .vendor = PCI_VENDOR_ID_O2,
1014 .device = PCI_DEVICE_ID_O2_8221,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .driver_data = (kernel_ulong_t)&sdhci_o2,
1018 },
1019
1020 {
1021 .vendor = PCI_VENDOR_ID_O2,
1022 .device = PCI_DEVICE_ID_O2_8320,
1023 .subvendor = PCI_ANY_ID,
1024 .subdevice = PCI_ANY_ID,
1025 .driver_data = (kernel_ulong_t)&sdhci_o2,
1026 },
1027
1028 {
1029 .vendor = PCI_VENDOR_ID_O2,
1030 .device = PCI_DEVICE_ID_O2_8321,
1031 .subvendor = PCI_ANY_ID,
1032 .subdevice = PCI_ANY_ID,
1033 .driver_data = (kernel_ulong_t)&sdhci_o2,
1034 },
1035
1036 {
1037 .vendor = PCI_VENDOR_ID_O2,
1038 .device = PCI_DEVICE_ID_O2_FUJIN2,
1039 .subvendor = PCI_ANY_ID,
1040 .subdevice = PCI_ANY_ID,
1041 .driver_data = (kernel_ulong_t)&sdhci_o2,
1042 },
1043
1044 {
1045 .vendor = PCI_VENDOR_ID_O2,
1046 .device = PCI_DEVICE_ID_O2_SDS0,
1047 .subvendor = PCI_ANY_ID,
1048 .subdevice = PCI_ANY_ID,
1049 .driver_data = (kernel_ulong_t)&sdhci_o2,
1050 },
1051
1052 {
1053 .vendor = PCI_VENDOR_ID_O2,
1054 .device = PCI_DEVICE_ID_O2_SDS1,
1055 .subvendor = PCI_ANY_ID,
1056 .subdevice = PCI_ANY_ID,
1057 .driver_data = (kernel_ulong_t)&sdhci_o2,
1058 },
1059
1060 {
1061 .vendor = PCI_VENDOR_ID_O2,
1062 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1063 .subvendor = PCI_ANY_ID,
1064 .subdevice = PCI_ANY_ID,
1065 .driver_data = (kernel_ulong_t)&sdhci_o2,
1066 },
1067
1068 {
1069 .vendor = PCI_VENDOR_ID_O2,
1070 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1071 .subvendor = PCI_ANY_ID,
1072 .subdevice = PCI_ANY_ID,
1073 .driver_data = (kernel_ulong_t)&sdhci_o2,
1074 },
1075 {
1076 .vendor = PCI_VENDOR_ID_AMD,
1077 .device = PCI_ANY_ID,
1078 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1079 .class_mask = 0xFFFF00,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .driver_data = (kernel_ulong_t)&sdhci_amd,
1083 },
1084 { /* Generic SD host controller */
1085 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1086 },
1087
1088 { /* end: all zeroes */ },
1089 };
1090
1091 MODULE_DEVICE_TABLE(pci, pci_ids);
1092
1093 /*****************************************************************************\
1094 * *
1095 * SDHCI core callbacks *
1096 * *
1097 \*****************************************************************************/
1098
1099 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1100 {
1101 struct sdhci_pci_slot *slot;
1102 struct pci_dev *pdev;
1103 int ret = -1;
1104
1105 slot = sdhci_priv(host);
1106 pdev = slot->chip->pdev;
1107
1108 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1109 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1110 (host->flags & SDHCI_USE_SDMA)) {
1111 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1112 "doesn't fully claim to support it.\n");
1113 }
1114
1115 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1116 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1117 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1118 } else {
1119 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1120 if (ret)
1121 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1122 }
1123 }
1124 if (ret)
1125 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1126 if (ret)
1127 return ret;
1128
1129 pci_set_master(pdev);
1130
1131 return 0;
1132 }
1133
1134 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1135 {
1136 u8 ctrl;
1137
1138 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1139
1140 switch (width) {
1141 case MMC_BUS_WIDTH_8:
1142 ctrl |= SDHCI_CTRL_8BITBUS;
1143 ctrl &= ~SDHCI_CTRL_4BITBUS;
1144 break;
1145 case MMC_BUS_WIDTH_4:
1146 ctrl |= SDHCI_CTRL_4BITBUS;
1147 ctrl &= ~SDHCI_CTRL_8BITBUS;
1148 break;
1149 default:
1150 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1151 break;
1152 }
1153
1154 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1155 }
1156
1157 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1158 {
1159 struct sdhci_pci_slot *slot = sdhci_priv(host);
1160 int rst_n_gpio = slot->rst_n_gpio;
1161
1162 if (!gpio_is_valid(rst_n_gpio))
1163 return;
1164 gpio_set_value_cansleep(rst_n_gpio, 0);
1165 /* For eMMC, minimum is 1us but give it 10us for good measure */
1166 udelay(10);
1167 gpio_set_value_cansleep(rst_n_gpio, 1);
1168 /* For eMMC, minimum is 200us but give it 300us for good measure */
1169 usleep_range(300, 1000);
1170 }
1171
1172 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1173 {
1174 struct sdhci_pci_slot *slot = sdhci_priv(host);
1175
1176 if (slot->hw_reset)
1177 slot->hw_reset(host);
1178 }
1179
1180 static const struct sdhci_ops sdhci_pci_ops = {
1181 .set_clock = sdhci_set_clock,
1182 .enable_dma = sdhci_pci_enable_dma,
1183 .set_bus_width = sdhci_pci_set_bus_width,
1184 .reset = sdhci_reset,
1185 .set_uhs_signaling = sdhci_set_uhs_signaling,
1186 .hw_reset = sdhci_pci_hw_reset,
1187 };
1188
1189 /*****************************************************************************\
1190 * *
1191 * Suspend/resume *
1192 * *
1193 \*****************************************************************************/
1194
1195 #ifdef CONFIG_PM
1196
1197 static int sdhci_pci_suspend(struct device *dev)
1198 {
1199 struct pci_dev *pdev = to_pci_dev(dev);
1200 struct sdhci_pci_chip *chip;
1201 struct sdhci_pci_slot *slot;
1202 mmc_pm_flag_t slot_pm_flags;
1203 mmc_pm_flag_t pm_flags = 0;
1204 int i, ret;
1205
1206 chip = pci_get_drvdata(pdev);
1207 if (!chip)
1208 return 0;
1209
1210 for (i = 0; i < chip->num_slots; i++) {
1211 slot = chip->slots[i];
1212 if (!slot)
1213 continue;
1214
1215 ret = sdhci_suspend_host(slot->host);
1216
1217 if (ret)
1218 goto err_pci_suspend;
1219
1220 slot_pm_flags = slot->host->mmc->pm_flags;
1221 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1222 sdhci_enable_irq_wakeups(slot->host);
1223
1224 pm_flags |= slot_pm_flags;
1225 }
1226
1227 if (chip->fixes && chip->fixes->suspend) {
1228 ret = chip->fixes->suspend(chip);
1229 if (ret)
1230 goto err_pci_suspend;
1231 }
1232
1233 if (pm_flags & MMC_PM_KEEP_POWER) {
1234 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1235 device_init_wakeup(dev, true);
1236 else
1237 device_init_wakeup(dev, false);
1238 } else
1239 device_init_wakeup(dev, false);
1240
1241 return 0;
1242
1243 err_pci_suspend:
1244 while (--i >= 0)
1245 sdhci_resume_host(chip->slots[i]->host);
1246 return ret;
1247 }
1248
1249 static int sdhci_pci_resume(struct device *dev)
1250 {
1251 struct pci_dev *pdev = to_pci_dev(dev);
1252 struct sdhci_pci_chip *chip;
1253 struct sdhci_pci_slot *slot;
1254 int i, ret;
1255
1256 chip = pci_get_drvdata(pdev);
1257 if (!chip)
1258 return 0;
1259
1260 if (chip->fixes && chip->fixes->resume) {
1261 ret = chip->fixes->resume(chip);
1262 if (ret)
1263 return ret;
1264 }
1265
1266 for (i = 0; i < chip->num_slots; i++) {
1267 slot = chip->slots[i];
1268 if (!slot)
1269 continue;
1270
1271 ret = sdhci_resume_host(slot->host);
1272 if (ret)
1273 return ret;
1274 }
1275
1276 return 0;
1277 }
1278
1279 static int sdhci_pci_runtime_suspend(struct device *dev)
1280 {
1281 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1282 struct sdhci_pci_chip *chip;
1283 struct sdhci_pci_slot *slot;
1284 int i, ret;
1285
1286 chip = pci_get_drvdata(pdev);
1287 if (!chip)
1288 return 0;
1289
1290 for (i = 0; i < chip->num_slots; i++) {
1291 slot = chip->slots[i];
1292 if (!slot)
1293 continue;
1294
1295 ret = sdhci_runtime_suspend_host(slot->host);
1296
1297 if (ret)
1298 goto err_pci_runtime_suspend;
1299 }
1300
1301 if (chip->fixes && chip->fixes->suspend) {
1302 ret = chip->fixes->suspend(chip);
1303 if (ret)
1304 goto err_pci_runtime_suspend;
1305 }
1306
1307 return 0;
1308
1309 err_pci_runtime_suspend:
1310 while (--i >= 0)
1311 sdhci_runtime_resume_host(chip->slots[i]->host);
1312 return ret;
1313 }
1314
1315 static int sdhci_pci_runtime_resume(struct device *dev)
1316 {
1317 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1318 struct sdhci_pci_chip *chip;
1319 struct sdhci_pci_slot *slot;
1320 int i, ret;
1321
1322 chip = pci_get_drvdata(pdev);
1323 if (!chip)
1324 return 0;
1325
1326 if (chip->fixes && chip->fixes->resume) {
1327 ret = chip->fixes->resume(chip);
1328 if (ret)
1329 return ret;
1330 }
1331
1332 for (i = 0; i < chip->num_slots; i++) {
1333 slot = chip->slots[i];
1334 if (!slot)
1335 continue;
1336
1337 ret = sdhci_runtime_resume_host(slot->host);
1338 if (ret)
1339 return ret;
1340 }
1341
1342 return 0;
1343 }
1344
1345 static int sdhci_pci_runtime_idle(struct device *dev)
1346 {
1347 return 0;
1348 }
1349
1350 #else /* CONFIG_PM */
1351
1352 #define sdhci_pci_suspend NULL
1353 #define sdhci_pci_resume NULL
1354
1355 #endif /* CONFIG_PM */
1356
1357 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1358 .suspend = sdhci_pci_suspend,
1359 .resume = sdhci_pci_resume,
1360 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1361 sdhci_pci_runtime_resume, sdhci_pci_runtime_idle)
1362 };
1363
1364 /*****************************************************************************\
1365 * *
1366 * Device probing/removal *
1367 * *
1368 \*****************************************************************************/
1369
1370 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1371 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1372 int slotno)
1373 {
1374 struct sdhci_pci_slot *slot;
1375 struct sdhci_host *host;
1376 int ret, bar = first_bar + slotno;
1377
1378 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1379 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1380 return ERR_PTR(-ENODEV);
1381 }
1382
1383 if (pci_resource_len(pdev, bar) < 0x100) {
1384 dev_err(&pdev->dev, "Invalid iomem size. You may "
1385 "experience problems.\n");
1386 }
1387
1388 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1389 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1390 return ERR_PTR(-ENODEV);
1391 }
1392
1393 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1394 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1395 return ERR_PTR(-ENODEV);
1396 }
1397
1398 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1399 if (IS_ERR(host)) {
1400 dev_err(&pdev->dev, "cannot allocate host\n");
1401 return ERR_CAST(host);
1402 }
1403
1404 slot = sdhci_priv(host);
1405
1406 slot->chip = chip;
1407 slot->host = host;
1408 slot->pci_bar = bar;
1409 slot->rst_n_gpio = -EINVAL;
1410 slot->cd_gpio = -EINVAL;
1411 slot->cd_idx = -1;
1412
1413 /* Retrieve platform data if there is any */
1414 if (*sdhci_pci_get_data)
1415 slot->data = sdhci_pci_get_data(pdev, slotno);
1416
1417 if (slot->data) {
1418 if (slot->data->setup) {
1419 ret = slot->data->setup(slot->data);
1420 if (ret) {
1421 dev_err(&pdev->dev, "platform setup failed\n");
1422 goto free;
1423 }
1424 }
1425 slot->rst_n_gpio = slot->data->rst_n_gpio;
1426 slot->cd_gpio = slot->data->cd_gpio;
1427 }
1428
1429 host->hw_name = "PCI";
1430 host->ops = &sdhci_pci_ops;
1431 host->quirks = chip->quirks;
1432 host->quirks2 = chip->quirks2;
1433
1434 host->irq = pdev->irq;
1435
1436 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1437 if (ret) {
1438 dev_err(&pdev->dev, "cannot request region\n");
1439 goto cleanup;
1440 }
1441
1442 host->ioaddr = pci_ioremap_bar(pdev, bar);
1443 if (!host->ioaddr) {
1444 dev_err(&pdev->dev, "failed to remap registers\n");
1445 ret = -ENOMEM;
1446 goto release;
1447 }
1448
1449 if (chip->fixes && chip->fixes->probe_slot) {
1450 ret = chip->fixes->probe_slot(slot);
1451 if (ret)
1452 goto unmap;
1453 }
1454
1455 if (gpio_is_valid(slot->rst_n_gpio)) {
1456 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1457 gpio_direction_output(slot->rst_n_gpio, 1);
1458 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1459 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1460 } else {
1461 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1462 slot->rst_n_gpio = -EINVAL;
1463 }
1464 }
1465
1466 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1467 host->mmc->slotno = slotno;
1468 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1469
1470 if (slot->cd_idx >= 0 &&
1471 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1472 slot->cd_override_level, 0, NULL)) {
1473 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1474 slot->cd_idx = -1;
1475 }
1476
1477 ret = sdhci_add_host(host);
1478 if (ret)
1479 goto remove;
1480
1481 sdhci_pci_add_own_cd(slot);
1482
1483 /*
1484 * Check if the chip needs a separate GPIO for card detect to wake up
1485 * from runtime suspend. If it is not there, don't allow runtime PM.
1486 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1487 */
1488 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1489 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1490 chip->allow_runtime_pm = false;
1491
1492 return slot;
1493
1494 remove:
1495 if (gpio_is_valid(slot->rst_n_gpio))
1496 gpio_free(slot->rst_n_gpio);
1497
1498 if (chip->fixes && chip->fixes->remove_slot)
1499 chip->fixes->remove_slot(slot, 0);
1500
1501 unmap:
1502 iounmap(host->ioaddr);
1503
1504 release:
1505 pci_release_region(pdev, bar);
1506
1507 cleanup:
1508 if (slot->data && slot->data->cleanup)
1509 slot->data->cleanup(slot->data);
1510
1511 free:
1512 sdhci_free_host(host);
1513
1514 return ERR_PTR(ret);
1515 }
1516
1517 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1518 {
1519 int dead;
1520 u32 scratch;
1521
1522 sdhci_pci_remove_own_cd(slot);
1523
1524 dead = 0;
1525 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1526 if (scratch == (u32)-1)
1527 dead = 1;
1528
1529 sdhci_remove_host(slot->host, dead);
1530
1531 if (gpio_is_valid(slot->rst_n_gpio))
1532 gpio_free(slot->rst_n_gpio);
1533
1534 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1535 slot->chip->fixes->remove_slot(slot, dead);
1536
1537 if (slot->data && slot->data->cleanup)
1538 slot->data->cleanup(slot->data);
1539
1540 pci_release_region(slot->chip->pdev, slot->pci_bar);
1541
1542 sdhci_free_host(slot->host);
1543 }
1544
1545 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1546 {
1547 pm_runtime_put_noidle(dev);
1548 pm_runtime_allow(dev);
1549 pm_runtime_set_autosuspend_delay(dev, 50);
1550 pm_runtime_use_autosuspend(dev);
1551 pm_suspend_ignore_children(dev, 1);
1552 }
1553
1554 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1555 {
1556 pm_runtime_forbid(dev);
1557 pm_runtime_get_noresume(dev);
1558 }
1559
1560 static int sdhci_pci_probe(struct pci_dev *pdev,
1561 const struct pci_device_id *ent)
1562 {
1563 struct sdhci_pci_chip *chip;
1564 struct sdhci_pci_slot *slot;
1565
1566 u8 slots, first_bar;
1567 int ret, i;
1568
1569 BUG_ON(pdev == NULL);
1570 BUG_ON(ent == NULL);
1571
1572 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1573 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1574
1575 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1576 if (ret)
1577 return ret;
1578
1579 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1580 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1581 if (slots == 0)
1582 return -ENODEV;
1583
1584 BUG_ON(slots > MAX_SLOTS);
1585
1586 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1587 if (ret)
1588 return ret;
1589
1590 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1591
1592 if (first_bar > 5) {
1593 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1594 return -ENODEV;
1595 }
1596
1597 ret = pci_enable_device(pdev);
1598 if (ret)
1599 return ret;
1600
1601 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1602 if (!chip) {
1603 ret = -ENOMEM;
1604 goto err;
1605 }
1606
1607 chip->pdev = pdev;
1608 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1609 if (chip->fixes) {
1610 chip->quirks = chip->fixes->quirks;
1611 chip->quirks2 = chip->fixes->quirks2;
1612 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1613 }
1614 chip->num_slots = slots;
1615
1616 pci_set_drvdata(pdev, chip);
1617
1618 if (chip->fixes && chip->fixes->probe) {
1619 ret = chip->fixes->probe(chip);
1620 if (ret)
1621 goto free;
1622 }
1623
1624 slots = chip->num_slots; /* Quirk may have changed this */
1625
1626 for (i = 0; i < slots; i++) {
1627 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1628 if (IS_ERR(slot)) {
1629 for (i--; i >= 0; i--)
1630 sdhci_pci_remove_slot(chip->slots[i]);
1631 ret = PTR_ERR(slot);
1632 goto free;
1633 }
1634
1635 chip->slots[i] = slot;
1636 }
1637
1638 if (chip->allow_runtime_pm)
1639 sdhci_pci_runtime_pm_allow(&pdev->dev);
1640
1641 return 0;
1642
1643 free:
1644 pci_set_drvdata(pdev, NULL);
1645 kfree(chip);
1646
1647 err:
1648 pci_disable_device(pdev);
1649 return ret;
1650 }
1651
1652 static void sdhci_pci_remove(struct pci_dev *pdev)
1653 {
1654 int i;
1655 struct sdhci_pci_chip *chip;
1656
1657 chip = pci_get_drvdata(pdev);
1658
1659 if (chip) {
1660 if (chip->allow_runtime_pm)
1661 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1662
1663 for (i = 0; i < chip->num_slots; i++)
1664 sdhci_pci_remove_slot(chip->slots[i]);
1665
1666 pci_set_drvdata(pdev, NULL);
1667 kfree(chip);
1668 }
1669
1670 pci_disable_device(pdev);
1671 }
1672
1673 static struct pci_driver sdhci_driver = {
1674 .name = "sdhci-pci",
1675 .id_table = pci_ids,
1676 .probe = sdhci_pci_probe,
1677 .remove = sdhci_pci_remove,
1678 .driver = {
1679 .pm = &sdhci_pci_pm_ops
1680 },
1681 };
1682
1683 module_pci_driver(sdhci_driver);
1684
1685 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1686 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1687 MODULE_LICENSE("GPL");
Linux with added FPC-III support