?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
m68k/defconfig: Enable automounting of devtmpfs at /dev
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pxav3.c
blob45238871192da1d6553268d82659dce3cc600d68
1 /*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Mingwei Wang <mwwang@marvell.com>
6 * Philip Rakity <prakity@marvell.com>
7 * Mark Brown <markb@marvell.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/mmc/card.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/platform_data/pxa_sdhci.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/module.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/mbus.h>
38
39 #include "sdhci.h"
40 #include "sdhci-pltfm.h"
41
42 #define PXAV3_RPM_DELAY_MS 50
43
44 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A
45 #define SDCLK_SEL 0x100
46 #define SDCLK_DELAY_SHIFT 9
47 #define SDCLK_DELAY_MASK 0x1f
48
49 #define SD_CFG_FIFO_PARAM 0x100
50 #define SDCFG_GEN_PAD_CLK_ON (1<<6)
51 #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
53
54 #define SD_SPI_MODE 0x108
55 #define SD_CE_ATA_1 0x10C
56
57 #define SD_CE_ATA_2 0x10E
58 #define SDCE_MISC_INT (1<<2)
59 #define SDCE_MISC_INT_EN (1<<1)
60
61 struct sdhci_pxa {
62 struct clk *clk_core;
63 struct clk *clk_io;
64 u8 power_mode;
65 };
66
67 /*
68 * These registers are relative to the second register region, for the
69 * MBus bridge.
70 */
71 #define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
72 #define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
73 #define SDHCI_MAX_WIN_NUM 8
74
75 static int mv_conf_mbus_windows(struct platform_device *pdev,
76 const struct mbus_dram_target_info *dram)
77 {
78 int i;
79 void __iomem *regs;
80 struct resource *res;
81
82 if (!dram) {
83 dev_err(&pdev->dev, "no mbus dram info\n");
84 return -EINVAL;
85 }
86
87 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
88 if (!res) {
89 dev_err(&pdev->dev, "cannot get mbus registers\n");
90 return -EINVAL;
91 }
92
93 regs = ioremap(res->start, resource_size(res));
94 if (!regs) {
95 dev_err(&pdev->dev, "cannot map mbus registers\n");
96 return -ENOMEM;
97 }
98
99 for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
100 writel(0, regs + SDHCI_WINDOW_CTRL(i));
101 writel(0, regs + SDHCI_WINDOW_BASE(i));
102 }
103
104 for (i = 0; i < dram->num_cs; i++) {
105 const struct mbus_dram_window *cs = dram->cs + i;
106
107 /* Write size, attributes and target id to control register */
108 writel(((cs->size - 1) & 0xffff0000) |
109 (cs->mbus_attr << 8) |
110 (dram->mbus_dram_target_id << 4) | 1,
111 regs + SDHCI_WINDOW_CTRL(i));
112 /* Write base address to base register */
113 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
114 }
115
116 iounmap(regs);
117
118 return 0;
119 }
120
121 static void pxav3_reset(struct sdhci_host *host, u8 mask)
122 {
123 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
124 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
125
126 sdhci_reset(host, mask);
127
128 if (mask == SDHCI_RESET_ALL) {
129 /*
130 * tune timing of read data/command when crc error happen
131 * no performance impact
132 */
133 if (pdata && 0 != pdata->clk_delay_cycles) {
134 u16 tmp;
135
136 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
137 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
138 << SDCLK_DELAY_SHIFT;
139 tmp |= SDCLK_SEL;
140 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
141 }
142 }
143 }
144
145 #define MAX_WAIT_COUNT 5
146 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
147 {
148 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
149 struct sdhci_pxa *pxa = pltfm_host->priv;
150 u16 tmp;
151 int count;
152
153 if (pxa->power_mode == MMC_POWER_UP
154 && power_mode == MMC_POWER_ON) {
155
156 dev_dbg(mmc_dev(host->mmc),
157 "%s: slot->power_mode = %d,"
158 "ios->power_mode = %d\n",
159 __func__,
160 pxa->power_mode,
161 power_mode);
162
163 /* set we want notice of when 74 clocks are sent */
164 tmp = readw(host->ioaddr + SD_CE_ATA_2);
165 tmp |= SDCE_MISC_INT_EN;
166 writew(tmp, host->ioaddr + SD_CE_ATA_2);
167
168 /* start sending the 74 clocks */
169 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
170 tmp |= SDCFG_GEN_PAD_CLK_ON;
171 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
172
173 /* slowest speed is about 100KHz or 10usec per clock */
174 udelay(740);
175 count = 0;
176
177 while (count++ < MAX_WAIT_COUNT) {
178 if ((readw(host->ioaddr + SD_CE_ATA_2)
179 & SDCE_MISC_INT) == 0)
180 break;
181 udelay(10);
182 }
183
184 if (count == MAX_WAIT_COUNT)
185 dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
186
187 /* clear the interrupt bit if posted */
188 tmp = readw(host->ioaddr + SD_CE_ATA_2);
189 tmp |= SDCE_MISC_INT;
190 writew(tmp, host->ioaddr + SD_CE_ATA_2);
191 }
192 pxa->power_mode = power_mode;
193 }
194
195 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
196 {
197 u16 ctrl_2;
198
199 /*
200 * Set V18_EN -- UHS modes do not work without this.
201 * does not change signaling voltage
202 */
203 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
204
205 /* Select Bus Speed Mode for host */
206 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
207 switch (uhs) {
208 case MMC_TIMING_UHS_SDR12:
209 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
210 break;
211 case MMC_TIMING_UHS_SDR25:
212 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
213 break;
214 case MMC_TIMING_UHS_SDR50:
215 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
216 break;
217 case MMC_TIMING_UHS_SDR104:
218 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
219 break;
220 case MMC_TIMING_MMC_DDR52:
221 case MMC_TIMING_UHS_DDR50:
222 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
223 break;
224 }
225
226 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
227 dev_dbg(mmc_dev(host->mmc),
228 "%s uhs = %d, ctrl_2 = %04X\n",
229 __func__, uhs, ctrl_2);
230 }
231
232 static const struct sdhci_ops pxav3_sdhci_ops = {
233 .set_clock = sdhci_set_clock,
234 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
235 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
236 .set_bus_width = sdhci_set_bus_width,
237 .reset = pxav3_reset,
238 .set_uhs_signaling = pxav3_set_uhs_signaling,
239 };
240
241 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
242 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
243 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
244 | SDHCI_QUIRK_32BIT_ADMA_SIZE
245 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
246 .ops = &pxav3_sdhci_ops,
247 };
248
249 #ifdef CONFIG_OF
250 static const struct of_device_id sdhci_pxav3_of_match[] = {
251 {
252 .compatible = "mrvl,pxav3-mmc",
253 },
254 {
255 .compatible = "marvell,armada-380-sdhci",
256 },
257 {},
258 };
259 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
260
261 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
262 {
263 struct sdhci_pxa_platdata *pdata;
264 struct device_node *np = dev->of_node;
265 u32 clk_delay_cycles;
266
267 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
268 if (!pdata)
269 return NULL;
270
271 of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
272 if (clk_delay_cycles > 0)
273 pdata->clk_delay_cycles = clk_delay_cycles;
274
275 return pdata;
276 }
277 #else
278 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
279 {
280 return NULL;
281 }
282 #endif
283
284 static int sdhci_pxav3_probe(struct platform_device *pdev)
285 {
286 struct sdhci_pltfm_host *pltfm_host;
287 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
288 struct device *dev = &pdev->dev;
289 struct device_node *np = pdev->dev.of_node;
290 struct sdhci_host *host = NULL;
291 struct sdhci_pxa *pxa = NULL;
292 const struct of_device_id *match;
293 int ret;
294
295 pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
296 if (!pxa)
297 return -ENOMEM;
298
299 host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
300 if (IS_ERR(host))
301 return PTR_ERR(host);
302
303 if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
304 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
305 if (ret < 0)
306 goto err_mbus_win;
307 }
308
309
310 pltfm_host = sdhci_priv(host);
311 pltfm_host->priv = pxa;
312
313 pxa->clk_io = devm_clk_get(dev, "io");
314 if (IS_ERR(pxa->clk_io))
315 pxa->clk_io = devm_clk_get(dev, NULL);
316 if (IS_ERR(pxa->clk_io)) {
317 dev_err(dev, "failed to get io clock\n");
318 ret = PTR_ERR(pxa->clk_io);
319 goto err_clk_get;
320 }
321 pltfm_host->clk = pxa->clk_io;
322 clk_prepare_enable(pxa->clk_io);
323
324 pxa->clk_core = devm_clk_get(dev, "core");
325 if (!IS_ERR(pxa->clk_core))
326 clk_prepare_enable(pxa->clk_core);
327
328 /* enable 1/8V DDR capable */
329 host->mmc->caps |= MMC_CAP_1_8V_DDR;
330
331 match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
332 if (match) {
333 ret = mmc_of_parse(host->mmc);
334 if (ret)
335 goto err_of_parse;
336 sdhci_get_of_property(pdev);
337 pdata = pxav3_get_mmc_pdata(dev);
338 } else if (pdata) {
339 /* on-chip device */
340 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
341 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
342
343 /* If slot design supports 8 bit data, indicate this to MMC. */
344 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
345 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
346
347 if (pdata->quirks)
348 host->quirks |= pdata->quirks;
349 if (pdata->quirks2)
350 host->quirks2 |= pdata->quirks2;
351 if (pdata->host_caps)
352 host->mmc->caps |= pdata->host_caps;
353 if (pdata->host_caps2)
354 host->mmc->caps2 |= pdata->host_caps2;
355 if (pdata->pm_caps)
356 host->mmc->pm_caps |= pdata->pm_caps;
357
358 if (gpio_is_valid(pdata->ext_cd_gpio)) {
359 ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
360 0);
361 if (ret) {
362 dev_err(mmc_dev(host->mmc),
363 "failed to allocate card detect gpio\n");
364 goto err_cd_req;
365 }
366 }
367 }
368
369 pm_runtime_enable(&pdev->dev);
370 pm_runtime_get_sync(&pdev->dev);
371 pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
372 pm_runtime_use_autosuspend(&pdev->dev);
373 pm_suspend_ignore_children(&pdev->dev, 1);
374
375 ret = sdhci_add_host(host);
376 if (ret) {
377 dev_err(&pdev->dev, "failed to add host\n");
378 goto err_add_host;
379 }
380
381 platform_set_drvdata(pdev, host);
382
383 if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
384 device_init_wakeup(&pdev->dev, 1);
385 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
386 } else {
387 device_init_wakeup(&pdev->dev, 0);
388 }
389
390 pm_runtime_put_autosuspend(&pdev->dev);
391
392 return 0;
393
394 err_add_host:
395 pm_runtime_put_sync(&pdev->dev);
396 pm_runtime_disable(&pdev->dev);
397 err_of_parse:
398 err_cd_req:
399 clk_disable_unprepare(pxa->clk_io);
400 if (!IS_ERR(pxa->clk_core))
401 clk_disable_unprepare(pxa->clk_core);
402 err_clk_get:
403 err_mbus_win:
404 sdhci_pltfm_free(pdev);
405 return ret;
406 }
407
408 static int sdhci_pxav3_remove(struct platform_device *pdev)
409 {
410 struct sdhci_host *host = platform_get_drvdata(pdev);
411 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
412 struct sdhci_pxa *pxa = pltfm_host->priv;
413
414 pm_runtime_get_sync(&pdev->dev);
415 sdhci_remove_host(host, 1);
416 pm_runtime_disable(&pdev->dev);
417
418 clk_disable_unprepare(pxa->clk_io);
419 if (!IS_ERR(pxa->clk_core))
420 clk_disable_unprepare(pxa->clk_core);
421
422 sdhci_pltfm_free(pdev);
423
424 return 0;
425 }
426
427 #ifdef CONFIG_PM_SLEEP
428 static int sdhci_pxav3_suspend(struct device *dev)
429 {
430 int ret;
431 struct sdhci_host *host = dev_get_drvdata(dev);
432
433 pm_runtime_get_sync(dev);
434 ret = sdhci_suspend_host(host);
435 pm_runtime_mark_last_busy(dev);
436 pm_runtime_put_autosuspend(dev);
437
438 return ret;
439 }
440
441 static int sdhci_pxav3_resume(struct device *dev)
442 {
443 int ret;
444 struct sdhci_host *host = dev_get_drvdata(dev);
445
446 pm_runtime_get_sync(dev);
447 ret = sdhci_resume_host(host);
448 pm_runtime_mark_last_busy(dev);
449 pm_runtime_put_autosuspend(dev);
450
451 return ret;
452 }
453 #endif
454
455 #ifdef CONFIG_PM
456 static int sdhci_pxav3_runtime_suspend(struct device *dev)
457 {
458 struct sdhci_host *host = dev_get_drvdata(dev);
459 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
460 struct sdhci_pxa *pxa = pltfm_host->priv;
461 unsigned long flags;
462
463 spin_lock_irqsave(&host->lock, flags);
464 host->runtime_suspended = true;
465 spin_unlock_irqrestore(&host->lock, flags);
466
467 clk_disable_unprepare(pxa->clk_io);
468 if (!IS_ERR(pxa->clk_core))
469 clk_disable_unprepare(pxa->clk_core);
470
471 return 0;
472 }
473
474 static int sdhci_pxav3_runtime_resume(struct device *dev)
475 {
476 struct sdhci_host *host = dev_get_drvdata(dev);
477 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
478 struct sdhci_pxa *pxa = pltfm_host->priv;
479 unsigned long flags;
480
481 clk_prepare_enable(pxa->clk_io);
482 if (!IS_ERR(pxa->clk_core))
483 clk_prepare_enable(pxa->clk_core);
484
485 spin_lock_irqsave(&host->lock, flags);
486 host->runtime_suspended = false;
487 spin_unlock_irqrestore(&host->lock, flags);
488
489 return 0;
490 }
491 #endif
492
493 #ifdef CONFIG_PM
494 static const struct dev_pm_ops sdhci_pxav3_pmops = {
495 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
496 SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
497 sdhci_pxav3_runtime_resume, NULL)
498 };
499
500 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
501
502 #else
503 #define SDHCI_PXAV3_PMOPS NULL
504 #endif
505
506 static struct platform_driver sdhci_pxav3_driver = {
507 .driver = {
508 .name = "sdhci-pxav3",
509 #ifdef CONFIG_OF
510 .of_match_table = sdhci_pxav3_of_match,
511 #endif
512 .pm = SDHCI_PXAV3_PMOPS,
513 },
514 .probe = sdhci_pxav3_probe,
515 .remove = sdhci_pxav3_remove,
516 };
517
518 module_platform_driver(sdhci_pxav3_driver);
519
520 MODULE_DESCRIPTION("SDHCI driver for pxav3");
521 MODULE_AUTHOR("Marvell International Ltd.");
522 MODULE_LICENSE("GPL v2");
523
Linux with added FPC-III support