drivers/mmc/host/sdhci-tegra.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/slot-gpio.h>
  28
  29 #include "sdhci-pltfm.h"
  30
  31 /* Tegra SDHOST controller vendor register definitions */
  32 #define SDHCI_TEGRA_VENDOR_MISC_CTRL            0x120
  33 #define SDHCI_MISC_CTRL_ENABLE_SDR104           0x8
  34 #define SDHCI_MISC_CTRL_ENABLE_SDR50            0x10
  35 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300   0x20
  36 #define SDHCI_MISC_CTRL_ENABLE_DDR50            0x200
  37
  38 #define NVQUIRK_FORCE_SDHCI_SPEC_200    BIT(0)
  39 #define NVQUIRK_ENABLE_BLOCK_GAP_DET    BIT(1)
  40 #define NVQUIRK_ENABLE_SDHCI_SPEC_300   BIT(2)
  41 #define NVQUIRK_DISABLE_SDR50           BIT(3)
  42 #define NVQUIRK_DISABLE_SDR104          BIT(4)
  43 #define NVQUIRK_DISABLE_DDR50           BIT(5)
  44
  45 struct sdhci_tegra_soc_data {
  46         const struct sdhci_pltfm_data *pdata;
  47         u32 nvquirks;
  48 };
  49
  50 struct sdhci_tegra {
  51         const struct sdhci_tegra_soc_data *soc_data;
  52         int power_gpio;
  53 };
  54
  55 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  56 {
  57         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  58         struct sdhci_tegra *tegra_host = pltfm_host->priv;
  59         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  60
  61         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  62                         (reg == SDHCI_HOST_VERSION))) {
  63                 /* Erratum: Version register is invalid in HW. */
  64                 return SDHCI_SPEC_200;
  65         }
  66
  67         return readw(host->ioaddr + reg);
  68 }
  69
  70 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  71 {
  72         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  73         struct sdhci_tegra *tegra_host = pltfm_host->priv;
  74         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  75
  76         /* Seems like we're getting spurious timeout and crc errors, so
  77          * disable signalling of them. In case of real errors software
  78          * timers should take care of eventually detecting them.
  79          */
  80         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  81                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  82
  83         writel(val, host->ioaddr + reg);
  84
  85         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
  86                         (reg == SDHCI_INT_ENABLE))) {
  87                 /* Erratum: Must enable block gap interrupt detection */
  88                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  89                 if (val & SDHCI_INT_CARD_INT)
  90                         gap_ctrl |= 0x8;
  91                 else
  92                         gap_ctrl &= ~0x8;
  93                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  94         }
  95 }
  96
  97 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
  98 {
  99         return mmc_gpio_get_ro(host->mmc);
 100 }
 101
 102 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
 103 {
 104         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 105         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 106         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 107         u32 misc_ctrl;
 108
 109         sdhci_reset(host, mask);
 110
 111         if (!(mask & SDHCI_RESET_ALL))
 112                 return;
 113
 114         misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 115         /* Erratum: Enable SDHCI spec v3.00 support */
 116         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
 117                 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
 118         /* Don't advertise UHS modes which aren't supported yet */
 119         if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
 120                 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
 121         if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
 122                 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
 123         if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
 124                 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
 125         sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 126 }
 127
 128 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
 129 {
 130         u32 ctrl;
 131
 132         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 133         if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
 134             (bus_width == MMC_BUS_WIDTH_8)) {
 135                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 136                 ctrl |= SDHCI_CTRL_8BITBUS;
 137         } else {
 138                 ctrl &= ~SDHCI_CTRL_8BITBUS;
 139                 if (bus_width == MMC_BUS_WIDTH_4)
 140                         ctrl |= SDHCI_CTRL_4BITBUS;
 141                 else
 142                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 143         }
 144         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 145 }
 146
 147 static const struct sdhci_ops tegra_sdhci_ops = {
 148         .get_ro     = tegra_sdhci_get_ro,
 149         .read_w     = tegra_sdhci_readw,
 150         .write_l    = tegra_sdhci_writel,
 151         .set_clock  = sdhci_set_clock,
 152         .set_bus_width = tegra_sdhci_set_bus_width,
 153         .reset      = tegra_sdhci_reset,
 154         .set_uhs_signaling = sdhci_set_uhs_signaling,
 155         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 156 };
 157
 158 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
 159         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 160                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 161                   SDHCI_QUIRK_NO_HISPD_BIT |
 162                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 163                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 164         .ops  = &tegra_sdhci_ops,
 165 };
 166
 167 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
 168         .pdata = &sdhci_tegra20_pdata,
 169         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
 170                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
 171 };
 172
 173 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
 174         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 175                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 176                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 177                   SDHCI_QUIRK_NO_HISPD_BIT |
 178                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 179                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 180         .ops  = &tegra_sdhci_ops,
 181 };
 182
 183 static struct sdhci_tegra_soc_data soc_data_tegra30 = {
 184         .pdata = &sdhci_tegra30_pdata,
 185         .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
 186                     NVQUIRK_DISABLE_SDR50 |
 187                     NVQUIRK_DISABLE_SDR104,
 188 };
 189
 190 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
 191         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 192                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 193                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 194                   SDHCI_QUIRK_NO_HISPD_BIT |
 195                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
 196                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 197         .ops  = &tegra_sdhci_ops,
 198 };
 199
 200 static struct sdhci_tegra_soc_data soc_data_tegra114 = {
 201         .pdata = &sdhci_tegra114_pdata,
 202         .nvquirks = NVQUIRK_DISABLE_SDR50 |
 203                     NVQUIRK_DISABLE_DDR50 |
 204                     NVQUIRK_DISABLE_SDR104,
 205 };
 206
 207 static const struct of_device_id sdhci_tegra_dt_match[] = {
 208         { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
 209         { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
 210         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
 211         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
 212         {}
 213 };
 214 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
 215
 216 static int sdhci_tegra_parse_dt(struct device *dev)
 217 {
 218         struct device_node *np = dev->of_node;
 219         struct sdhci_host *host = dev_get_drvdata(dev);
 220         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 221         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 222
 223         tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
 224         return mmc_of_parse(host->mmc);
 225 }
 226
 227 static int sdhci_tegra_probe(struct platform_device *pdev)
 228 {
 229         const struct of_device_id *match;
 230         const struct sdhci_tegra_soc_data *soc_data;
 231         struct sdhci_host *host;
 232         struct sdhci_pltfm_host *pltfm_host;
 233         struct sdhci_tegra *tegra_host;
 234         struct clk *clk;
 235         int rc;
 236
 237         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
 238         if (!match)
 239                 return -EINVAL;
 240         soc_data = match->data;
 241
 242         host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
 243         if (IS_ERR(host))
 244                 return PTR_ERR(host);
 245         pltfm_host = sdhci_priv(host);
 246
 247         tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
 248         if (!tegra_host) {
 249                 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
 250                 rc = -ENOMEM;
 251                 goto err_alloc_tegra_host;
 252         }
 253         tegra_host->soc_data = soc_data;
 254         pltfm_host->priv = tegra_host;
 255
 256         rc = sdhci_tegra_parse_dt(&pdev->dev);
 257         if (rc)
 258                 goto err_parse_dt;
 259
 260         if (gpio_is_valid(tegra_host->power_gpio)) {
 261                 rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
 262                 if (rc) {
 263                         dev_err(mmc_dev(host->mmc),
 264                                 "failed to allocate power gpio\n");
 265                         goto err_power_req;
 266                 }
 267                 gpio_direction_output(tegra_host->power_gpio, 1);
 268         }
 269
 270         clk = clk_get(mmc_dev(host->mmc), NULL);
 271         if (IS_ERR(clk)) {
 272                 dev_err(mmc_dev(host->mmc), "clk err\n");
 273                 rc = PTR_ERR(clk);
 274                 goto err_clk_get;
 275         }
 276         clk_prepare_enable(clk);
 277         pltfm_host->clk = clk;
 278
 279         rc = sdhci_add_host(host);
 280         if (rc)
 281                 goto err_add_host;
 282
 283         return 0;
 284
 285 err_add_host:
 286         clk_disable_unprepare(pltfm_host->clk);
 287         clk_put(pltfm_host->clk);
 288 err_clk_get:
 289         if (gpio_is_valid(tegra_host->power_gpio))
 290                 gpio_free(tegra_host->power_gpio);
 291 err_power_req:
 292 err_parse_dt:
 293 err_alloc_tegra_host:
 294         sdhci_pltfm_free(pdev);
 295         return rc;
 296 }
 297
 298 static int sdhci_tegra_remove(struct platform_device *pdev)
 299 {
 300         struct sdhci_host *host = platform_get_drvdata(pdev);
 301         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 302         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 303         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
 304
 305         sdhci_remove_host(host, dead);
 306
 307         if (gpio_is_valid(tegra_host->power_gpio))
 308                 gpio_free(tegra_host->power_gpio);
 309
 310         clk_disable_unprepare(pltfm_host->clk);
 311         clk_put(pltfm_host->clk);
 312
 313         sdhci_pltfm_free(pdev);
 314
 315         return 0;
 316 }
 317
 318 static struct platform_driver sdhci_tegra_driver = {
 319         .driver         = {
 320                 .name   = "sdhci-tegra",
 321                 .of_match_table = sdhci_tegra_dt_match,
 322                 .pm     = SDHCI_PLTFM_PMOPS,
 323         },
 324         .probe          = sdhci_tegra_probe,
 325         .remove         = sdhci_tegra_remove,
 326 };
 327
 328 module_platform_driver(sdhci_tegra_driver);
 329
 330 MODULE_DESCRIPTION("SDHCI driver for Tegra");
 331 MODULE_AUTHOR("Google, Inc.");
 332 MODULE_LICENSE("GPL v2");