drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  * Header file for Host Controller registers and I/O accessors.
   5  *
   6  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or (at
  11  * your option) any later version.
  12  */
  13 #ifndef __SDHCI_HW_H
  14 #define __SDHCI_HW_H
  15
  16 #include <linux/scatterlist.h>
  17 #include <linux/compiler.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20
  21 #include <linux/mmc/sdhci.h>
  22
  23 /*
  24  * Controller registers
  25  */
  26
  27 #define SDHCI_DMA_ADDRESS       0x00
  28 #define SDHCI_ARGUMENT2         SDHCI_DMA_ADDRESS
  29
  30 #define SDHCI_BLOCK_SIZE        0x04
  31 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  32
  33 #define SDHCI_BLOCK_COUNT       0x06
  34
  35 #define SDHCI_ARGUMENT          0x08
  36
  37 #define SDHCI_TRANSFER_MODE     0x0C
  38 #define  SDHCI_TRNS_DMA         0x01
  39 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  40 #define  SDHCI_TRNS_AUTO_CMD12  0x04
  41 #define  SDHCI_TRNS_AUTO_CMD23  0x08
  42 #define  SDHCI_TRNS_READ        0x10
  43 #define  SDHCI_TRNS_MULTI       0x20
  44
  45 #define SDHCI_COMMAND           0x0E
  46 #define  SDHCI_CMD_RESP_MASK    0x03
  47 #define  SDHCI_CMD_CRC          0x08
  48 #define  SDHCI_CMD_INDEX        0x10
  49 #define  SDHCI_CMD_DATA         0x20
  50 #define  SDHCI_CMD_ABORTCMD     0xC0
  51
  52 #define  SDHCI_CMD_RESP_NONE    0x00
  53 #define  SDHCI_CMD_RESP_LONG    0x01
  54 #define  SDHCI_CMD_RESP_SHORT   0x02
  55 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  56
  57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  59
  60 #define SDHCI_RESPONSE          0x10
  61
  62 #define SDHCI_BUFFER            0x20
  63
  64 #define SDHCI_PRESENT_STATE     0x24
  65 #define  SDHCI_CMD_INHIBIT      0x00000001
  66 #define  SDHCI_DATA_INHIBIT     0x00000002
  67 #define  SDHCI_DOING_WRITE      0x00000100
  68 #define  SDHCI_DOING_READ       0x00000200
  69 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  70 #define  SDHCI_DATA_AVAILABLE   0x00000800
  71 #define  SDHCI_CARD_PRESENT     0x00010000
  72 #define  SDHCI_WRITE_PROTECT    0x00080000
  73 #define  SDHCI_DATA_LVL_MASK    0x00F00000
  74 #define   SDHCI_DATA_LVL_SHIFT  20
  75 #define   SDHCI_DATA_0_LVL_MASK 0x00100000
  76
  77 #define SDHCI_HOST_CONTROL      0x28
  78 #define  SDHCI_CTRL_LED         0x01
  79 #define  SDHCI_CTRL_4BITBUS     0x02
  80 #define  SDHCI_CTRL_HISPD       0x04
  81 #define  SDHCI_CTRL_DMA_MASK    0x18
  82 #define   SDHCI_CTRL_SDMA       0x00
  83 #define   SDHCI_CTRL_ADMA1      0x08
  84 #define   SDHCI_CTRL_ADMA32     0x10
  85 #define   SDHCI_CTRL_ADMA64     0x18
  86 #define   SDHCI_CTRL_8BITBUS    0x20
  87
  88 #define SDHCI_POWER_CONTROL     0x29
  89 #define  SDHCI_POWER_ON         0x01
  90 #define  SDHCI_POWER_180        0x0A
  91 #define  SDHCI_POWER_300        0x0C
  92 #define  SDHCI_POWER_330        0x0E
  93
  94 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  95
  96 #define SDHCI_WAKE_UP_CONTROL   0x2B
  97 #define  SDHCI_WAKE_ON_INT      0x01
  98 #define  SDHCI_WAKE_ON_INSERT   0x02
  99 #define  SDHCI_WAKE_ON_REMOVE   0x04
 100
 101 #define SDHCI_CLOCK_CONTROL     0x2C
 102 #define  SDHCI_DIVIDER_SHIFT    8
 103 #define  SDHCI_DIVIDER_HI_SHIFT 6
 104 #define  SDHCI_DIV_MASK 0xFF
 105 #define  SDHCI_DIV_MASK_LEN     8
 106 #define  SDHCI_DIV_HI_MASK      0x300
 107 #define  SDHCI_PROG_CLOCK_MODE  0x0020
 108 #define  SDHCI_CLOCK_CARD_EN    0x0004
 109 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 110 #define  SDHCI_CLOCK_INT_EN     0x0001
 111
 112 #define SDHCI_TIMEOUT_CONTROL   0x2E
 113
 114 #define SDHCI_SOFTWARE_RESET    0x2F
 115 #define  SDHCI_RESET_ALL        0x01
 116 #define  SDHCI_RESET_CMD        0x02
 117 #define  SDHCI_RESET_DATA       0x04
 118
 119 #define SDHCI_INT_STATUS        0x30
 120 #define SDHCI_INT_ENABLE        0x34
 121 #define SDHCI_SIGNAL_ENABLE     0x38
 122 #define  SDHCI_INT_RESPONSE     0x00000001
 123 #define  SDHCI_INT_DATA_END     0x00000002
 124 #define  SDHCI_INT_BLK_GAP      0x00000004
 125 #define  SDHCI_INT_DMA_END      0x00000008
 126 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 127 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 128 #define  SDHCI_INT_CARD_INSERT  0x00000040
 129 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 130 #define  SDHCI_INT_CARD_INT     0x00000100
 131 #define  SDHCI_INT_ERROR        0x00008000
 132 #define  SDHCI_INT_TIMEOUT      0x00010000
 133 #define  SDHCI_INT_CRC          0x00020000
 134 #define  SDHCI_INT_END_BIT      0x00040000
 135 #define  SDHCI_INT_INDEX        0x00080000
 136 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 137 #define  SDHCI_INT_DATA_CRC     0x00200000
 138 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 139 #define  SDHCI_INT_BUS_POWER    0x00800000
 140 #define  SDHCI_INT_ACMD12ERR    0x01000000
 141 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 142
 143 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 144 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 145
 146 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 147                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 148 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 149                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 150                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 151                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
 152                 SDHCI_INT_BLK_GAP)
 153 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 154
 155 #define SDHCI_ACMD12_ERR        0x3C
 156
 157 #define SDHCI_HOST_CONTROL2             0x3E
 158 #define  SDHCI_CTRL_UHS_MASK            0x0007
 159 #define   SDHCI_CTRL_UHS_SDR12          0x0000
 160 #define   SDHCI_CTRL_UHS_SDR25          0x0001
 161 #define   SDHCI_CTRL_UHS_SDR50          0x0002
 162 #define   SDHCI_CTRL_UHS_SDR104         0x0003
 163 #define   SDHCI_CTRL_UHS_DDR50          0x0004
 164 #define   SDHCI_CTRL_HS400              0x0005 /* Non-standard */
 165 #define  SDHCI_CTRL_VDD_180             0x0008
 166 #define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
 167 #define   SDHCI_CTRL_DRV_TYPE_B         0x0000
 168 #define   SDHCI_CTRL_DRV_TYPE_A         0x0010
 169 #define   SDHCI_CTRL_DRV_TYPE_C         0x0020
 170 #define   SDHCI_CTRL_DRV_TYPE_D         0x0030
 171 #define  SDHCI_CTRL_EXEC_TUNING         0x0040
 172 #define  SDHCI_CTRL_TUNED_CLK           0x0080
 173 #define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 174
 175 #define SDHCI_CAPABILITIES      0x40
 176 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 177 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 178 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 179 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 180 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 181 #define  SDHCI_CLOCK_BASE_SHIFT 8
 182 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 183 #define  SDHCI_MAX_BLOCK_SHIFT  16
 184 #define  SDHCI_CAN_DO_8BIT      0x00040000
 185 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 186 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 187 #define  SDHCI_CAN_DO_HISPD     0x00200000
 188 #define  SDHCI_CAN_DO_SDMA      0x00400000
 189 #define  SDHCI_CAN_VDD_330      0x01000000
 190 #define  SDHCI_CAN_VDD_300      0x02000000
 191 #define  SDHCI_CAN_VDD_180      0x04000000
 192 #define  SDHCI_CAN_64BIT        0x10000000
 193
 194 #define  SDHCI_SUPPORT_SDR50    0x00000001
 195 #define  SDHCI_SUPPORT_SDR104   0x00000002
 196 #define  SDHCI_SUPPORT_DDR50    0x00000004
 197 #define  SDHCI_DRIVER_TYPE_A    0x00000010
 198 #define  SDHCI_DRIVER_TYPE_C    0x00000020
 199 #define  SDHCI_DRIVER_TYPE_D    0x00000040
 200 #define  SDHCI_RETUNING_TIMER_COUNT_MASK        0x00000F00
 201 #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT       8
 202 #define  SDHCI_USE_SDR50_TUNING                 0x00002000
 203 #define  SDHCI_RETUNING_MODE_MASK               0x0000C000
 204 #define  SDHCI_RETUNING_MODE_SHIFT              14
 205 #define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
 206 #define  SDHCI_CLOCK_MUL_SHIFT  16
 207 #define  SDHCI_SUPPORT_HS400    0x80000000 /* Non-standard */
 208
 209 #define SDHCI_CAPABILITIES_1    0x44
 210
 211 #define SDHCI_MAX_CURRENT               0x48
 212 #define  SDHCI_MAX_CURRENT_LIMIT        0xFF
 213 #define  SDHCI_MAX_CURRENT_330_MASK     0x0000FF
 214 #define  SDHCI_MAX_CURRENT_330_SHIFT    0
 215 #define  SDHCI_MAX_CURRENT_300_MASK     0x00FF00
 216 #define  SDHCI_MAX_CURRENT_300_SHIFT    8
 217 #define  SDHCI_MAX_CURRENT_180_MASK     0xFF0000
 218 #define  SDHCI_MAX_CURRENT_180_SHIFT    16
 219 #define   SDHCI_MAX_CURRENT_MULTIPLIER  4
 220
 221 /* 4C-4F reserved for more max current */
 222
 223 #define SDHCI_SET_ACMD12_ERROR  0x50
 224 #define SDHCI_SET_INT_ERROR     0x52
 225
 226 #define SDHCI_ADMA_ERROR        0x54
 227
 228 /* 55-57 reserved */
 229
 230 #define SDHCI_ADMA_ADDRESS      0x58
 231 #define SDHCI_ADMA_ADDRESS_HI   0x5C
 232
 233 /* 60-FB reserved */
 234
 235 #define SDHCI_PRESET_FOR_SDR12 0x66
 236 #define SDHCI_PRESET_FOR_SDR25 0x68
 237 #define SDHCI_PRESET_FOR_SDR50 0x6A
 238 #define SDHCI_PRESET_FOR_SDR104        0x6C
 239 #define SDHCI_PRESET_FOR_DDR50 0x6E
 240 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
 241 #define SDHCI_PRESET_DRV_MASK  0xC000
 242 #define SDHCI_PRESET_DRV_SHIFT  14
 243 #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
 244 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT   10
 245 #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
 246 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT   0
 247
 248 #define SDHCI_SLOT_INT_STATUS   0xFC
 249
 250 #define SDHCI_HOST_VERSION      0xFE
 251 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 252 #define  SDHCI_VENDOR_VER_SHIFT 8
 253 #define  SDHCI_SPEC_VER_MASK    0x00FF
 254 #define  SDHCI_SPEC_VER_SHIFT   0
 255 #define   SDHCI_SPEC_100        0
 256 #define   SDHCI_SPEC_200        1
 257 #define   SDHCI_SPEC_300        2
 258
 259 /*
 260  * End of controller registers.
 261  */
 262
 263 #define SDHCI_MAX_DIV_SPEC_200  256
 264 #define SDHCI_MAX_DIV_SPEC_300  2046
 265
 266 /*
 267  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 268  */
 269 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
 270 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
 271
 272 /* ADMA2 32-bit DMA descriptor size */
 273 #define SDHCI_ADMA2_32_DESC_SZ  8
 274
 275 /* ADMA2 32-bit DMA alignment */
 276 #define SDHCI_ADMA2_32_ALIGN    4
 277
 278 /* ADMA2 32-bit descriptor */
 279 struct sdhci_adma2_32_desc {
 280         __le16  cmd;
 281         __le16  len;
 282         __le32  addr;
 283 }  __packed __aligned(SDHCI_ADMA2_32_ALIGN);
 284
 285 /* ADMA2 64-bit DMA descriptor size */
 286 #define SDHCI_ADMA2_64_DESC_SZ  12
 287
 288 /* ADMA2 64-bit DMA alignment */
 289 #define SDHCI_ADMA2_64_ALIGN    8
 290
 291 /*
 292  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
 293  * aligned.
 294  */
 295 struct sdhci_adma2_64_desc {
 296         __le16  cmd;
 297         __le16  len;
 298         __le32  addr_lo;
 299         __le32  addr_hi;
 300 }  __packed __aligned(4);
 301
 302 #define ADMA2_TRAN_VALID        0x21
 303 #define ADMA2_NOP_END_VALID     0x3
 304 #define ADMA2_END               0x2
 305
 306 /*
 307  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
 308  * 4KiB page size.
 309  */
 310 #define SDHCI_MAX_SEGS          128
 311
 312 struct sdhci_ops {
 313 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 314         u32             (*read_l)(struct sdhci_host *host, int reg);
 315         u16             (*read_w)(struct sdhci_host *host, int reg);
 316         u8              (*read_b)(struct sdhci_host *host, int reg);
 317         void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
 318         void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
 319         void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
 320 #endif
 321
 322         void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
 323
 324         int             (*enable_dma)(struct sdhci_host *host);
 325         unsigned int    (*get_max_clock)(struct sdhci_host *host);
 326         unsigned int    (*get_min_clock)(struct sdhci_host *host);
 327         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
 328         unsigned int    (*get_max_timeout_count)(struct sdhci_host *host);
 329         void            (*set_timeout)(struct sdhci_host *host,
 330                                        struct mmc_command *cmd);
 331         void            (*set_bus_width)(struct sdhci_host *host, int width);
 332         void (*platform_send_init_74_clocks)(struct sdhci_host *host,
 333                                              u8 power_mode);
 334         unsigned int    (*get_ro)(struct sdhci_host *host);
 335         void            (*reset)(struct sdhci_host *host, u8 mask);
 336         int     (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
 337         void    (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
 338         void    (*hw_reset)(struct sdhci_host *host);
 339         void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
 340         void    (*platform_init)(struct sdhci_host *host);
 341         void    (*card_event)(struct sdhci_host *host);
 342 };
 343
 344 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 345
 346 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 347 {
 348         if (unlikely(host->ops->write_l))
 349                 host->ops->write_l(host, val, reg);
 350         else
 351                 writel(val, host->ioaddr + reg);
 352 }
 353
 354 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 355 {
 356         if (unlikely(host->ops->write_w))
 357                 host->ops->write_w(host, val, reg);
 358         else
 359                 writew(val, host->ioaddr + reg);
 360 }
 361
 362 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 363 {
 364         if (unlikely(host->ops->write_b))
 365                 host->ops->write_b(host, val, reg);
 366         else
 367                 writeb(val, host->ioaddr + reg);
 368 }
 369
 370 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 371 {
 372         if (unlikely(host->ops->read_l))
 373                 return host->ops->read_l(host, reg);
 374         else
 375                 return readl(host->ioaddr + reg);
 376 }
 377
 378 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 379 {
 380         if (unlikely(host->ops->read_w))
 381                 return host->ops->read_w(host, reg);
 382         else
 383                 return readw(host->ioaddr + reg);
 384 }
 385
 386 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 387 {
 388         if (unlikely(host->ops->read_b))
 389                 return host->ops->read_b(host, reg);
 390         else
 391                 return readb(host->ioaddr + reg);
 392 }
 393
 394 #else
 395
 396 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 397 {
 398         writel(val, host->ioaddr + reg);
 399 }
 400
 401 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 402 {
 403         writew(val, host->ioaddr + reg);
 404 }
 405
 406 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 407 {
 408         writeb(val, host->ioaddr + reg);
 409 }
 410
 411 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 412 {
 413         return readl(host->ioaddr + reg);
 414 }
 415
 416 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 417 {
 418         return readw(host->ioaddr + reg);
 419 }
 420
 421 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 422 {
 423         return readb(host->ioaddr + reg);
 424 }
 425
 426 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 427
 428 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 429         size_t priv_size);
 430 extern void sdhci_free_host(struct sdhci_host *host);
 431
 432 static inline void *sdhci_priv(struct sdhci_host *host)
 433 {
 434         return (void *)host->private;
 435 }
 436
 437 extern void sdhci_card_detect(struct sdhci_host *host);
 438 extern int sdhci_add_host(struct sdhci_host *host);
 439 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 440 extern void sdhci_send_command(struct sdhci_host *host,
 441                                 struct mmc_command *cmd);
 442
 443 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
 444 {
 445         return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
 446 }
 447
 448 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
 449 void sdhci_set_bus_width(struct sdhci_host *host, int width);
 450 void sdhci_reset(struct sdhci_host *host, u8 mask);
 451 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 452
 453 #ifdef CONFIG_PM
 454 extern int sdhci_suspend_host(struct sdhci_host *host);
 455 extern int sdhci_resume_host(struct sdhci_host *host);
 456 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
 457 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
 458 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
 459 #endif
 460
 461 #endif /* __SDHCI_HW_H */