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m68k/defconfig: Enable automounting of devtmpfs at /dev
[linux/fpc-iii.git] / drivers / mmc / host / sunxi-mmc.c
blob15cb8b7ffc3418a19770f97cf388c59ad440c0f4
1 /*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/device.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22
23 #include <linux/clk.h>
24 #include <linux/clk/sunxi.h>
25
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/spinlock.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 #include <linux/reset.h>
33
34 #include <linux/of_address.h>
35 #include <linux/of_gpio.h>
36 #include <linux/of_platform.h>
37
38 #include <linux/mmc/host.h>
39 #include <linux/mmc/sd.h>
40 #include <linux/mmc/sdio.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/core.h>
43 #include <linux/mmc/card.h>
44 #include <linux/mmc/slot-gpio.h>
45
46 /* register offset definitions */
47 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
48 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
49 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
50 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
51 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
52 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
53 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
54 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
55 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
56 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
57 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
58 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
59 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
60 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
61 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
62 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
63 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
64 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
65 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
66 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
67 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
68 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
69 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
70 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
71 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
72 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
73 #define SDXC_REG_CHDA (0x90)
74 #define SDXC_REG_CBDA (0x94)
75
76 #define mmc_readl(host, reg) \
77 readl((host)->reg_base + SDXC_##reg)
78 #define mmc_writel(host, reg, value) \
79 writel((value), (host)->reg_base + SDXC_##reg)
80
81 /* global control register bits */
82 #define SDXC_SOFT_RESET BIT(0)
83 #define SDXC_FIFO_RESET BIT(1)
84 #define SDXC_DMA_RESET BIT(2)
85 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
86 #define SDXC_DMA_ENABLE_BIT BIT(5)
87 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
88 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
89 #define SDXC_DDR_MODE BIT(10)
90 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
91 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
92 #define SDXC_ACCESS_BY_AHB BIT(31)
93 #define SDXC_ACCESS_BY_DMA (0 << 31)
94 #define SDXC_HARDWARE_RESET \
95 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
96
97 /* clock control bits */
98 #define SDXC_CARD_CLOCK_ON BIT(16)
99 #define SDXC_LOW_POWER_ON BIT(17)
100
101 /* bus width */
102 #define SDXC_WIDTH1 0
103 #define SDXC_WIDTH4 1
104 #define SDXC_WIDTH8 2
105
106 /* smc command bits */
107 #define SDXC_RESP_EXPIRE BIT(6)
108 #define SDXC_LONG_RESPONSE BIT(7)
109 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
110 #define SDXC_DATA_EXPIRE BIT(9)
111 #define SDXC_WRITE BIT(10)
112 #define SDXC_SEQUENCE_MODE BIT(11)
113 #define SDXC_SEND_AUTO_STOP BIT(12)
114 #define SDXC_WAIT_PRE_OVER BIT(13)
115 #define SDXC_STOP_ABORT_CMD BIT(14)
116 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
117 #define SDXC_UPCLK_ONLY BIT(21)
118 #define SDXC_READ_CEATA_DEV BIT(22)
119 #define SDXC_CCS_EXPIRE BIT(23)
120 #define SDXC_ENABLE_BIT_BOOT BIT(24)
121 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
122 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
123 #define SDXC_BOOT_ABORT BIT(27)
124 #define SDXC_VOLTAGE_SWITCH BIT(28)
125 #define SDXC_USE_HOLD_REGISTER BIT(29)
126 #define SDXC_START BIT(31)
127
128 /* interrupt bits */
129 #define SDXC_RESP_ERROR BIT(1)
130 #define SDXC_COMMAND_DONE BIT(2)
131 #define SDXC_DATA_OVER BIT(3)
132 #define SDXC_TX_DATA_REQUEST BIT(4)
133 #define SDXC_RX_DATA_REQUEST BIT(5)
134 #define SDXC_RESP_CRC_ERROR BIT(6)
135 #define SDXC_DATA_CRC_ERROR BIT(7)
136 #define SDXC_RESP_TIMEOUT BIT(8)
137 #define SDXC_DATA_TIMEOUT BIT(9)
138 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
139 #define SDXC_FIFO_RUN_ERROR BIT(11)
140 #define SDXC_HARD_WARE_LOCKED BIT(12)
141 #define SDXC_START_BIT_ERROR BIT(13)
142 #define SDXC_AUTO_COMMAND_DONE BIT(14)
143 #define SDXC_END_BIT_ERROR BIT(15)
144 #define SDXC_SDIO_INTERRUPT BIT(16)
145 #define SDXC_CARD_INSERT BIT(30)
146 #define SDXC_CARD_REMOVE BIT(31)
147 #define SDXC_INTERRUPT_ERROR_BIT \
148 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
149 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
150 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
151 #define SDXC_INTERRUPT_DONE_BIT \
152 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
153 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
154
155 /* status */
156 #define SDXC_RXWL_FLAG BIT(0)
157 #define SDXC_TXWL_FLAG BIT(1)
158 #define SDXC_FIFO_EMPTY BIT(2)
159 #define SDXC_FIFO_FULL BIT(3)
160 #define SDXC_CARD_PRESENT BIT(8)
161 #define SDXC_CARD_DATA_BUSY BIT(9)
162 #define SDXC_DATA_FSM_BUSY BIT(10)
163 #define SDXC_DMA_REQUEST BIT(31)
164 #define SDXC_FIFO_SIZE 16
165
166 /* Function select */
167 #define SDXC_CEATA_ON (0xceaa << 16)
168 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
169 #define SDXC_SDIO_READ_WAIT BIT(1)
170 #define SDXC_ABORT_READ_DATA BIT(2)
171 #define SDXC_SEND_CCSD BIT(8)
172 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
173 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
174
175 /* IDMA controller bus mod bit field */
176 #define SDXC_IDMAC_SOFT_RESET BIT(0)
177 #define SDXC_IDMAC_FIX_BURST BIT(1)
178 #define SDXC_IDMAC_IDMA_ON BIT(7)
179 #define SDXC_IDMAC_REFETCH_DES BIT(31)
180
181 /* IDMA status bit field */
182 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
183 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
184 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
185 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
186 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
187 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
188 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
189 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
190 #define SDXC_IDMAC_IDLE (0 << 13)
191 #define SDXC_IDMAC_SUSPEND (1 << 13)
192 #define SDXC_IDMAC_DESC_READ (2 << 13)
193 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
194 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
195 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
196 #define SDXC_IDMAC_READ (6 << 13)
197 #define SDXC_IDMAC_WRITE (7 << 13)
198 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
199
200 /*
201 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
202 * Bits 0-12: buf1 size
203 * Bits 13-25: buf2 size
204 * Bits 26-31: not used
205 * Since we only ever set buf1 size, we can simply store it directly.
206 */
207 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
208 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
209 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
210 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
211 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
212 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
213 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
214
215 struct sunxi_idma_des {
216 u32 config;
217 u32 buf_size;
218 u32 buf_addr_ptr1;
219 u32 buf_addr_ptr2;
220 };
221
222 struct sunxi_mmc_host {
223 struct mmc_host *mmc;
224 struct reset_control *reset;
225
226 /* IO mapping base */
227 void __iomem *reg_base;
228
229 /* clock management */
230 struct clk *clk_ahb;
231 struct clk *clk_mmc;
232
233 /* irq */
234 spinlock_t lock;
235 int irq;
236 u32 int_sum;
237 u32 sdio_imask;
238
239 /* dma */
240 u32 idma_des_size_bits;
241 dma_addr_t sg_dma;
242 void *sg_cpu;
243 bool wait_dma;
244
245 struct mmc_request *mrq;
246 struct mmc_request *manual_stop_mrq;
247 int ferror;
248 };
249
250 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
251 {
252 unsigned long expire = jiffies + msecs_to_jiffies(250);
253 u32 rval;
254
255 mmc_writel(host, REG_CMDR, SDXC_HARDWARE_RESET);
256 do {
257 rval = mmc_readl(host, REG_GCTRL);
258 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
259
260 if (rval & SDXC_HARDWARE_RESET) {
261 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
262 return -EIO;
263 }
264
265 return 0;
266 }
267
268 static int sunxi_mmc_init_host(struct mmc_host *mmc)
269 {
270 u32 rval;
271 struct sunxi_mmc_host *host = mmc_priv(mmc);
272
273 if (sunxi_mmc_reset_host(host))
274 return -EIO;
275
276 mmc_writel(host, REG_FTRGL, 0x20070008);
277 mmc_writel(host, REG_TMOUT, 0xffffffff);
278 mmc_writel(host, REG_IMASK, host->sdio_imask);
279 mmc_writel(host, REG_RINTR, 0xffffffff);
280 mmc_writel(host, REG_DBGC, 0xdeb);
281 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
282 mmc_writel(host, REG_DLBA, host->sg_dma);
283
284 rval = mmc_readl(host, REG_GCTRL);
285 rval |= SDXC_INTERRUPT_ENABLE_BIT;
286 rval &= ~SDXC_ACCESS_DONE_DIRECT;
287 mmc_writel(host, REG_GCTRL, rval);
288
289 return 0;
290 }
291
292 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
293 struct mmc_data *data)
294 {
295 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
296 struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
297 int i, max_len = (1 << host->idma_des_size_bits);
298
299 for (i = 0; i < data->sg_len; i++) {
300 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
301 SDXC_IDMAC_DES0_DIC;
302
303 if (data->sg[i].length == max_len)
304 pdes[i].buf_size = 0; /* 0 == max_len */
305 else
306 pdes[i].buf_size = data->sg[i].length;
307
308 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
309 pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
310 }
311
312 pdes[0].config |= SDXC_IDMAC_DES0_FD;
313 pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
314
315 /*
316 * Avoid the io-store starting the idmac hitting io-mem before the
317 * descriptors hit the main-mem.
318 */
319 wmb();
320 }
321
322 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
323 {
324 if (data->flags & MMC_DATA_WRITE)
325 return DMA_TO_DEVICE;
326 else
327 return DMA_FROM_DEVICE;
328 }
329
330 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
331 struct mmc_data *data)
332 {
333 u32 i, dma_len;
334 struct scatterlist *sg;
335
336 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
337 sunxi_mmc_get_dma_dir(data));
338 if (dma_len == 0) {
339 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
340 return -ENOMEM;
341 }
342
343 for_each_sg(data->sg, sg, data->sg_len, i) {
344 if (sg->offset & 3 || sg->length & 3) {
345 dev_err(mmc_dev(host->mmc),
346 "unaligned scatterlist: os %x length %d\n",
347 sg->offset, sg->length);
348 return -EINVAL;
349 }
350 }
351
352 return 0;
353 }
354
355 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
356 struct mmc_data *data)
357 {
358 u32 rval;
359
360 sunxi_mmc_init_idma_des(host, data);
361
362 rval = mmc_readl(host, REG_GCTRL);
363 rval |= SDXC_DMA_ENABLE_BIT;
364 mmc_writel(host, REG_GCTRL, rval);
365 rval |= SDXC_DMA_RESET;
366 mmc_writel(host, REG_GCTRL, rval);
367
368 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
369
370 if (!(data->flags & MMC_DATA_WRITE))
371 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
372
373 mmc_writel(host, REG_DMAC,
374 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
375 }
376
377 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
378 struct mmc_request *req)
379 {
380 u32 arg, cmd_val, ri;
381 unsigned long expire = jiffies + msecs_to_jiffies(1000);
382
383 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
384 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
385
386 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
387 cmd_val |= SD_IO_RW_DIRECT;
388 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
389 ((req->cmd->arg >> 28) & 0x7);
390 } else {
391 cmd_val |= MMC_STOP_TRANSMISSION;
392 arg = 0;
393 }
394
395 mmc_writel(host, REG_CARG, arg);
396 mmc_writel(host, REG_CMDR, cmd_val);
397
398 do {
399 ri = mmc_readl(host, REG_RINTR);
400 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
401 time_before(jiffies, expire));
402
403 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
404 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
405 if (req->stop)
406 req->stop->resp[0] = -ETIMEDOUT;
407 } else {
408 if (req->stop)
409 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
410 }
411
412 mmc_writel(host, REG_RINTR, 0xffff);
413 }
414
415 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
416 {
417 struct mmc_command *cmd = host->mrq->cmd;
418 struct mmc_data *data = host->mrq->data;
419
420 /* For some cmds timeout is normal with sd/mmc cards */
421 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
422 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
423 cmd->opcode == SD_IO_RW_DIRECT))
424 return;
425
426 dev_err(mmc_dev(host->mmc),
427 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
428 host->mmc->index, cmd->opcode,
429 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
430 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
431 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
432 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
433 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
434 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
435 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
436 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
437 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
438 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
439 );
440 }
441
442 /* Called in interrupt context! */
443 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
444 {
445 struct mmc_request *mrq = host->mrq;
446 struct mmc_data *data = mrq->data;
447 u32 rval;
448
449 mmc_writel(host, REG_IMASK, host->sdio_imask);
450 mmc_writel(host, REG_IDIE, 0);
451
452 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
453 sunxi_mmc_dump_errinfo(host);
454 mrq->cmd->error = -ETIMEDOUT;
455
456 if (data) {
457 data->error = -ETIMEDOUT;
458 host->manual_stop_mrq = mrq;
459 }
460
461 if (mrq->stop)
462 mrq->stop->error = -ETIMEDOUT;
463 } else {
464 if (mrq->cmd->flags & MMC_RSP_136) {
465 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
466 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
467 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
468 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
469 } else {
470 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
471 }
472
473 if (data)
474 data->bytes_xfered = data->blocks * data->blksz;
475 }
476
477 if (data) {
478 mmc_writel(host, REG_IDST, 0x337);
479 mmc_writel(host, REG_DMAC, 0);
480 rval = mmc_readl(host, REG_GCTRL);
481 rval |= SDXC_DMA_RESET;
482 mmc_writel(host, REG_GCTRL, rval);
483 rval &= ~SDXC_DMA_ENABLE_BIT;
484 mmc_writel(host, REG_GCTRL, rval);
485 rval |= SDXC_FIFO_RESET;
486 mmc_writel(host, REG_GCTRL, rval);
487 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
488 sunxi_mmc_get_dma_dir(data));
489 }
490
491 mmc_writel(host, REG_RINTR, 0xffff);
492
493 host->mrq = NULL;
494 host->int_sum = 0;
495 host->wait_dma = false;
496
497 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
498 }
499
500 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
501 {
502 struct sunxi_mmc_host *host = dev_id;
503 struct mmc_request *mrq;
504 u32 msk_int, idma_int;
505 bool finalize = false;
506 bool sdio_int = false;
507 irqreturn_t ret = IRQ_HANDLED;
508
509 spin_lock(&host->lock);
510
511 idma_int = mmc_readl(host, REG_IDST);
512 msk_int = mmc_readl(host, REG_MISTA);
513
514 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
515 host->mrq, msk_int, idma_int);
516
517 mrq = host->mrq;
518 if (mrq) {
519 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
520 host->wait_dma = false;
521
522 host->int_sum |= msk_int;
523
524 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
525 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
526 !(host->int_sum & SDXC_COMMAND_DONE))
527 mmc_writel(host, REG_IMASK,
528 host->sdio_imask | SDXC_COMMAND_DONE);
529 /* Don't wait for dma on error */
530 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
531 finalize = true;
532 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
533 !host->wait_dma)
534 finalize = true;
535 }
536
537 if (msk_int & SDXC_SDIO_INTERRUPT)
538 sdio_int = true;
539
540 mmc_writel(host, REG_RINTR, msk_int);
541 mmc_writel(host, REG_IDST, idma_int);
542
543 if (finalize)
544 ret = sunxi_mmc_finalize_request(host);
545
546 spin_unlock(&host->lock);
547
548 if (finalize && ret == IRQ_HANDLED)
549 mmc_request_done(host->mmc, mrq);
550
551 if (sdio_int)
552 mmc_signal_sdio_irq(host->mmc);
553
554 return ret;
555 }
556
557 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
558 {
559 struct sunxi_mmc_host *host = dev_id;
560 struct mmc_request *mrq;
561 unsigned long iflags;
562
563 spin_lock_irqsave(&host->lock, iflags);
564 mrq = host->manual_stop_mrq;
565 spin_unlock_irqrestore(&host->lock, iflags);
566
567 if (!mrq) {
568 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
569 return IRQ_HANDLED;
570 }
571
572 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
573 sunxi_mmc_send_manual_stop(host, mrq);
574
575 spin_lock_irqsave(&host->lock, iflags);
576 host->manual_stop_mrq = NULL;
577 spin_unlock_irqrestore(&host->lock, iflags);
578
579 mmc_request_done(host->mmc, mrq);
580
581 return IRQ_HANDLED;
582 }
583
584 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
585 {
586 unsigned long expire = jiffies + msecs_to_jiffies(250);
587 u32 rval;
588
589 rval = mmc_readl(host, REG_CLKCR);
590 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
591
592 if (oclk_en)
593 rval |= SDXC_CARD_CLOCK_ON;
594
595 mmc_writel(host, REG_CLKCR, rval);
596
597 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
598 mmc_writel(host, REG_CMDR, rval);
599
600 do {
601 rval = mmc_readl(host, REG_CMDR);
602 } while (time_before(jiffies, expire) && (rval & SDXC_START));
603
604 /* clear irq status bits set by the command */
605 mmc_writel(host, REG_RINTR,
606 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
607
608 if (rval & SDXC_START) {
609 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
610 return -EIO;
611 }
612
613 return 0;
614 }
615
616 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
617 struct mmc_ios *ios)
618 {
619 u32 rate, oclk_dly, rval, sclk_dly, src_clk;
620 int ret;
621
622 rate = clk_round_rate(host->clk_mmc, ios->clock);
623 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
624 ios->clock, rate);
625
626 /* setting clock rate */
627 ret = clk_set_rate(host->clk_mmc, rate);
628 if (ret) {
629 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
630 rate, ret);
631 return ret;
632 }
633
634 ret = sunxi_mmc_oclk_onoff(host, 0);
635 if (ret)
636 return ret;
637
638 /* clear internal divider */
639 rval = mmc_readl(host, REG_CLKCR);
640 rval &= ~0xff;
641 mmc_writel(host, REG_CLKCR, rval);
642
643 /* determine delays */
644 if (rate <= 400000) {
645 oclk_dly = 0;
646 sclk_dly = 7;
647 } else if (rate <= 25000000) {
648 oclk_dly = 0;
649 sclk_dly = 5;
650 } else if (rate <= 50000000) {
651 if (ios->timing == MMC_TIMING_UHS_DDR50) {
652 oclk_dly = 2;
653 sclk_dly = 4;
654 } else {
655 oclk_dly = 3;
656 sclk_dly = 5;
657 }
658 } else {
659 /* rate > 50000000 */
660 oclk_dly = 2;
661 sclk_dly = 4;
662 }
663
664 src_clk = clk_get_rate(clk_get_parent(host->clk_mmc));
665 if (src_clk >= 300000000 && src_clk <= 400000000) {
666 if (oclk_dly)
667 oclk_dly--;
668 if (sclk_dly)
669 sclk_dly--;
670 }
671
672 clk_sunxi_mmc_phase_control(host->clk_mmc, sclk_dly, oclk_dly);
673
674 return sunxi_mmc_oclk_onoff(host, 1);
675 }
676
677 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
678 {
679 struct sunxi_mmc_host *host = mmc_priv(mmc);
680 u32 rval;
681
682 /* Set the power state */
683 switch (ios->power_mode) {
684 case MMC_POWER_ON:
685 break;
686
687 case MMC_POWER_UP:
688 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
689
690 host->ferror = sunxi_mmc_init_host(mmc);
691 if (host->ferror)
692 return;
693
694 dev_dbg(mmc_dev(mmc), "power on!\n");
695 break;
696
697 case MMC_POWER_OFF:
698 dev_dbg(mmc_dev(mmc), "power off!\n");
699 sunxi_mmc_reset_host(host);
700 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
701 break;
702 }
703
704 /* set bus width */
705 switch (ios->bus_width) {
706 case MMC_BUS_WIDTH_1:
707 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
708 break;
709 case MMC_BUS_WIDTH_4:
710 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
711 break;
712 case MMC_BUS_WIDTH_8:
713 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
714 break;
715 }
716
717 /* set ddr mode */
718 rval = mmc_readl(host, REG_GCTRL);
719 if (ios->timing == MMC_TIMING_UHS_DDR50)
720 rval |= SDXC_DDR_MODE;
721 else
722 rval &= ~SDXC_DDR_MODE;
723 mmc_writel(host, REG_GCTRL, rval);
724
725 /* set up clock */
726 if (ios->clock && ios->power_mode) {
727 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
728 /* Android code had a usleep_range(50000, 55000); here */
729 }
730 }
731
732 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
733 {
734 struct sunxi_mmc_host *host = mmc_priv(mmc);
735 unsigned long flags;
736 u32 imask;
737
738 spin_lock_irqsave(&host->lock, flags);
739
740 imask = mmc_readl(host, REG_IMASK);
741 if (enable) {
742 host->sdio_imask = SDXC_SDIO_INTERRUPT;
743 imask |= SDXC_SDIO_INTERRUPT;
744 } else {
745 host->sdio_imask = 0;
746 imask &= ~SDXC_SDIO_INTERRUPT;
747 }
748 mmc_writel(host, REG_IMASK, imask);
749 spin_unlock_irqrestore(&host->lock, flags);
750 }
751
752 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
753 {
754 struct sunxi_mmc_host *host = mmc_priv(mmc);
755 mmc_writel(host, REG_HWRST, 0);
756 udelay(10);
757 mmc_writel(host, REG_HWRST, 1);
758 udelay(300);
759 }
760
761 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
762 {
763 struct sunxi_mmc_host *host = mmc_priv(mmc);
764 struct mmc_command *cmd = mrq->cmd;
765 struct mmc_data *data = mrq->data;
766 unsigned long iflags;
767 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
768 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
769 int ret;
770
771 /* Check for set_ios errors (should never happen) */
772 if (host->ferror) {
773 mrq->cmd->error = host->ferror;
774 mmc_request_done(mmc, mrq);
775 return;
776 }
777
778 if (data) {
779 ret = sunxi_mmc_map_dma(host, data);
780 if (ret < 0) {
781 dev_err(mmc_dev(mmc), "map DMA failed\n");
782 cmd->error = ret;
783 data->error = ret;
784 mmc_request_done(mmc, mrq);
785 return;
786 }
787 }
788
789 if (cmd->opcode == MMC_GO_IDLE_STATE) {
790 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
791 imask |= SDXC_COMMAND_DONE;
792 }
793
794 if (cmd->flags & MMC_RSP_PRESENT) {
795 cmd_val |= SDXC_RESP_EXPIRE;
796 if (cmd->flags & MMC_RSP_136)
797 cmd_val |= SDXC_LONG_RESPONSE;
798 if (cmd->flags & MMC_RSP_CRC)
799 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
800
801 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
802 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
803 if (cmd->data->flags & MMC_DATA_STREAM) {
804 imask |= SDXC_AUTO_COMMAND_DONE;
805 cmd_val |= SDXC_SEQUENCE_MODE |
806 SDXC_SEND_AUTO_STOP;
807 }
808
809 if (cmd->data->stop) {
810 imask |= SDXC_AUTO_COMMAND_DONE;
811 cmd_val |= SDXC_SEND_AUTO_STOP;
812 } else {
813 imask |= SDXC_DATA_OVER;
814 }
815
816 if (cmd->data->flags & MMC_DATA_WRITE)
817 cmd_val |= SDXC_WRITE;
818 else
819 host->wait_dma = true;
820 } else {
821 imask |= SDXC_COMMAND_DONE;
822 }
823 } else {
824 imask |= SDXC_COMMAND_DONE;
825 }
826
827 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
828 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
829 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
830
831 spin_lock_irqsave(&host->lock, iflags);
832
833 if (host->mrq || host->manual_stop_mrq) {
834 spin_unlock_irqrestore(&host->lock, iflags);
835
836 if (data)
837 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
838 sunxi_mmc_get_dma_dir(data));
839
840 dev_err(mmc_dev(mmc), "request already pending\n");
841 mrq->cmd->error = -EBUSY;
842 mmc_request_done(mmc, mrq);
843 return;
844 }
845
846 if (data) {
847 mmc_writel(host, REG_BLKSZ, data->blksz);
848 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
849 sunxi_mmc_start_dma(host, data);
850 }
851
852 host->mrq = mrq;
853 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
854 mmc_writel(host, REG_CARG, cmd->arg);
855 mmc_writel(host, REG_CMDR, cmd_val);
856
857 spin_unlock_irqrestore(&host->lock, iflags);
858 }
859
860 static const struct of_device_id sunxi_mmc_of_match[] = {
861 { .compatible = "allwinner,sun4i-a10-mmc", },
862 { .compatible = "allwinner,sun5i-a13-mmc", },
863 { /* sentinel */ }
864 };
865 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
866
867 static struct mmc_host_ops sunxi_mmc_ops = {
868 .request = sunxi_mmc_request,
869 .set_ios = sunxi_mmc_set_ios,
870 .get_ro = mmc_gpio_get_ro,
871 .get_cd = mmc_gpio_get_cd,
872 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
873 .hw_reset = sunxi_mmc_hw_reset,
874 };
875
876 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
877 struct platform_device *pdev)
878 {
879 struct device_node *np = pdev->dev.of_node;
880 int ret;
881
882 if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
883 host->idma_des_size_bits = 13;
884 else
885 host->idma_des_size_bits = 16;
886
887 ret = mmc_regulator_get_supply(host->mmc);
888 if (ret) {
889 if (ret != -EPROBE_DEFER)
890 dev_err(&pdev->dev, "Could not get vmmc supply\n");
891 return ret;
892 }
893
894 host->reg_base = devm_ioremap_resource(&pdev->dev,
895 platform_get_resource(pdev, IORESOURCE_MEM, 0));
896 if (IS_ERR(host->reg_base))
897 return PTR_ERR(host->reg_base);
898
899 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
900 if (IS_ERR(host->clk_ahb)) {
901 dev_err(&pdev->dev, "Could not get ahb clock\n");
902 return PTR_ERR(host->clk_ahb);
903 }
904
905 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
906 if (IS_ERR(host->clk_mmc)) {
907 dev_err(&pdev->dev, "Could not get mmc clock\n");
908 return PTR_ERR(host->clk_mmc);
909 }
910
911 host->reset = devm_reset_control_get(&pdev->dev, "ahb");
912
913 ret = clk_prepare_enable(host->clk_ahb);
914 if (ret) {
915 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
916 return ret;
917 }
918
919 ret = clk_prepare_enable(host->clk_mmc);
920 if (ret) {
921 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
922 goto error_disable_clk_ahb;
923 }
924
925 if (!IS_ERR(host->reset)) {
926 ret = reset_control_deassert(host->reset);
927 if (ret) {
928 dev_err(&pdev->dev, "reset err %d\n", ret);
929 goto error_disable_clk_mmc;
930 }
931 }
932
933 /*
934 * Sometimes the controller asserts the irq on boot for some reason,
935 * make sure the controller is in a sane state before enabling irqs.
936 */
937 ret = sunxi_mmc_reset_host(host);
938 if (ret)
939 goto error_assert_reset;
940
941 host->irq = platform_get_irq(pdev, 0);
942 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
943 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
944
945 error_assert_reset:
946 if (!IS_ERR(host->reset))
947 reset_control_assert(host->reset);
948 error_disable_clk_mmc:
949 clk_disable_unprepare(host->clk_mmc);
950 error_disable_clk_ahb:
951 clk_disable_unprepare(host->clk_ahb);
952 return ret;
953 }
954
955 static int sunxi_mmc_probe(struct platform_device *pdev)
956 {
957 struct sunxi_mmc_host *host;
958 struct mmc_host *mmc;
959 int ret;
960
961 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
962 if (!mmc) {
963 dev_err(&pdev->dev, "mmc alloc host failed\n");
964 return -ENOMEM;
965 }
966
967 host = mmc_priv(mmc);
968 host->mmc = mmc;
969 spin_lock_init(&host->lock);
970
971 ret = sunxi_mmc_resource_request(host, pdev);
972 if (ret)
973 goto error_free_host;
974
975 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
976 &host->sg_dma, GFP_KERNEL);
977 if (!host->sg_cpu) {
978 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
979 ret = -ENOMEM;
980 goto error_free_host;
981 }
982
983 mmc->ops = &sunxi_mmc_ops;
984 mmc->max_blk_count = 8192;
985 mmc->max_blk_size = 4096;
986 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
987 mmc->max_seg_size = (1 << host->idma_des_size_bits);
988 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
989 /* 400kHz ~ 50MHz */
990 mmc->f_min = 400000;
991 mmc->f_max = 50000000;
992 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
993 MMC_CAP_ERASE;
994
995 ret = mmc_of_parse(mmc);
996 if (ret)
997 goto error_free_dma;
998
999 ret = mmc_add_host(mmc);
1000 if (ret)
1001 goto error_free_dma;
1002
1003 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1004 platform_set_drvdata(pdev, mmc);
1005 return 0;
1006
1007 error_free_dma:
1008 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1009 error_free_host:
1010 mmc_free_host(mmc);
1011 return ret;
1012 }
1013
1014 static int sunxi_mmc_remove(struct platform_device *pdev)
1015 {
1016 struct mmc_host *mmc = platform_get_drvdata(pdev);
1017 struct sunxi_mmc_host *host = mmc_priv(mmc);
1018
1019 mmc_remove_host(mmc);
1020 disable_irq(host->irq);
1021 sunxi_mmc_reset_host(host);
1022
1023 if (!IS_ERR(host->reset))
1024 reset_control_assert(host->reset);
1025
1026 clk_disable_unprepare(host->clk_mmc);
1027 clk_disable_unprepare(host->clk_ahb);
1028
1029 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1030 mmc_free_host(mmc);
1031
1032 return 0;
1033 }
1034
1035 static struct platform_driver sunxi_mmc_driver = {
1036 .driver = {
1037 .name = "sunxi-mmc",
1038 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1039 },
1040 .probe = sunxi_mmc_probe,
1041 .remove = sunxi_mmc_remove,
1042 };
1043 module_platform_driver(sunxi_mmc_driver);
1044
1045 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1046 MODULE_LICENSE("GPL v2");
1047 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1048 MODULE_ALIAS("platform:sunxi-mmc");
Linux with added FPC-III support