arch/arm/mach-mv78xx0/common.c

   1 /*
   2  * arch/arm/mach-mv78xx0/common.c
   3  *
   4  * Core functions for Marvell MV78xx0 SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/ata_platform.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/ethtool.h>
  18 #include <asm/hardware/cache-feroceon-l2.h>
  19 #include <asm/mach/map.h>
  20 #include <asm/mach/time.h>
  21 #include <mach/mv78xx0.h>
  22 #include <mach/bridge-regs.h>
  23 #include <linux/platform_data/usb-ehci-orion.h>
  24 #include <linux/platform_data/mtd-orion_nand.h>
  25 #include <plat/time.h>
  26 #include <plat/common.h>
  27 #include <plat/addr-map.h>
  28 #include "common.h"
  29
  30 static int get_tclk(void);
  31
  32 /*****************************************************************************
  33  * Common bits
  34  ****************************************************************************/
  35 int mv78xx0_core_index(void)
  36 {
  37         u32 extra;
  38
  39         /*
  40          * Read Extra Features register.
  41          */
  42         __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
  43
  44         return !!(extra & 0x00004000);
  45 }
  46
  47 static int get_hclk(void)
  48 {
  49         int hclk;
  50
  51         /*
  52          * HCLK tick rate is configured by DEV_D[7:5] pins.
  53          */
  54         switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
  55         case 0:
  56                 hclk = 166666667;
  57                 break;
  58         case 1:
  59                 hclk = 200000000;
  60                 break;
  61         case 2:
  62                 hclk = 266666667;
  63                 break;
  64         case 3:
  65                 hclk = 333333333;
  66                 break;
  67         case 4:
  68                 hclk = 400000000;
  69                 break;
  70         default:
  71                 panic("unknown HCLK PLL setting: %.8x\n",
  72                         readl(SAMPLE_AT_RESET_LOW));
  73         }
  74
  75         return hclk;
  76 }
  77
  78 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
  79 {
  80         u32 cfg;
  81
  82         /*
  83          * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
  84          * PCLK/L2CLK by bits [19:14].
  85          */
  86         if (core_index == 0) {
  87                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
  88         } else {
  89                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
  90         }
  91
  92         /*
  93          * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
  94          * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
  95          */
  96         *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
  97
  98         /*
  99          * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
 100          * ratio (1, 2, 3).
 101          */
 102         *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
 103 }
 104
 105 static int get_tclk(void)
 106 {
 107         int tclk_freq;
 108
 109         /*
 110          * TCLK tick rate is configured by DEV_A[2:0] strap pins.
 111          */
 112         switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
 113         case 1:
 114                 tclk_freq = 166666667;
 115                 break;
 116         case 3:
 117                 tclk_freq = 200000000;
 118                 break;
 119         default:
 120                 panic("unknown TCLK PLL setting: %.8x\n",
 121                         readl(SAMPLE_AT_RESET_HIGH));
 122         }
 123
 124         return tclk_freq;
 125 }
 126
 127
 128 /*****************************************************************************
 129  * I/O Address Mapping
 130  ****************************************************************************/
 131 static struct map_desc mv78xx0_io_desc[] __initdata = {
 132         {
 133                 .virtual        = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
 134                 .pfn            = 0,
 135                 .length         = MV78XX0_CORE_REGS_SIZE,
 136                 .type           = MT_DEVICE,
 137         }, {
 138                 .virtual        = (unsigned long) MV78XX0_REGS_VIRT_BASE,
 139                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
 140                 .length         = MV78XX0_REGS_SIZE,
 141                 .type           = MT_DEVICE,
 142         },
 143 };
 144
 145 void __init mv78xx0_map_io(void)
 146 {
 147         unsigned long phys;
 148
 149         /*
 150          * Map the right set of per-core registers depending on
 151          * which core we are running on.
 152          */
 153         if (mv78xx0_core_index() == 0) {
 154                 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
 155         } else {
 156                 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
 157         }
 158         mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
 159
 160         iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
 161 }
 162
 163
 164 /*****************************************************************************
 165  * CLK tree
 166  ****************************************************************************/
 167 static struct clk *tclk;
 168
 169 static void __init clk_init(void)
 170 {
 171         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
 172                                        get_tclk());
 173
 174         orion_clkdev_init(tclk);
 175 }
 176
 177 /*****************************************************************************
 178  * EHCI
 179  ****************************************************************************/
 180 void __init mv78xx0_ehci0_init(void)
 181 {
 182         orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
 183 }
 184
 185
 186 /*****************************************************************************
 187  * EHCI1
 188  ****************************************************************************/
 189 void __init mv78xx0_ehci1_init(void)
 190 {
 191         orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 192 }
 193
 194
 195 /*****************************************************************************
 196  * EHCI2
 197  ****************************************************************************/
 198 void __init mv78xx0_ehci2_init(void)
 199 {
 200         orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 201 }
 202
 203
 204 /*****************************************************************************
 205  * GE00
 206  ****************************************************************************/
 207 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 208 {
 209         orion_ge00_init(eth_data,
 210                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
 211                         IRQ_MV78XX0_GE_ERR,
 212                         MV643XX_TX_CSUM_DEFAULT_LIMIT);
 213 }
 214
 215
 216 /*****************************************************************************
 217  * GE01
 218  ****************************************************************************/
 219 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 220 {
 221         orion_ge01_init(eth_data,
 222                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
 223                         NO_IRQ,
 224                         MV643XX_TX_CSUM_DEFAULT_LIMIT);
 225 }
 226
 227
 228 /*****************************************************************************
 229  * GE10
 230  ****************************************************************************/
 231 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 232 {
 233         u32 dev, rev;
 234
 235         /*
 236          * On the Z0, ge10 and ge11 are internally connected back
 237          * to back, and not brought out.
 238          */
 239         mv78xx0_pcie_id(&dev, &rev);
 240         if (dev == MV78X00_Z0_DEV_ID) {
 241                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
 242                 eth_data->speed = SPEED_1000;
 243                 eth_data->duplex = DUPLEX_FULL;
 244         }
 245
 246         orion_ge10_init(eth_data,
 247                         GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
 248                         NO_IRQ);
 249 }
 250
 251
 252 /*****************************************************************************
 253  * GE11
 254  ****************************************************************************/
 255 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 256 {
 257         u32 dev, rev;
 258
 259         /*
 260          * On the Z0, ge10 and ge11 are internally connected back
 261          * to back, and not brought out.
 262          */
 263         mv78xx0_pcie_id(&dev, &rev);
 264         if (dev == MV78X00_Z0_DEV_ID) {
 265                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
 266                 eth_data->speed = SPEED_1000;
 267                 eth_data->duplex = DUPLEX_FULL;
 268         }
 269
 270         orion_ge11_init(eth_data,
 271                         GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
 272                         NO_IRQ);
 273 }
 274
 275 /*****************************************************************************
 276  * I2C
 277  ****************************************************************************/
 278 void __init mv78xx0_i2c_init(void)
 279 {
 280         orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
 281         orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
 282 }
 283
 284 /*****************************************************************************
 285  * SATA
 286  ****************************************************************************/
 287 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 288 {
 289         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 290 }
 291
 292
 293 /*****************************************************************************
 294  * UART0
 295  ****************************************************************************/
 296 void __init mv78xx0_uart0_init(void)
 297 {
 298         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 299                          IRQ_MV78XX0_UART_0, tclk);
 300 }
 301
 302
 303 /*****************************************************************************
 304  * UART1
 305  ****************************************************************************/
 306 void __init mv78xx0_uart1_init(void)
 307 {
 308         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 309                          IRQ_MV78XX0_UART_1, tclk);
 310 }
 311
 312
 313 /*****************************************************************************
 314  * UART2
 315  ****************************************************************************/
 316 void __init mv78xx0_uart2_init(void)
 317 {
 318         orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
 319                          IRQ_MV78XX0_UART_2, tclk);
 320 }
 321
 322 /*****************************************************************************
 323  * UART3
 324  ****************************************************************************/
 325 void __init mv78xx0_uart3_init(void)
 326 {
 327         orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
 328                          IRQ_MV78XX0_UART_3, tclk);
 329 }
 330
 331 /*****************************************************************************
 332  * Time handling
 333  ****************************************************************************/
 334 void __init mv78xx0_init_early(void)
 335 {
 336         orion_time_set_base(TIMER_VIRT_BASE);
 337         if (mv78xx0_core_index() == 0)
 338                 mvebu_mbus_init("marvell,mv78xx0-mbus",
 339                                 BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
 340                                 DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
 341         else
 342                 mvebu_mbus_init("marvell,mv78xx0-mbus",
 343                                 BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
 344                                 DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
 345 }
 346
 347 void __init_refok mv78xx0_timer_init(void)
 348 {
 349         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 350                         IRQ_MV78XX0_TIMER_1, get_tclk());
 351 }
 352
 353
 354 /*****************************************************************************
 355  * General
 356  ****************************************************************************/
 357 static char * __init mv78xx0_id(void)
 358 {
 359         u32 dev, rev;
 360
 361         mv78xx0_pcie_id(&dev, &rev);
 362
 363         if (dev == MV78X00_Z0_DEV_ID) {
 364                 if (rev == MV78X00_REV_Z0)
 365                         return "MV78X00-Z0";
 366                 else
 367                         return "MV78X00-Rev-Unsupported";
 368         } else if (dev == MV78100_DEV_ID) {
 369                 if (rev == MV78100_REV_A0)
 370                         return "MV78100-A0";
 371                 else if (rev == MV78100_REV_A1)
 372                         return "MV78100-A1";
 373                 else
 374                         return "MV78100-Rev-Unsupported";
 375         } else if (dev == MV78200_DEV_ID) {
 376                 if (rev == MV78100_REV_A0)
 377                         return "MV78200-A0";
 378                 else
 379                         return "MV78200-Rev-Unsupported";
 380         } else {
 381                 return "Device-Unknown";
 382         }
 383 }
 384
 385 static int __init is_l2_writethrough(void)
 386 {
 387         return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
 388 }
 389
 390 void __init mv78xx0_init(void)
 391 {
 392         int core_index;
 393         int hclk;
 394         int pclk;
 395         int l2clk;
 396
 397         core_index = mv78xx0_core_index();
 398         hclk = get_hclk();
 399         get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
 400
 401         printk(KERN_INFO "%s ", mv78xx0_id());
 402         printk("core #%d, ", core_index);
 403         printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
 404         printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
 405         printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
 406         printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
 407
 408 #ifdef CONFIG_CACHE_FEROCEON_L2
 409         feroceon_l2_init(is_l2_writethrough());
 410 #endif
 411
 412         /* Setup root of clk tree */
 413         clk_init();
 414 }
 415
 416 void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 417 {
 418         /*
 419          * Enable soft reset to assert RSTOUTn.
 420          */
 421         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 422
 423         /*
 424          * Assert soft reset.
 425          */
 426         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 427
 428         while (1)
 429                 ;
 430 }