arch/s390/include/asm/processor.h

   1 /*
   2  *  S390 version
   3  *    Copyright IBM Corp. 1999
   4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   6  *
   7  *  Derived from "include/asm-i386/processor.h"
   8  *    Copyright (C) 1994, Linus Torvalds
   9  */
  10
  11 #ifndef __ASM_S390_PROCESSOR_H
  12 #define __ASM_S390_PROCESSOR_H
  13
  14 #define CIF_MCCK_PENDING        0       /* machine check handling is pending */
  15 #define CIF_ASCE                1       /* user asce needs fixup / uaccess */
  16 #define CIF_NOHZ_DELAY          2       /* delay HZ disable for a tick */
  17
  18 #define _CIF_MCCK_PENDING       (1<<CIF_MCCK_PENDING)
  19 #define _CIF_ASCE               (1<<CIF_ASCE)
  20 #define _CIF_NOHZ_DELAY         (1<<CIF_NOHZ_DELAY)
  21
  22 #ifndef __ASSEMBLY__
  23
  24 #include <linux/linkage.h>
  25 #include <linux/irqflags.h>
  26 #include <asm/cpu.h>
  27 #include <asm/page.h>
  28 #include <asm/ptrace.h>
  29 #include <asm/setup.h>
  30 #include <asm/runtime_instr.h>
  31
  32 static inline void set_cpu_flag(int flag)
  33 {
  34         S390_lowcore.cpu_flags |= (1U << flag);
  35 }
  36
  37 static inline void clear_cpu_flag(int flag)
  38 {
  39         S390_lowcore.cpu_flags &= ~(1U << flag);
  40 }
  41
  42 static inline int test_cpu_flag(int flag)
  43 {
  44         return !!(S390_lowcore.cpu_flags & (1U << flag));
  45 }
  46
  47 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
  48
  49 /*
  50  * Default implementation of macro that returns current
  51  * instruction pointer ("program counter").
  52  */
  53 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  54
  55 static inline void get_cpu_id(struct cpuid *ptr)
  56 {
  57         asm volatile("stidp %0" : "=Q" (*ptr));
  58 }
  59
  60 extern void s390_adjust_jiffies(void);
  61 extern const struct seq_operations cpuinfo_op;
  62 extern int sysctl_ieee_emulation_warnings;
  63 extern void execve_tail(void);
  64
  65 /*
  66  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  67  */
  68
  69 #define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  70 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  71                                         (1UL << 30) : (1UL << 41))
  72 #define TASK_SIZE               TASK_SIZE_OF(current)
  73 #define TASK_MAX_SIZE           (1UL << 53)
  74
  75 #define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  76 #define STACK_TOP_MAX           (1UL << 42)
  77
  78 #define HAVE_ARCH_PICK_MMAP_LAYOUT
  79
  80 typedef struct {
  81         __u32 ar4;
  82 } mm_segment_t;
  83
  84 /*
  85  * Thread structure
  86  */
  87 struct thread_struct {
  88         s390_fp_regs fp_regs;
  89         unsigned int  acrs[NUM_ACRS];
  90         unsigned long ksp;              /* kernel stack pointer             */
  91         mm_segment_t mm_segment;
  92         unsigned long gmap_addr;        /* address of last gmap fault. */
  93         unsigned int gmap_pfault;       /* signal of a pending guest pfault */
  94         struct per_regs per_user;       /* User specified PER registers */
  95         struct per_event per_event;     /* Cause of the last PER trap */
  96         unsigned long per_flags;        /* Flags to control debug behavior */
  97         /* pfault_wait is used to block the process on a pfault event */
  98         unsigned long pfault_wait;
  99         struct list_head list;
 100         /* cpu runtime instrumentation */
 101         struct runtime_instr_cb *ri_cb;
 102         int ri_signum;
 103         unsigned char trap_tdb[256];    /* Transaction abort diagnose block */
 104         __vector128 *vxrs;              /* Vector register save area */
 105 };
 106
 107 /* Flag to disable transactions. */
 108 #define PER_FLAG_NO_TE                  1UL
 109 /* Flag to enable random transaction aborts. */
 110 #define PER_FLAG_TE_ABORT_RAND          2UL
 111 /* Flag to specify random transaction abort mode:
 112  * - abort each transaction at a random instruction before TEND if set.
 113  * - abort random transactions at a random instruction if cleared.
 114  */
 115 #define PER_FLAG_TE_ABORT_RAND_TEND     4UL
 116
 117 typedef struct thread_struct thread_struct;
 118
 119 /*
 120  * Stack layout of a C stack frame.
 121  */
 122 #ifndef __PACK_STACK
 123 struct stack_frame {
 124         unsigned long back_chain;
 125         unsigned long empty1[5];
 126         unsigned long gprs[10];
 127         unsigned int  empty2[8];
 128 };
 129 #else
 130 struct stack_frame {
 131         unsigned long empty1[5];
 132         unsigned int  empty2[8];
 133         unsigned long gprs[10];
 134         unsigned long back_chain;
 135 };
 136 #endif
 137
 138 #define ARCH_MIN_TASKALIGN      8
 139
 140 #define INIT_THREAD {                                                   \
 141         .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 142 }
 143
 144 /*
 145  * Do necessary setup to start up a new thread.
 146  */
 147 #define start_thread(regs, new_psw, new_stackp) do {                    \
 148         regs->psw.mask  = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;    \
 149         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 150         regs->gprs[15]  = new_stackp;                                   \
 151         execve_tail();                                                  \
 152 } while (0)
 153
 154 #define start_thread31(regs, new_psw, new_stackp) do {                  \
 155         regs->psw.mask  = PSW_USER_BITS | PSW_MASK_BA;                  \
 156         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 157         regs->gprs[15]  = new_stackp;                                   \
 158         crst_table_downgrade(current->mm, 1UL << 31);                   \
 159         execve_tail();                                                  \
 160 } while (0)
 161
 162 /* Forward declaration, a strange C thing */
 163 struct task_struct;
 164 struct mm_struct;
 165 struct seq_file;
 166
 167 void show_cacheinfo(struct seq_file *m);
 168
 169 /* Free all resources held by a thread. */
 170 extern void release_thread(struct task_struct *);
 171
 172 /*
 173  * Return saved PC of a blocked thread.
 174  */
 175 extern unsigned long thread_saved_pc(struct task_struct *t);
 176
 177 unsigned long get_wchan(struct task_struct *p);
 178 #define task_pt_regs(tsk) ((struct pt_regs *) \
 179         (task_stack_page(tsk) + THREAD_SIZE) - 1)
 180 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 181 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 182
 183 /* Has task runtime instrumentation enabled ? */
 184 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
 185
 186 static inline unsigned short stap(void)
 187 {
 188         unsigned short cpu_address;
 189
 190         asm volatile("stap %0" : "=m" (cpu_address));
 191         return cpu_address;
 192 }
 193
 194 /*
 195  * Give up the time slice of the virtual PU.
 196  */
 197 void cpu_relax(void);
 198
 199 #define cpu_relax_lowlatency()  barrier()
 200
 201 static inline void psw_set_key(unsigned int key)
 202 {
 203         asm volatile("spka 0(%0)" : : "d" (key));
 204 }
 205
 206 /*
 207  * Set PSW to specified value.
 208  */
 209 static inline void __load_psw(psw_t psw)
 210 {
 211         asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 212 }
 213
 214 /*
 215  * Set PSW mask to specified value, while leaving the
 216  * PSW addr pointing to the next instruction.
 217  */
 218 static inline void __load_psw_mask (unsigned long mask)
 219 {
 220         unsigned long addr;
 221         psw_t psw;
 222
 223         psw.mask = mask;
 224
 225         asm volatile(
 226                 "       larl    %0,1f\n"
 227                 "       stg     %0,%O1+8(%R1)\n"
 228                 "       lpswe   %1\n"
 229                 "1:"
 230                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 231 }
 232
 233 /*
 234  * Rewind PSW instruction address by specified number of bytes.
 235  */
 236 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 237 {
 238         unsigned long mask;
 239
 240         mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 241                (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 242                                           (1UL << 24) - 1;
 243         return (psw.addr - ilc) & mask;
 244 }
 245
 246 /*
 247  * Function to stop a processor until the next interrupt occurs
 248  */
 249 void enabled_wait(void);
 250
 251 /*
 252  * Function to drop a processor into disabled wait state
 253  */
 254 static inline void __noreturn disabled_wait(unsigned long code)
 255 {
 256         unsigned long ctl_buf;
 257         psw_t dw_psw;
 258
 259         dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 260         dw_psw.addr = code;
 261         /*
 262          * Store status and then load disabled wait psw,
 263          * the processor is dead afterwards
 264          */
 265         asm volatile(
 266                 "       stctg   0,0,0(%2)\n"
 267                 "       ni      4(%2),0xef\n"   /* switch off protection */
 268                 "       lctlg   0,0,0(%2)\n"
 269                 "       lghi    1,0x1000\n"
 270                 "       stpt    0x328(1)\n"     /* store timer */
 271                 "       stckc   0x330(1)\n"     /* store clock comparator */
 272                 "       stpx    0x318(1)\n"     /* store prefix register */
 273                 "       stam    0,15,0x340(1)\n"/* store access registers */
 274                 "       stfpc   0x31c(1)\n"     /* store fpu control */
 275                 "       std     0,0x200(1)\n"   /* store f0 */
 276                 "       std     1,0x208(1)\n"   /* store f1 */
 277                 "       std     2,0x210(1)\n"   /* store f2 */
 278                 "       std     3,0x218(1)\n"   /* store f3 */
 279                 "       std     4,0x220(1)\n"   /* store f4 */
 280                 "       std     5,0x228(1)\n"   /* store f5 */
 281                 "       std     6,0x230(1)\n"   /* store f6 */
 282                 "       std     7,0x238(1)\n"   /* store f7 */
 283                 "       std     8,0x240(1)\n"   /* store f8 */
 284                 "       std     9,0x248(1)\n"   /* store f9 */
 285                 "       std     10,0x250(1)\n"  /* store f10 */
 286                 "       std     11,0x258(1)\n"  /* store f11 */
 287                 "       std     12,0x260(1)\n"  /* store f12 */
 288                 "       std     13,0x268(1)\n"  /* store f13 */
 289                 "       std     14,0x270(1)\n"  /* store f14 */
 290                 "       std     15,0x278(1)\n"  /* store f15 */
 291                 "       stmg    0,15,0x280(1)\n"/* store general registers */
 292                 "       stctg   0,15,0x380(1)\n"/* store control registers */
 293                 "       oi      0x384(1),0x10\n"/* fake protection bit */
 294                 "       lpswe   0(%1)"
 295                 : "=m" (ctl_buf)
 296                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 297         while (1);
 298 }
 299
 300 /*
 301  * Use to set psw mask except for the first byte which
 302  * won't be changed by this function.
 303  */
 304 static inline void
 305 __set_psw_mask(unsigned long mask)
 306 {
 307         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 308 }
 309
 310 #define local_mcck_enable() \
 311         __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
 312 #define local_mcck_disable() \
 313         __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
 314
 315 /*
 316  * Basic Machine Check/Program Check Handler.
 317  */
 318
 319 extern void s390_base_mcck_handler(void);
 320 extern void s390_base_pgm_handler(void);
 321 extern void s390_base_ext_handler(void);
 322
 323 extern void (*s390_base_mcck_handler_fn)(void);
 324 extern void (*s390_base_pgm_handler_fn)(void);
 325 extern void (*s390_base_ext_handler_fn)(void);
 326
 327 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 328
 329 extern int memcpy_real(void *, void *, size_t);
 330 extern void memcpy_absolute(void *, void *, size_t);
 331
 332 #define mem_assign_absolute(dest, val) {                        \
 333         __typeof__(dest) __tmp = (val);                         \
 334                                                                 \
 335         BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 336         memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 337 }
 338
 339 /*
 340  * Helper macro for exception table entries
 341  */
 342 #define EX_TABLE(_fault, _target)       \
 343         ".section __ex_table,\"a\"\n"   \
 344         ".align 4\n"                    \
 345         ".long  (" #_fault ") - .\n"    \
 346         ".long  (" #_target ") - .\n"   \
 347         ".previous\n"
 348
 349 #else /* __ASSEMBLY__ */
 350
 351 #define EX_TABLE(_fault, _target)       \
 352         .section __ex_table,"a" ;       \
 353         .align  4 ;                     \
 354         .long   (_fault) - . ;          \
 355         .long   (_target) - . ;         \
 356         .previous
 357
 358 #endif /* __ASSEMBLY__ */
 359
 360 #endif /* __ASM_S390_PROCESSOR_H */