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Merge tag 'pm+acpi-4.2-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux/fpc-iii.git] / arch / s390 / net / bpf_jit_comp.c
blob8d2e5165865f2c27b50fe8b1c6845de45666698a
1 /*
2 * BPF Jit compiler for s390.
3 *
4 * Minimum build requirements:
5 *
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
9 * - PACK_STACK
10 * - 64BIT
11 *
12 * Copyright IBM Corp. 2012,2015
13 *
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
16 */
17
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
25 #include <asm/cacheflush.h>
26 #include <asm/dis.h>
27 #include "bpf_jit.h"
28
29 int bpf_jit_enable __read_mostly;
30
31 struct bpf_jit {
32 u32 seen; /* Flags to remember seen eBPF instructions */
33 u32 seen_reg[16]; /* Array to remember which registers are used */
34 u32 *addrs; /* Array with relative instruction addresses */
35 u8 *prg_buf; /* Start of program */
36 int size; /* Size of program and literal pool */
37 int size_prg; /* Size of program */
38 int prg; /* Current position in program */
39 int lit_start; /* Start of literal pool */
40 int lit; /* Current position in literal pool */
41 int base_ip; /* Base address for literal pool */
42 int ret0_ip; /* Address of return 0 */
43 int exit_ip; /* Address of exit */
44 int tail_call_start; /* Tail call start offset */
45 int labels[1]; /* Labels for local jumps */
46 };
47
48 #define BPF_SIZE_MAX 4096 /* Max size for program */
49
50 #define SEEN_SKB 1 /* skb access */
51 #define SEEN_MEM 2 /* use mem[] for temporary storage */
52 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
53 #define SEEN_LITERAL 8 /* code uses literals */
54 #define SEEN_FUNC 16 /* calls C functions */
55 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
56 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
57
58 /*
59 * s390 registers
60 */
61 #define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */
62 #define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */
63 #define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */
64 #define REG_L (__MAX_BPF_REG+3) /* Literal pool register */
65 #define REG_15 (__MAX_BPF_REG+4) /* Register 15 */
66 #define REG_0 REG_W0 /* Register 0 */
67 #define REG_1 REG_W1 /* Register 1 */
68 #define REG_2 BPF_REG_1 /* Register 2 */
69 #define REG_14 BPF_REG_0 /* Register 14 */
70
71 /*
72 * Mapping of BPF registers to s390 registers
73 */
74 static const int reg2hex[] = {
75 /* Return code */
76 [BPF_REG_0] = 14,
77 /* Function parameters */
78 [BPF_REG_1] = 2,
79 [BPF_REG_2] = 3,
80 [BPF_REG_3] = 4,
81 [BPF_REG_4] = 5,
82 [BPF_REG_5] = 6,
83 /* Call saved registers */
84 [BPF_REG_6] = 7,
85 [BPF_REG_7] = 8,
86 [BPF_REG_8] = 9,
87 [BPF_REG_9] = 10,
88 /* BPF stack pointer */
89 [BPF_REG_FP] = 13,
90 /* SKB data pointer */
91 [REG_SKB_DATA] = 12,
92 /* Work registers for s390x backend */
93 [REG_W0] = 0,
94 [REG_W1] = 1,
95 [REG_L] = 11,
96 [REG_15] = 15,
97 };
98
99 static inline u32 reg(u32 dst_reg, u32 src_reg)
100 {
101 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
102 }
103
104 static inline u32 reg_high(u32 reg)
105 {
106 return reg2hex[reg] << 4;
107 }
108
109 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
110 {
111 u32 r1 = reg2hex[b1];
112
113 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
114 jit->seen_reg[r1] = 1;
115 }
116
117 #define REG_SET_SEEN(b1) \
118 ({ \
119 reg_set_seen(jit, b1); \
120 })
121
122 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
123
124 /*
125 * EMIT macros for code generation
126 */
127
128 #define _EMIT2(op) \
129 ({ \
130 if (jit->prg_buf) \
131 *(u16 *) (jit->prg_buf + jit->prg) = op; \
132 jit->prg += 2; \
133 })
134
135 #define EMIT2(op, b1, b2) \
136 ({ \
137 _EMIT2(op | reg(b1, b2)); \
138 REG_SET_SEEN(b1); \
139 REG_SET_SEEN(b2); \
140 })
141
142 #define _EMIT4(op) \
143 ({ \
144 if (jit->prg_buf) \
145 *(u32 *) (jit->prg_buf + jit->prg) = op; \
146 jit->prg += 4; \
147 })
148
149 #define EMIT4(op, b1, b2) \
150 ({ \
151 _EMIT4(op | reg(b1, b2)); \
152 REG_SET_SEEN(b1); \
153 REG_SET_SEEN(b2); \
154 })
155
156 #define EMIT4_RRF(op, b1, b2, b3) \
157 ({ \
158 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
159 REG_SET_SEEN(b1); \
160 REG_SET_SEEN(b2); \
161 REG_SET_SEEN(b3); \
162 })
163
164 #define _EMIT4_DISP(op, disp) \
165 ({ \
166 unsigned int __disp = (disp) & 0xfff; \
167 _EMIT4(op | __disp); \
168 })
169
170 #define EMIT4_DISP(op, b1, b2, disp) \
171 ({ \
172 _EMIT4_DISP(op | reg_high(b1) << 16 | \
173 reg_high(b2) << 8, disp); \
174 REG_SET_SEEN(b1); \
175 REG_SET_SEEN(b2); \
176 })
177
178 #define EMIT4_IMM(op, b1, imm) \
179 ({ \
180 unsigned int __imm = (imm) & 0xffff; \
181 _EMIT4(op | reg_high(b1) << 16 | __imm); \
182 REG_SET_SEEN(b1); \
183 })
184
185 #define EMIT4_PCREL(op, pcrel) \
186 ({ \
187 long __pcrel = ((pcrel) >> 1) & 0xffff; \
188 _EMIT4(op | __pcrel); \
189 })
190
191 #define _EMIT6(op1, op2) \
192 ({ \
193 if (jit->prg_buf) { \
194 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
195 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
196 } \
197 jit->prg += 6; \
198 })
199
200 #define _EMIT6_DISP(op1, op2, disp) \
201 ({ \
202 unsigned int __disp = (disp) & 0xfff; \
203 _EMIT6(op1 | __disp, op2); \
204 })
205
206 #define EMIT6_DISP(op1, op2, b1, b2, b3, disp) \
207 ({ \
208 _EMIT6_DISP(op1 | reg(b1, b2) << 16 | \
209 reg_high(b3) << 8, op2, disp); \
210 REG_SET_SEEN(b1); \
211 REG_SET_SEEN(b2); \
212 REG_SET_SEEN(b3); \
213 })
214
215 #define _EMIT6_DISP_LH(op1, op2, disp) \
216 ({ \
217 unsigned int __disp_h = ((u32)disp) & 0xff000; \
218 unsigned int __disp_l = ((u32)disp) & 0x00fff; \
219 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
220 })
221
222 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
223 ({ \
224 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
225 reg_high(b3) << 8, op2, disp); \
226 REG_SET_SEEN(b1); \
227 REG_SET_SEEN(b2); \
228 REG_SET_SEEN(b3); \
229 })
230
231 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
232 ({ \
233 int rel = (jit->labels[label] - jit->prg) >> 1; \
234 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
235 op2 | mask << 12); \
236 REG_SET_SEEN(b1); \
237 REG_SET_SEEN(b2); \
238 })
239
240 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
241 ({ \
242 int rel = (jit->labels[label] - jit->prg) >> 1; \
243 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
244 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
245 REG_SET_SEEN(b1); \
246 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
247 })
248
249 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
250 ({ \
251 /* Branch instruction needs 6 bytes */ \
252 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
253 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
254 REG_SET_SEEN(b1); \
255 REG_SET_SEEN(b2); \
256 })
257
258 #define _EMIT6_IMM(op, imm) \
259 ({ \
260 unsigned int __imm = (imm); \
261 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
262 })
263
264 #define EMIT6_IMM(op, b1, imm) \
265 ({ \
266 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
267 REG_SET_SEEN(b1); \
268 })
269
270 #define EMIT_CONST_U32(val) \
271 ({ \
272 unsigned int ret; \
273 ret = jit->lit - jit->base_ip; \
274 jit->seen |= SEEN_LITERAL; \
275 if (jit->prg_buf) \
276 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
277 jit->lit += 4; \
278 ret; \
279 })
280
281 #define EMIT_CONST_U64(val) \
282 ({ \
283 unsigned int ret; \
284 ret = jit->lit - jit->base_ip; \
285 jit->seen |= SEEN_LITERAL; \
286 if (jit->prg_buf) \
287 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
288 jit->lit += 8; \
289 ret; \
290 })
291
292 #define EMIT_ZERO(b1) \
293 ({ \
294 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
295 EMIT4(0xb9160000, b1, b1); \
296 REG_SET_SEEN(b1); \
297 })
298
299 /*
300 * Fill whole space with illegal instructions
301 */
302 static void jit_fill_hole(void *area, unsigned int size)
303 {
304 memset(area, 0, size);
305 }
306
307 /*
308 * Save registers from "rs" (register start) to "re" (register end) on stack
309 */
310 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
311 {
312 u32 off = STK_OFF_R6 + (rs - 6) * 8;
313
314 if (rs == re)
315 /* stg %rs,off(%r15) */
316 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
317 else
318 /* stmg %rs,%re,off(%r15) */
319 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
320 }
321
322 /*
323 * Restore registers from "rs" (register start) to "re" (register end) on stack
324 */
325 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
326 {
327 u32 off = STK_OFF_R6 + (rs - 6) * 8;
328
329 if (jit->seen & SEEN_STACK)
330 off += STK_OFF;
331
332 if (rs == re)
333 /* lg %rs,off(%r15) */
334 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
335 else
336 /* lmg %rs,%re,off(%r15) */
337 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
338 }
339
340 /*
341 * Return first seen register (from start)
342 */
343 static int get_start(struct bpf_jit *jit, int start)
344 {
345 int i;
346
347 for (i = start; i <= 15; i++) {
348 if (jit->seen_reg[i])
349 return i;
350 }
351 return 0;
352 }
353
354 /*
355 * Return last seen register (from start) (gap >= 2)
356 */
357 static int get_end(struct bpf_jit *jit, int start)
358 {
359 int i;
360
361 for (i = start; i < 15; i++) {
362 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
363 return i - 1;
364 }
365 return jit->seen_reg[15] ? 15 : 14;
366 }
367
368 #define REGS_SAVE 1
369 #define REGS_RESTORE 0
370 /*
371 * Save and restore clobbered registers (6-15) on stack.
372 * We save/restore registers in chunks with gap >= 2 registers.
373 */
374 static void save_restore_regs(struct bpf_jit *jit, int op)
375 {
376
377 int re = 6, rs;
378
379 do {
380 rs = get_start(jit, re);
381 if (!rs)
382 break;
383 re = get_end(jit, rs + 1);
384 if (op == REGS_SAVE)
385 save_regs(jit, rs, re);
386 else
387 restore_regs(jit, rs, re);
388 re++;
389 } while (re <= 15);
390 }
391
392 /*
393 * Emit function prologue
394 *
395 * Save registers and create stack frame if necessary.
396 * See stack frame layout desription in "bpf_jit.h"!
397 */
398 static void bpf_jit_prologue(struct bpf_jit *jit)
399 {
400 if (jit->seen & SEEN_TAIL_CALL) {
401 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
402 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
403 } else {
404 /* j tail_call_start: NOP if no tail calls are used */
405 EMIT4_PCREL(0xa7f40000, 6);
406 _EMIT2(0);
407 }
408 /* Tail calls have to skip above initialization */
409 jit->tail_call_start = jit->prg;
410 /* Save registers */
411 save_restore_regs(jit, REGS_SAVE);
412 /* Setup literal pool */
413 if (jit->seen & SEEN_LITERAL) {
414 /* basr %r13,0 */
415 EMIT2(0x0d00, REG_L, REG_0);
416 jit->base_ip = jit->prg;
417 }
418 /* Setup stack and backchain */
419 if (jit->seen & SEEN_STACK) {
420 if (jit->seen & SEEN_FUNC)
421 /* lgr %w1,%r15 (backchain) */
422 EMIT4(0xb9040000, REG_W1, REG_15);
423 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
424 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
425 /* aghi %r15,-STK_OFF */
426 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
427 if (jit->seen & SEEN_FUNC)
428 /* stg %w1,152(%r15) (backchain) */
429 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
430 REG_15, 152);
431 }
432 /*
433 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
434 * we store the SKB header length on the stack and the SKB data
435 * pointer in REG_SKB_DATA.
436 */
437 if (jit->seen & SEEN_SKB) {
438 /* Header length: llgf %w1,<len>(%b1) */
439 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
440 offsetof(struct sk_buff, len));
441 /* s %w1,<data_len>(%b1) */
442 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
443 offsetof(struct sk_buff, data_len));
444 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
445 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15,
446 STK_OFF_HLEN);
447 /* lg %skb_data,data_off(%b1) */
448 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
449 BPF_REG_1, offsetof(struct sk_buff, data));
450 }
451 /* BPF compatibility: clear A (%b0) and X (%b7) registers */
452 if (REG_SEEN(BPF_REG_A))
453 /* lghi %ba,0 */
454 EMIT4_IMM(0xa7090000, BPF_REG_A, 0);
455 if (REG_SEEN(BPF_REG_X))
456 /* lghi %bx,0 */
457 EMIT4_IMM(0xa7090000, BPF_REG_X, 0);
458 }
459
460 /*
461 * Function epilogue
462 */
463 static void bpf_jit_epilogue(struct bpf_jit *jit)
464 {
465 /* Return 0 */
466 if (jit->seen & SEEN_RET0) {
467 jit->ret0_ip = jit->prg;
468 /* lghi %b0,0 */
469 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
470 }
471 jit->exit_ip = jit->prg;
472 /* Load exit code: lgr %r2,%b0 */
473 EMIT4(0xb9040000, REG_2, BPF_REG_0);
474 /* Restore registers */
475 save_restore_regs(jit, REGS_RESTORE);
476 /* br %r14 */
477 _EMIT2(0x07fe);
478 }
479
480 /*
481 * Compile one eBPF instruction into s390x code
482 *
483 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
484 * stack space for the large switch statement.
485 */
486 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
487 {
488 struct bpf_insn *insn = &fp->insnsi[i];
489 int jmp_off, last, insn_count = 1;
490 unsigned int func_addr, mask;
491 u32 dst_reg = insn->dst_reg;
492 u32 src_reg = insn->src_reg;
493 u32 *addrs = jit->addrs;
494 s32 imm = insn->imm;
495 s16 off = insn->off;
496
497 switch (insn->code) {
498 /*
499 * BPF_MOV
500 */
501 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
502 /* llgfr %dst,%src */
503 EMIT4(0xb9160000, dst_reg, src_reg);
504 break;
505 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
506 /* lgr %dst,%src */
507 EMIT4(0xb9040000, dst_reg, src_reg);
508 break;
509 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
510 /* llilf %dst,imm */
511 EMIT6_IMM(0xc00f0000, dst_reg, imm);
512 break;
513 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
514 /* lgfi %dst,imm */
515 EMIT6_IMM(0xc0010000, dst_reg, imm);
516 break;
517 /*
518 * BPF_LD 64
519 */
520 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
521 {
522 /* 16 byte instruction that uses two 'struct bpf_insn' */
523 u64 imm64;
524
525 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
526 /* lg %dst,<d(imm)>(%l) */
527 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
528 EMIT_CONST_U64(imm64));
529 insn_count = 2;
530 break;
531 }
532 /*
533 * BPF_ADD
534 */
535 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
536 /* ar %dst,%src */
537 EMIT2(0x1a00, dst_reg, src_reg);
538 EMIT_ZERO(dst_reg);
539 break;
540 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
541 /* agr %dst,%src */
542 EMIT4(0xb9080000, dst_reg, src_reg);
543 break;
544 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
545 if (!imm)
546 break;
547 /* alfi %dst,imm */
548 EMIT6_IMM(0xc20b0000, dst_reg, imm);
549 EMIT_ZERO(dst_reg);
550 break;
551 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
552 if (!imm)
553 break;
554 /* agfi %dst,imm */
555 EMIT6_IMM(0xc2080000, dst_reg, imm);
556 break;
557 /*
558 * BPF_SUB
559 */
560 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
561 /* sr %dst,%src */
562 EMIT2(0x1b00, dst_reg, src_reg);
563 EMIT_ZERO(dst_reg);
564 break;
565 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
566 /* sgr %dst,%src */
567 EMIT4(0xb9090000, dst_reg, src_reg);
568 break;
569 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
570 if (!imm)
571 break;
572 /* alfi %dst,-imm */
573 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
574 EMIT_ZERO(dst_reg);
575 break;
576 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
577 if (!imm)
578 break;
579 /* agfi %dst,-imm */
580 EMIT6_IMM(0xc2080000, dst_reg, -imm);
581 break;
582 /*
583 * BPF_MUL
584 */
585 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
586 /* msr %dst,%src */
587 EMIT4(0xb2520000, dst_reg, src_reg);
588 EMIT_ZERO(dst_reg);
589 break;
590 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
591 /* msgr %dst,%src */
592 EMIT4(0xb90c0000, dst_reg, src_reg);
593 break;
594 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
595 if (imm == 1)
596 break;
597 /* msfi %r5,imm */
598 EMIT6_IMM(0xc2010000, dst_reg, imm);
599 EMIT_ZERO(dst_reg);
600 break;
601 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
602 if (imm == 1)
603 break;
604 /* msgfi %dst,imm */
605 EMIT6_IMM(0xc2000000, dst_reg, imm);
606 break;
607 /*
608 * BPF_DIV / BPF_MOD
609 */
610 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
611 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
612 {
613 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
614
615 jit->seen |= SEEN_RET0;
616 /* ltr %src,%src (if src == 0 goto fail) */
617 EMIT2(0x1200, src_reg, src_reg);
618 /* jz <ret0> */
619 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
620 /* lhi %w0,0 */
621 EMIT4_IMM(0xa7080000, REG_W0, 0);
622 /* lr %w1,%dst */
623 EMIT2(0x1800, REG_W1, dst_reg);
624 /* dlr %w0,%src */
625 EMIT4(0xb9970000, REG_W0, src_reg);
626 /* llgfr %dst,%rc */
627 EMIT4(0xb9160000, dst_reg, rc_reg);
628 break;
629 }
630 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
631 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
632 {
633 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
634
635 jit->seen |= SEEN_RET0;
636 /* ltgr %src,%src (if src == 0 goto fail) */
637 EMIT4(0xb9020000, src_reg, src_reg);
638 /* jz <ret0> */
639 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
640 /* lghi %w0,0 */
641 EMIT4_IMM(0xa7090000, REG_W0, 0);
642 /* lgr %w1,%dst */
643 EMIT4(0xb9040000, REG_W1, dst_reg);
644 /* dlgr %w0,%dst */
645 EMIT4(0xb9870000, REG_W0, src_reg);
646 /* lgr %dst,%rc */
647 EMIT4(0xb9040000, dst_reg, rc_reg);
648 break;
649 }
650 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
651 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
652 {
653 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
654
655 if (imm == 1) {
656 if (BPF_OP(insn->code) == BPF_MOD)
657 /* lhgi %dst,0 */
658 EMIT4_IMM(0xa7090000, dst_reg, 0);
659 break;
660 }
661 /* lhi %w0,0 */
662 EMIT4_IMM(0xa7080000, REG_W0, 0);
663 /* lr %w1,%dst */
664 EMIT2(0x1800, REG_W1, dst_reg);
665 /* dl %w0,<d(imm)>(%l) */
666 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
667 EMIT_CONST_U32(imm));
668 /* llgfr %dst,%rc */
669 EMIT4(0xb9160000, dst_reg, rc_reg);
670 break;
671 }
672 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
673 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
674 {
675 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
676
677 if (imm == 1) {
678 if (BPF_OP(insn->code) == BPF_MOD)
679 /* lhgi %dst,0 */
680 EMIT4_IMM(0xa7090000, dst_reg, 0);
681 break;
682 }
683 /* lghi %w0,0 */
684 EMIT4_IMM(0xa7090000, REG_W0, 0);
685 /* lgr %w1,%dst */
686 EMIT4(0xb9040000, REG_W1, dst_reg);
687 /* dlg %w0,<d(imm)>(%l) */
688 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
689 EMIT_CONST_U64(imm));
690 /* lgr %dst,%rc */
691 EMIT4(0xb9040000, dst_reg, rc_reg);
692 break;
693 }
694 /*
695 * BPF_AND
696 */
697 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
698 /* nr %dst,%src */
699 EMIT2(0x1400, dst_reg, src_reg);
700 EMIT_ZERO(dst_reg);
701 break;
702 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
703 /* ngr %dst,%src */
704 EMIT4(0xb9800000, dst_reg, src_reg);
705 break;
706 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
707 /* nilf %dst,imm */
708 EMIT6_IMM(0xc00b0000, dst_reg, imm);
709 EMIT_ZERO(dst_reg);
710 break;
711 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
712 /* ng %dst,<d(imm)>(%l) */
713 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
714 EMIT_CONST_U64(imm));
715 break;
716 /*
717 * BPF_OR
718 */
719 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
720 /* or %dst,%src */
721 EMIT2(0x1600, dst_reg, src_reg);
722 EMIT_ZERO(dst_reg);
723 break;
724 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
725 /* ogr %dst,%src */
726 EMIT4(0xb9810000, dst_reg, src_reg);
727 break;
728 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
729 /* oilf %dst,imm */
730 EMIT6_IMM(0xc00d0000, dst_reg, imm);
731 EMIT_ZERO(dst_reg);
732 break;
733 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
734 /* og %dst,<d(imm)>(%l) */
735 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
736 EMIT_CONST_U64(imm));
737 break;
738 /*
739 * BPF_XOR
740 */
741 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
742 /* xr %dst,%src */
743 EMIT2(0x1700, dst_reg, src_reg);
744 EMIT_ZERO(dst_reg);
745 break;
746 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
747 /* xgr %dst,%src */
748 EMIT4(0xb9820000, dst_reg, src_reg);
749 break;
750 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
751 if (!imm)
752 break;
753 /* xilf %dst,imm */
754 EMIT6_IMM(0xc0070000, dst_reg, imm);
755 EMIT_ZERO(dst_reg);
756 break;
757 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
758 /* xg %dst,<d(imm)>(%l) */
759 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
760 EMIT_CONST_U64(imm));
761 break;
762 /*
763 * BPF_LSH
764 */
765 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
766 /* sll %dst,0(%src) */
767 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
768 EMIT_ZERO(dst_reg);
769 break;
770 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
771 /* sllg %dst,%dst,0(%src) */
772 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
773 break;
774 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
775 if (imm == 0)
776 break;
777 /* sll %dst,imm(%r0) */
778 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
779 EMIT_ZERO(dst_reg);
780 break;
781 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
782 if (imm == 0)
783 break;
784 /* sllg %dst,%dst,imm(%r0) */
785 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
786 break;
787 /*
788 * BPF_RSH
789 */
790 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
791 /* srl %dst,0(%src) */
792 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
793 EMIT_ZERO(dst_reg);
794 break;
795 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
796 /* srlg %dst,%dst,0(%src) */
797 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
798 break;
799 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
800 if (imm == 0)
801 break;
802 /* srl %dst,imm(%r0) */
803 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
804 EMIT_ZERO(dst_reg);
805 break;
806 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
807 if (imm == 0)
808 break;
809 /* srlg %dst,%dst,imm(%r0) */
810 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
811 break;
812 /*
813 * BPF_ARSH
814 */
815 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
816 /* srag %dst,%dst,0(%src) */
817 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
818 break;
819 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
820 if (imm == 0)
821 break;
822 /* srag %dst,%dst,imm(%r0) */
823 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
824 break;
825 /*
826 * BPF_NEG
827 */
828 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
829 /* lcr %dst,%dst */
830 EMIT2(0x1300, dst_reg, dst_reg);
831 EMIT_ZERO(dst_reg);
832 break;
833 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
834 /* lcgr %dst,%dst */
835 EMIT4(0xb9130000, dst_reg, dst_reg);
836 break;
837 /*
838 * BPF_FROM_BE/LE
839 */
840 case BPF_ALU | BPF_END | BPF_FROM_BE:
841 /* s390 is big endian, therefore only clear high order bytes */
842 switch (imm) {
843 case 16: /* dst = (u16) cpu_to_be16(dst) */
844 /* llghr %dst,%dst */
845 EMIT4(0xb9850000, dst_reg, dst_reg);
846 break;
847 case 32: /* dst = (u32) cpu_to_be32(dst) */
848 /* llgfr %dst,%dst */
849 EMIT4(0xb9160000, dst_reg, dst_reg);
850 break;
851 case 64: /* dst = (u64) cpu_to_be64(dst) */
852 break;
853 }
854 break;
855 case BPF_ALU | BPF_END | BPF_FROM_LE:
856 switch (imm) {
857 case 16: /* dst = (u16) cpu_to_le16(dst) */
858 /* lrvr %dst,%dst */
859 EMIT4(0xb91f0000, dst_reg, dst_reg);
860 /* srl %dst,16(%r0) */
861 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
862 /* llghr %dst,%dst */
863 EMIT4(0xb9850000, dst_reg, dst_reg);
864 break;
865 case 32: /* dst = (u32) cpu_to_le32(dst) */
866 /* lrvr %dst,%dst */
867 EMIT4(0xb91f0000, dst_reg, dst_reg);
868 /* llgfr %dst,%dst */
869 EMIT4(0xb9160000, dst_reg, dst_reg);
870 break;
871 case 64: /* dst = (u64) cpu_to_le64(dst) */
872 /* lrvgr %dst,%dst */
873 EMIT4(0xb90f0000, dst_reg, dst_reg);
874 break;
875 }
876 break;
877 /*
878 * BPF_ST(X)
879 */
880 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
881 /* stcy %src,off(%dst) */
882 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
883 jit->seen |= SEEN_MEM;
884 break;
885 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
886 /* sthy %src,off(%dst) */
887 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
888 jit->seen |= SEEN_MEM;
889 break;
890 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
891 /* sty %src,off(%dst) */
892 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
893 jit->seen |= SEEN_MEM;
894 break;
895 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
896 /* stg %src,off(%dst) */
897 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
898 jit->seen |= SEEN_MEM;
899 break;
900 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
901 /* lhi %w0,imm */
902 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
903 /* stcy %w0,off(dst) */
904 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
905 jit->seen |= SEEN_MEM;
906 break;
907 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
908 /* lhi %w0,imm */
909 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
910 /* sthy %w0,off(dst) */
911 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
912 jit->seen |= SEEN_MEM;
913 break;
914 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
915 /* llilf %w0,imm */
916 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
917 /* sty %w0,off(%dst) */
918 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
919 jit->seen |= SEEN_MEM;
920 break;
921 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
922 /* lgfi %w0,imm */
923 EMIT6_IMM(0xc0010000, REG_W0, imm);
924 /* stg %w0,off(%dst) */
925 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
926 jit->seen |= SEEN_MEM;
927 break;
928 /*
929 * BPF_STX XADD (atomic_add)
930 */
931 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
932 /* laal %w0,%src,off(%dst) */
933 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
934 dst_reg, off);
935 jit->seen |= SEEN_MEM;
936 break;
937 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
938 /* laalg %w0,%src,off(%dst) */
939 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
940 dst_reg, off);
941 jit->seen |= SEEN_MEM;
942 break;
943 /*
944 * BPF_LDX
945 */
946 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
947 /* llgc %dst,0(off,%src) */
948 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
949 jit->seen |= SEEN_MEM;
950 break;
951 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
952 /* llgh %dst,0(off,%src) */
953 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
954 jit->seen |= SEEN_MEM;
955 break;
956 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
957 /* llgf %dst,off(%src) */
958 jit->seen |= SEEN_MEM;
959 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
960 break;
961 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
962 /* lg %dst,0(off,%src) */
963 jit->seen |= SEEN_MEM;
964 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
965 break;
966 /*
967 * BPF_JMP / CALL
968 */
969 case BPF_JMP | BPF_CALL:
970 {
971 /*
972 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
973 */
974 const u64 func = (u64)__bpf_call_base + imm;
975
976 REG_SET_SEEN(BPF_REG_5);
977 jit->seen |= SEEN_FUNC;
978 /* lg %w1,<d(imm)>(%l) */
979 EMIT6_DISP(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
980 EMIT_CONST_U64(func));
981 /* basr %r14,%w1 */
982 EMIT2(0x0d00, REG_14, REG_W1);
983 /* lgr %b0,%r2: load return value into %b0 */
984 EMIT4(0xb9040000, BPF_REG_0, REG_2);
985 break;
986 }
987 case BPF_JMP | BPF_CALL | BPF_X:
988 /*
989 * Implicit input:
990 * B1: pointer to ctx
991 * B2: pointer to bpf_array
992 * B3: index in bpf_array
993 */
994 jit->seen |= SEEN_TAIL_CALL;
995
996 /*
997 * if (index >= array->map.max_entries)
998 * goto out;
999 */
1000
1001 /* llgf %w1,map.max_entries(%b2) */
1002 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1003 offsetof(struct bpf_array, map.max_entries));
1004 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1005 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3,
1006 REG_W1, 0, 0xa);
1007
1008 /*
1009 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1010 * goto out;
1011 */
1012
1013 if (jit->seen & SEEN_STACK)
1014 off = STK_OFF_TCCNT + STK_OFF;
1015 else
1016 off = STK_OFF_TCCNT;
1017 /* lhi %w0,1 */
1018 EMIT4_IMM(0xa7080000, REG_W0, 1);
1019 /* laal %w1,%w0,off(%r15) */
1020 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1021 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1022 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1023 MAX_TAIL_CALL_CNT, 0, 0x2);
1024
1025 /*
1026 * prog = array->prog[index];
1027 * if (prog == NULL)
1028 * goto out;
1029 */
1030
1031 /* sllg %r1,%b3,3: %r1 = index * 8 */
1032 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3);
1033 /* lg %r1,prog(%b2,%r1) */
1034 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1035 REG_1, offsetof(struct bpf_array, prog));
1036 /* clgij %r1,0,0x8,label0 */
1037 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1038
1039 /*
1040 * Restore registers before calling function
1041 */
1042 save_restore_regs(jit, REGS_RESTORE);
1043
1044 /*
1045 * goto *(prog->bpf_func + tail_call_start);
1046 */
1047
1048 /* lg %r1,bpf_func(%r1) */
1049 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1050 offsetof(struct bpf_prog, bpf_func));
1051 /* bc 0xf,tail_call_start(%r1) */
1052 _EMIT4(0x47f01000 + jit->tail_call_start);
1053 /* out: */
1054 jit->labels[0] = jit->prg;
1055 break;
1056 case BPF_JMP | BPF_EXIT: /* return b0 */
1057 last = (i == fp->len - 1) ? 1 : 0;
1058 if (last && !(jit->seen & SEEN_RET0))
1059 break;
1060 /* j <exit> */
1061 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1062 break;
1063 /*
1064 * Branch relative (number of skipped instructions) to offset on
1065 * condition.
1066 *
1067 * Condition code to mask mapping:
1068 *
1069 * CC | Description | Mask
1070 * ------------------------------
1071 * 0 | Operands equal | 8
1072 * 1 | First operand low | 4
1073 * 2 | First operand high | 2
1074 * 3 | Unused | 1
1075 *
1076 * For s390x relative branches: ip = ip + off_bytes
1077 * For BPF relative branches: insn = insn + off_insns + 1
1078 *
1079 * For example for s390x with offset 0 we jump to the branch
1080 * instruction itself (loop) and for BPF with offset 0 we
1081 * branch to the instruction behind the branch.
1082 */
1083 case BPF_JMP | BPF_JA: /* if (true) */
1084 mask = 0xf000; /* j */
1085 goto branch_oc;
1086 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1087 mask = 0x2000; /* jh */
1088 goto branch_ks;
1089 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1090 mask = 0xa000; /* jhe */
1091 goto branch_ks;
1092 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1093 mask = 0x2000; /* jh */
1094 goto branch_ku;
1095 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1096 mask = 0xa000; /* jhe */
1097 goto branch_ku;
1098 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1099 mask = 0x7000; /* jne */
1100 goto branch_ku;
1101 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1102 mask = 0x8000; /* je */
1103 goto branch_ku;
1104 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1105 mask = 0x7000; /* jnz */
1106 /* lgfi %w1,imm (load sign extend imm) */
1107 EMIT6_IMM(0xc0010000, REG_W1, imm);
1108 /* ngr %w1,%dst */
1109 EMIT4(0xb9800000, REG_W1, dst_reg);
1110 goto branch_oc;
1111
1112 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1113 mask = 0x2000; /* jh */
1114 goto branch_xs;
1115 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1116 mask = 0xa000; /* jhe */
1117 goto branch_xs;
1118 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1119 mask = 0x2000; /* jh */
1120 goto branch_xu;
1121 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1122 mask = 0xa000; /* jhe */
1123 goto branch_xu;
1124 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1125 mask = 0x7000; /* jne */
1126 goto branch_xu;
1127 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1128 mask = 0x8000; /* je */
1129 goto branch_xu;
1130 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1131 mask = 0x7000; /* jnz */
1132 /* ngrk %w1,%dst,%src */
1133 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1134 goto branch_oc;
1135 branch_ks:
1136 /* lgfi %w1,imm (load sign extend imm) */
1137 EMIT6_IMM(0xc0010000, REG_W1, imm);
1138 /* cgrj %dst,%w1,mask,off */
1139 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1140 break;
1141 branch_ku:
1142 /* lgfi %w1,imm (load sign extend imm) */
1143 EMIT6_IMM(0xc0010000, REG_W1, imm);
1144 /* clgrj %dst,%w1,mask,off */
1145 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1146 break;
1147 branch_xs:
1148 /* cgrj %dst,%src,mask,off */
1149 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1150 break;
1151 branch_xu:
1152 /* clgrj %dst,%src,mask,off */
1153 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1154 break;
1155 branch_oc:
1156 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1157 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1158 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1159 break;
1160 /*
1161 * BPF_LD
1162 */
1163 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1164 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1165 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1166 func_addr = __pa(sk_load_byte_pos);
1167 else
1168 func_addr = __pa(sk_load_byte);
1169 goto call_fn;
1170 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1171 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1172 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1173 func_addr = __pa(sk_load_half_pos);
1174 else
1175 func_addr = __pa(sk_load_half);
1176 goto call_fn;
1177 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1178 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1179 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1180 func_addr = __pa(sk_load_word_pos);
1181 else
1182 func_addr = __pa(sk_load_word);
1183 goto call_fn;
1184 call_fn:
1185 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1186 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1187
1188 /*
1189 * Implicit input:
1190 * BPF_REG_6 (R7) : skb pointer
1191 * REG_SKB_DATA (R12): skb data pointer
1192 *
1193 * Calculated input:
1194 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1195 * BPF_REG_5 (R6) : return address
1196 *
1197 * Output:
1198 * BPF_REG_0 (R14): data read from skb
1199 *
1200 * Scratch registers (BPF_REG_1-5)
1201 */
1202
1203 /* Call function: llilf %w1,func_addr */
1204 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1205
1206 /* Offset: lgfi %b2,imm */
1207 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1208 if (BPF_MODE(insn->code) == BPF_IND)
1209 /* agfr %b2,%src (%src is s32 here) */
1210 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1211
1212 /* basr %b5,%w1 (%b5 is call saved) */
1213 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1214
1215 /*
1216 * Note: For fast access we jump directly after the
1217 * jnz instruction from bpf_jit.S
1218 */
1219 /* jnz <ret0> */
1220 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1221 break;
1222 default: /* too complex, give up */
1223 pr_err("Unknown opcode %02x\n", insn->code);
1224 return -1;
1225 }
1226 return insn_count;
1227 }
1228
1229 /*
1230 * Compile eBPF program into s390x code
1231 */
1232 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1233 {
1234 int i, insn_count;
1235
1236 jit->lit = jit->lit_start;
1237 jit->prg = 0;
1238
1239 bpf_jit_prologue(jit);
1240 for (i = 0; i < fp->len; i += insn_count) {
1241 insn_count = bpf_jit_insn(jit, fp, i);
1242 if (insn_count < 0)
1243 return -1;
1244 jit->addrs[i + 1] = jit->prg; /* Next instruction address */
1245 }
1246 bpf_jit_epilogue(jit);
1247
1248 jit->lit_start = jit->prg;
1249 jit->size = jit->lit;
1250 jit->size_prg = jit->prg;
1251 return 0;
1252 }
1253
1254 /*
1255 * Classic BPF function stub. BPF programs will be converted into
1256 * eBPF and then bpf_int_jit_compile() will be called.
1257 */
1258 void bpf_jit_compile(struct bpf_prog *fp)
1259 {
1260 }
1261
1262 /*
1263 * Compile eBPF program "fp"
1264 */
1265 void bpf_int_jit_compile(struct bpf_prog *fp)
1266 {
1267 struct bpf_binary_header *header;
1268 struct bpf_jit jit;
1269 int pass;
1270
1271 if (!bpf_jit_enable)
1272 return;
1273 memset(&jit, 0, sizeof(jit));
1274 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1275 if (jit.addrs == NULL)
1276 return;
1277 /*
1278 * Three initial passes:
1279 * - 1/2: Determine clobbered registers
1280 * - 3: Calculate program size and addrs arrray
1281 */
1282 for (pass = 1; pass <= 3; pass++) {
1283 if (bpf_jit_prog(&jit, fp))
1284 goto free_addrs;
1285 }
1286 /*
1287 * Final pass: Allocate and generate program
1288 */
1289 if (jit.size >= BPF_SIZE_MAX)
1290 goto free_addrs;
1291 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1292 if (!header)
1293 goto free_addrs;
1294 if (bpf_jit_prog(&jit, fp))
1295 goto free_addrs;
1296 if (bpf_jit_enable > 1) {
1297 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1298 if (jit.prg_buf)
1299 print_fn_code(jit.prg_buf, jit.size_prg);
1300 }
1301 if (jit.prg_buf) {
1302 set_memory_ro((unsigned long)header, header->pages);
1303 fp->bpf_func = (void *) jit.prg_buf;
1304 fp->jited = true;
1305 }
1306 free_addrs:
1307 kfree(jit.addrs);
1308 }
1309
1310 /*
1311 * Free eBPF program
1312 */
1313 void bpf_jit_free(struct bpf_prog *fp)
1314 {
1315 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1316 struct bpf_binary_header *header = (void *)addr;
1317
1318 if (!fp->jited)
1319 goto free_filter;
1320
1321 set_memory_rw(addr, header->pages);
1322 bpf_jit_binary_free(header);
1323
1324 free_filter:
1325 bpf_prog_unlock_free(fp);
1326 }
Linux with added FPC-III support