drivers/gpio/gpio-vf610.c

   1 /*
   2  * Freescale vf610 GPIO support through PORT and GPIO
   3  *
   4  * Copyright (c) 2014 Toradex AG.
   5  *
   6  * Author: Stefan Agner <stefan@agner.ch>.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/gpio.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/irq.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_irq.h>
  30
  31 #define VF610_GPIO_PER_PORT             32
  32
  33 struct fsl_gpio_soc_data {
  34         /* SoCs has a Port Data Direction Register (PDDR) */
  35         bool have_paddr;
  36 };
  37
  38 struct vf610_gpio_port {
  39         struct gpio_chip gc;
  40         struct irq_chip ic;
  41         void __iomem *base;
  42         void __iomem *gpio_base;
  43         const struct fsl_gpio_soc_data *sdata;
  44         u8 irqc[VF610_GPIO_PER_PORT];
  45         int irq;
  46 };
  47
  48 #define GPIO_PDOR               0x00
  49 #define GPIO_PSOR               0x04
  50 #define GPIO_PCOR               0x08
  51 #define GPIO_PTOR               0x0c
  52 #define GPIO_PDIR               0x10
  53 #define GPIO_PDDR               0x14
  54
  55 #define PORT_PCR(n)             ((n) * 0x4)
  56 #define PORT_PCR_IRQC_OFFSET    16
  57
  58 #define PORT_ISFR               0xa0
  59 #define PORT_DFER               0xc0
  60 #define PORT_DFCR               0xc4
  61 #define PORT_DFWR               0xc8
  62
  63 #define PORT_INT_OFF            0x0
  64 #define PORT_INT_LOGIC_ZERO     0x8
  65 #define PORT_INT_RISING_EDGE    0x9
  66 #define PORT_INT_FALLING_EDGE   0xa
  67 #define PORT_INT_EITHER_EDGE    0xb
  68 #define PORT_INT_LOGIC_ONE      0xc
  69
  70 static const struct fsl_gpio_soc_data imx_data = {
  71         .have_paddr = true,
  72 };
  73
  74 static const struct of_device_id vf610_gpio_dt_ids[] = {
  75         { .compatible = "fsl,vf610-gpio",       .data = NULL, },
  76         { .compatible = "fsl,imx7ulp-gpio",     .data = &imx_data, },
  77         { /* sentinel */ }
  78 };
  79
  80 static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
  81 {
  82         writel_relaxed(val, reg);
  83 }
  84
  85 static inline u32 vf610_gpio_readl(void __iomem *reg)
  86 {
  87         return readl_relaxed(reg);
  88 }
  89
  90 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  91 {
  92         struct vf610_gpio_port *port = gpiochip_get_data(gc);
  93         unsigned long mask = BIT(gpio);
  94         void __iomem *addr;
  95
  96         if (port->sdata && port->sdata->have_paddr) {
  97                 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
  98                 addr = mask ? port->gpio_base + GPIO_PDOR :
  99                               port->gpio_base + GPIO_PDIR;
 100                 return !!(vf610_gpio_readl(addr) & BIT(gpio));
 101         } else {
 102                 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
 103                                            & BIT(gpio));
 104         }
 105 }
 106
 107 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 108 {
 109         struct vf610_gpio_port *port = gpiochip_get_data(gc);
 110         unsigned long mask = BIT(gpio);
 111
 112         if (val)
 113                 vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
 114         else
 115                 vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
 116 }
 117
 118 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 119 {
 120         struct vf610_gpio_port *port = gpiochip_get_data(chip);
 121         unsigned long mask = BIT(gpio);
 122         u32 val;
 123
 124         if (port->sdata && port->sdata->have_paddr) {
 125                 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
 126                 val &= ~mask;
 127                 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
 128         }
 129
 130         return pinctrl_gpio_direction_input(chip->base + gpio);
 131 }
 132
 133 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
 134                                        int value)
 135 {
 136         struct vf610_gpio_port *port = gpiochip_get_data(chip);
 137         unsigned long mask = BIT(gpio);
 138
 139         if (port->sdata && port->sdata->have_paddr)
 140                 vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
 141
 142         vf610_gpio_set(chip, gpio, value);
 143
 144         return pinctrl_gpio_direction_output(chip->base + gpio);
 145 }
 146
 147 static void vf610_gpio_irq_handler(struct irq_desc *desc)
 148 {
 149         struct vf610_gpio_port *port =
 150                 gpiochip_get_data(irq_desc_get_handler_data(desc));
 151         struct irq_chip *chip = irq_desc_get_chip(desc);
 152         int pin;
 153         unsigned long irq_isfr;
 154
 155         chained_irq_enter(chip, desc);
 156
 157         irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
 158
 159         for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
 160                 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
 161
 162                 generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
 163         }
 164
 165         chained_irq_exit(chip, desc);
 166 }
 167
 168 static void vf610_gpio_irq_ack(struct irq_data *d)
 169 {
 170         struct vf610_gpio_port *port =
 171                 gpiochip_get_data(irq_data_get_irq_chip_data(d));
 172         int gpio = d->hwirq;
 173
 174         vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
 175 }
 176
 177 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
 178 {
 179         struct vf610_gpio_port *port =
 180                 gpiochip_get_data(irq_data_get_irq_chip_data(d));
 181         u8 irqc;
 182
 183         switch (type) {
 184         case IRQ_TYPE_EDGE_RISING:
 185                 irqc = PORT_INT_RISING_EDGE;
 186                 break;
 187         case IRQ_TYPE_EDGE_FALLING:
 188                 irqc = PORT_INT_FALLING_EDGE;
 189                 break;
 190         case IRQ_TYPE_EDGE_BOTH:
 191                 irqc = PORT_INT_EITHER_EDGE;
 192                 break;
 193         case IRQ_TYPE_LEVEL_LOW:
 194                 irqc = PORT_INT_LOGIC_ZERO;
 195                 break;
 196         case IRQ_TYPE_LEVEL_HIGH:
 197                 irqc = PORT_INT_LOGIC_ONE;
 198                 break;
 199         default:
 200                 return -EINVAL;
 201         }
 202
 203         port->irqc[d->hwirq] = irqc;
 204
 205         if (type & IRQ_TYPE_LEVEL_MASK)
 206                 irq_set_handler_locked(d, handle_level_irq);
 207         else
 208                 irq_set_handler_locked(d, handle_edge_irq);
 209
 210         return 0;
 211 }
 212
 213 static void vf610_gpio_irq_mask(struct irq_data *d)
 214 {
 215         struct vf610_gpio_port *port =
 216                 gpiochip_get_data(irq_data_get_irq_chip_data(d));
 217         void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
 218
 219         vf610_gpio_writel(0, pcr_base);
 220 }
 221
 222 static void vf610_gpio_irq_unmask(struct irq_data *d)
 223 {
 224         struct vf610_gpio_port *port =
 225                 gpiochip_get_data(irq_data_get_irq_chip_data(d));
 226         void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
 227
 228         vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
 229                           pcr_base);
 230 }
 231
 232 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
 233 {
 234         struct vf610_gpio_port *port =
 235                 gpiochip_get_data(irq_data_get_irq_chip_data(d));
 236
 237         if (enable)
 238                 enable_irq_wake(port->irq);
 239         else
 240                 disable_irq_wake(port->irq);
 241
 242         return 0;
 243 }
 244
 245 static int vf610_gpio_probe(struct platform_device *pdev)
 246 {
 247         struct device *dev = &pdev->dev;
 248         struct device_node *np = dev->of_node;
 249         struct vf610_gpio_port *port;
 250         struct resource *iores;
 251         struct gpio_chip *gc;
 252         struct irq_chip *ic;
 253         int i;
 254         int ret;
 255
 256         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 257         if (!port)
 258                 return -ENOMEM;
 259
 260         port->sdata = of_device_get_match_data(dev);
 261         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 262         port->base = devm_ioremap_resource(dev, iores);
 263         if (IS_ERR(port->base))
 264                 return PTR_ERR(port->base);
 265
 266         iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 267         port->gpio_base = devm_ioremap_resource(dev, iores);
 268         if (IS_ERR(port->gpio_base))
 269                 return PTR_ERR(port->gpio_base);
 270
 271         port->irq = platform_get_irq(pdev, 0);
 272         if (port->irq < 0)
 273                 return port->irq;
 274
 275         gc = &port->gc;
 276         gc->of_node = np;
 277         gc->parent = dev;
 278         gc->label = "vf610-gpio";
 279         gc->ngpio = VF610_GPIO_PER_PORT;
 280         gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
 281
 282         gc->request = gpiochip_generic_request;
 283         gc->free = gpiochip_generic_free;
 284         gc->direction_input = vf610_gpio_direction_input;
 285         gc->get = vf610_gpio_get;
 286         gc->direction_output = vf610_gpio_direction_output;
 287         gc->set = vf610_gpio_set;
 288
 289         ic = &port->ic;
 290         ic->name = "gpio-vf610";
 291         ic->irq_ack = vf610_gpio_irq_ack;
 292         ic->irq_mask = vf610_gpio_irq_mask;
 293         ic->irq_unmask = vf610_gpio_irq_unmask;
 294         ic->irq_set_type = vf610_gpio_irq_set_type;
 295         ic->irq_set_wake = vf610_gpio_irq_set_wake;
 296
 297         ret = gpiochip_add_data(gc, port);
 298         if (ret < 0)
 299                 return ret;
 300
 301         /* Mask all GPIO interrupts */
 302         for (i = 0; i < gc->ngpio; i++)
 303                 vf610_gpio_writel(0, port->base + PORT_PCR(i));
 304
 305         /* Clear the interrupt status register for all GPIO's */
 306         vf610_gpio_writel(~0, port->base + PORT_ISFR);
 307
 308         ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE);
 309         if (ret) {
 310                 dev_err(dev, "failed to add irqchip\n");
 311                 gpiochip_remove(gc);
 312                 return ret;
 313         }
 314         gpiochip_set_chained_irqchip(gc, ic, port->irq,
 315                                      vf610_gpio_irq_handler);
 316
 317         return 0;
 318 }
 319
 320 static struct platform_driver vf610_gpio_driver = {
 321         .driver         = {
 322                 .name   = "gpio-vf610",
 323                 .of_match_table = vf610_gpio_dt_ids,
 324         },
 325         .probe          = vf610_gpio_probe,
 326 };
 327
 328 builtin_platform_driver(vf610_gpio_driver);