arch/arm/mach-ux500/cpu-db8500.c

   1 /*
   2  * Copyright (C) 2008-2009 ST-Ericsson SA
   3  *
   4  * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/amba/bus.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/mach/map.h>
  21 #include <asm/pmu.h>
  22 #include <plat/gpio-nomadik.h>
  23 #include <mach/hardware.h>
  24 #include <mach/setup.h>
  25 #include <mach/devices.h>
  26 #include <mach/usb.h>
  27 #include <mach/db8500-regs.h>
  28
  29 #include "devices-db8500.h"
  30 #include "ste-dma40-db8500.h"
  31
  32 /* minimum static i/o mapping required to boot U8500 platforms */
  33 static struct map_desc u8500_uart_io_desc[] __initdata = {
  34         __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
  35         __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
  36 };
  37
  38 static struct map_desc u8500_io_desc[] __initdata = {
  39         /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
  40         __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
  41         __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
  42         __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
  43         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
  44         __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
  45
  46         __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
  47         __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
  48         __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
  49         __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
  50         __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
  51
  52         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
  53         __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
  54         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
  55         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
  56         __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
  57         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
  58 };
  59
  60 void __init u8500_map_io(void)
  61 {
  62         /*
  63          * Map the UARTs early so that the DEBUG_LL stuff continues to work.
  64          */
  65         iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
  66
  67         ux500_map_io();
  68
  69         iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
  70
  71         _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
  72 }
  73
  74 static struct resource db8500_pmu_resources[] = {
  75         [0] = {
  76                 .start          = IRQ_DB8500_PMU,
  77                 .end            = IRQ_DB8500_PMU,
  78                 .flags          = IORESOURCE_IRQ,
  79         },
  80 };
  81
  82 /*
  83  * The PMU IRQ lines of two cores are wired together into a single interrupt.
  84  * Bounce the interrupt to the other core if it's not ours.
  85  */
  86 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
  87 {
  88         irqreturn_t ret = handler(irq, dev);
  89         int other = !smp_processor_id();
  90
  91         if (ret == IRQ_NONE && cpu_online(other))
  92                 irq_set_affinity(irq, cpumask_of(other));
  93
  94         /*
  95          * We should be able to get away with the amount of IRQ_NONEs we give,
  96          * while still having the spurious IRQ detection code kick in if the
  97          * interrupt really starts hitting spuriously.
  98          */
  99         return ret;
 100 }
 101
 102 static struct arm_pmu_platdata db8500_pmu_platdata = {
 103         .handle_irq             = db8500_pmu_handler,
 104 };
 105
 106 static struct platform_device db8500_pmu_device = {
 107         .name                   = "arm-pmu",
 108         .id                     = ARM_PMU_DEVICE_CPU,
 109         .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
 110         .resource               = db8500_pmu_resources,
 111         .dev.platform_data      = &db8500_pmu_platdata,
 112 };
 113
 114 static struct platform_device db8500_prcmu_device = {
 115         .name                   = "db8500-prcmu",
 116 };
 117
 118 static struct platform_device *platform_devs[] __initdata = {
 119         &u8500_dma40_device,
 120         &db8500_pmu_device,
 121         &db8500_prcmu_device,
 122 };
 123
 124 static resource_size_t __initdata db8500_gpio_base[] = {
 125         U8500_GPIOBANK0_BASE,
 126         U8500_GPIOBANK1_BASE,
 127         U8500_GPIOBANK2_BASE,
 128         U8500_GPIOBANK3_BASE,
 129         U8500_GPIOBANK4_BASE,
 130         U8500_GPIOBANK5_BASE,
 131         U8500_GPIOBANK6_BASE,
 132         U8500_GPIOBANK7_BASE,
 133         U8500_GPIOBANK8_BASE,
 134 };
 135
 136 static void __init db8500_add_gpios(struct device *parent)
 137 {
 138         struct nmk_gpio_platform_data pdata = {
 139                 .supports_sleepmode = true,
 140         };
 141
 142         dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
 143                          IRQ_DB8500_GPIO0, &pdata);
 144 }
 145
 146 static int usb_db8500_rx_dma_cfg[] = {
 147         DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
 148         DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
 149         DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
 150         DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
 151         DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
 152         DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
 153         DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
 154         DB8500_DMA_DEV39_USB_OTG_IEP_8
 155 };
 156
 157 static int usb_db8500_tx_dma_cfg[] = {
 158         DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
 159         DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
 160         DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
 161         DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
 162         DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
 163         DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
 164         DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
 165         DB8500_DMA_DEV39_USB_OTG_OEP_8
 166 };
 167
 168 static const char *db8500_read_soc_id(void)
 169 {
 170         void __iomem *uid = __io_address(U8500_BB_UID_BASE);
 171
 172         return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
 173                          readl((u32 *)uid+1),
 174                          readl((u32 *)uid+1), readl((u32 *)uid+2),
 175                          readl((u32 *)uid+3), readl((u32 *)uid+4));
 176 }
 177
 178 static struct device * __init db8500_soc_device_init(void)
 179 {
 180         const char *soc_id = db8500_read_soc_id();
 181
 182         return ux500_soc_device_init(soc_id);
 183 }
 184
 185 /*
 186  * This function is called from the board init
 187  */
 188 struct device * __init u8500_init_devices(void)
 189 {
 190         struct device *parent;
 191         int i;
 192
 193         parent = db8500_soc_device_init();
 194
 195         db8500_add_rtc(parent);
 196         db8500_add_gpios(parent);
 197         db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
 198
 199         platform_device_register_data(parent,
 200                 "cpufreq-u8500", -1, NULL, 0);
 201
 202         for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
 203                 platform_devs[i]->dev.parent = parent;
 204
 205         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 206
 207         return parent;
 208 }