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NFS: Don't clear desc->pg_moreio in nfs_do_recoalesce()
[linux/fpc-iii.git] / drivers / iio / adc / max1363.c
blob1b3b74be5c2007c821d2a6839fb62f9adc8ddfec
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * Driver for max1363 and similar chips.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/kernel.h>
21 #include <linux/sysfs.h>
22 #include <linux/list.h>
23 #include <linux/i2c.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
26 #include <linux/err.h>
27 #include <linux/module.h>
28
29 #include <linux/iio/iio.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/events.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/driver.h>
34 #include <linux/iio/kfifo_buf.h>
35 #include <linux/iio/trigger_consumer.h>
36 #include <linux/iio/triggered_buffer.h>
37
38 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
39
40 /* There is a fair bit more defined here than currently
41 * used, but the intention is to support everything these
42 * chips do in the long run */
43
44 /* see data sheets */
45 /* max1363 and max1236, max1237, max1238, max1239 */
46 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
47 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
48 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
49 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
50 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
51 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
52
53 /* think about including max11600 etc - more settings */
54 #define MAX1363_SETUP_EXT_CLOCK 0x08
55 #define MAX1363_SETUP_INT_CLOCK 0x00
56 #define MAX1363_SETUP_UNIPOLAR 0x00
57 #define MAX1363_SETUP_BIPOLAR 0x04
58 #define MAX1363_SETUP_RESET 0x00
59 #define MAX1363_SETUP_NORESET 0x02
60 /* max1363 only - though don't care on others.
61 * For now monitor modes are not implemented as the relevant
62 * line is not connected on my test board.
63 * The definitions are here as I intend to add this soon.
64 */
65 #define MAX1363_SETUP_MONITOR_SETUP 0x01
66
67 /* Specific to the max1363 */
68 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
69 #define MAX1363_MON_INT_ENABLE 0x01
70
71 /* defined for readability reasons */
72 /* All chips */
73 #define MAX1363_CONFIG_BYTE(a) ((a))
74
75 #define MAX1363_CONFIG_SE 0x01
76 #define MAX1363_CONFIG_DE 0x00
77 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
78 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
79 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
80 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
81 /* max123{6-9} only */
82 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
83
84 /* max1363 only - merely part of channel selects or don't care for others */
85 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
86
87 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
88
89 /* max1363 strictly 0x06 - but doesn't matter */
90 #define MAX1363_CHANNEL_SEL_MASK 0x1E
91 #define MAX1363_SCAN_MASK 0x60
92 #define MAX1363_SE_DE_MASK 0x01
93
94 #define MAX1363_MAX_CHANNELS 25
95 /**
96 * struct max1363_mode - scan mode information
97 * @conf: The corresponding value of the configuration register
98 * @modemask: Bit mask corresponding to channels enabled in this mode
99 */
100 struct max1363_mode {
101 int8_t conf;
102 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
103 };
104
105 /* This must be maintained along side the max1363_mode_table in max1363_core */
106 enum max1363_modes {
107 /* Single read of a single channel */
108 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
109 /* Differential single read */
110 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
111 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
112 /* Scan to channel and mid to channel where overlapping */
113 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
114 s6to7, s0to7, s6to8, s0to8, s6to9,
115 s0to9, s6to10, s0to10, s6to11, s0to11,
116 /* Differential scan to channel and mid to channel where overlapping */
117 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
118 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
119 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
120 d7m6to11m10, d1m0to11m10,
121 };
122
123 /**
124 * struct max1363_chip_info - chip specifc information
125 * @info: iio core function callbacks structure
126 * @channels: channel specification
127 * @num_channels: number of channels
128 * @mode_list: array of available scan modes
129 * @default_mode: the scan mode in which the chip starts up
130 * @int_vref_mv: the internal reference voltage
131 * @num_modes: number of modes
132 * @bits: accuracy of the adc in bits
133 */
134 struct max1363_chip_info {
135 const struct iio_info *info;
136 const struct iio_chan_spec *channels;
137 int num_channels;
138 const enum max1363_modes *mode_list;
139 enum max1363_modes default_mode;
140 u16 int_vref_mv;
141 u8 num_modes;
142 u8 bits;
143 };
144
145 /**
146 * struct max1363_state - driver instance specific data
147 * @client: i2c_client
148 * @setupbyte: cache of current device setup byte
149 * @configbyte: cache of current device config byte
150 * @chip_info: chip model specific constants, available modes, etc.
151 * @current_mode: the scan mode of this chip
152 * @requestedmask: a valid requested set of channels
153 * @reg: supply regulator
154 * @monitor_on: whether monitor mode is enabled
155 * @monitor_speed: parameter corresponding to device monitor speed setting
156 * @mask_high: bitmask for enabled high thresholds
157 * @mask_low: bitmask for enabled low thresholds
158 * @thresh_high: high threshold values
159 * @thresh_low: low threshold values
160 * @vref: Reference voltage regulator
161 * @vref_uv: Actual (external or internal) reference voltage
162 * @send: function used to send data to the chip
163 * @recv: function used to receive data from the chip
164 */
165 struct max1363_state {
166 struct i2c_client *client;
167 u8 setupbyte;
168 u8 configbyte;
169 const struct max1363_chip_info *chip_info;
170 const struct max1363_mode *current_mode;
171 u32 requestedmask;
172 struct regulator *reg;
173
174 /* Using monitor modes and buffer at the same time is
175 currently not supported */
176 bool monitor_on;
177 unsigned int monitor_speed:3;
178 u8 mask_high;
179 u8 mask_low;
180 /* 4x unipolar first then the fours bipolar ones */
181 s16 thresh_high[8];
182 s16 thresh_low[8];
183 struct regulator *vref;
184 u32 vref_uv;
185 int (*send)(const struct i2c_client *client,
186 const char *buf, int count);
187 int (*recv)(const struct i2c_client *client,
188 char *buf, int count);
189 };
190
191 #define MAX1363_MODE_SINGLE(_num, _mask) { \
192 .conf = MAX1363_CHANNEL_SEL(_num) \
193 | MAX1363_CONFIG_SCAN_SINGLE_1 \
194 | MAX1363_CONFIG_SE, \
195 .modemask[0] = _mask, \
196 }
197
198 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
199 .conf = MAX1363_CHANNEL_SEL(_num) \
200 | MAX1363_CONFIG_SCAN_TO_CS \
201 | MAX1363_CONFIG_SE, \
202 .modemask[0] = _mask, \
203 }
204
205 /* note not available for max1363 hence naming */
206 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
207 .conf = MAX1363_CHANNEL_SEL(_num) \
208 | MAX1236_SCAN_MID_TO_CHANNEL \
209 | MAX1363_CONFIG_SE, \
210 .modemask[0] = _mask \
211 }
212
213 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
214 .conf = MAX1363_CHANNEL_SEL(_nump) \
215 | MAX1363_CONFIG_SCAN_SINGLE_1 \
216 | MAX1363_CONFIG_DE, \
217 .modemask[0] = _mask \
218 }
219
220 /* Can't think how to automate naming so specify for now */
221 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
222 .conf = MAX1363_CHANNEL_SEL(_num) \
223 | MAX1363_CONFIG_SCAN_TO_CS \
224 | MAX1363_CONFIG_DE, \
225 .modemask[0] = _mask \
226 }
227
228 /* note only available for max1363 hence naming */
229 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
230 .conf = MAX1363_CHANNEL_SEL(_num) \
231 | MAX1236_SCAN_MID_TO_CHANNEL \
232 | MAX1363_CONFIG_SE, \
233 .modemask[0] = _mask \
234 }
235
236 static const struct max1363_mode max1363_mode_table[] = {
237 /* All of the single channel options first */
238 MAX1363_MODE_SINGLE(0, 1 << 0),
239 MAX1363_MODE_SINGLE(1, 1 << 1),
240 MAX1363_MODE_SINGLE(2, 1 << 2),
241 MAX1363_MODE_SINGLE(3, 1 << 3),
242 MAX1363_MODE_SINGLE(4, 1 << 4),
243 MAX1363_MODE_SINGLE(5, 1 << 5),
244 MAX1363_MODE_SINGLE(6, 1 << 6),
245 MAX1363_MODE_SINGLE(7, 1 << 7),
246 MAX1363_MODE_SINGLE(8, 1 << 8),
247 MAX1363_MODE_SINGLE(9, 1 << 9),
248 MAX1363_MODE_SINGLE(10, 1 << 10),
249 MAX1363_MODE_SINGLE(11, 1 << 11),
250
251 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
252 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
253 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
254 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
255 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
256 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
257 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
258 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
259 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
260 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
261 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
262 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
263
264 /* The multichannel scans next */
265 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
266 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
268 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
282
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
297 };
298
299 static const struct max1363_mode
300 *max1363_match_mode(const unsigned long *mask,
301 const struct max1363_chip_info *ci)
302 {
303 int i;
304 if (mask)
305 for (i = 0; i < ci->num_modes; i++)
306 if (bitmap_subset(mask,
307 max1363_mode_table[ci->mode_list[i]].
308 modemask,
309 MAX1363_MAX_CHANNELS))
310 return &max1363_mode_table[ci->mode_list[i]];
311 return NULL;
312 }
313
314 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
315 int count)
316 {
317 int i, err;
318
319 for (i = err = 0; err == 0 && i < count; ++i)
320 err = i2c_smbus_write_byte(client, buf[i]);
321
322 return err ? err : count;
323 }
324
325 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
326 int count)
327 {
328 int i, ret;
329
330 for (i = 0; i < count; ++i) {
331 ret = i2c_smbus_read_byte(client);
332 if (ret < 0)
333 return ret;
334 buf[i] = ret;
335 }
336
337 return count;
338 }
339
340 static int max1363_write_basic_config(struct max1363_state *st)
341 {
342 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
343
344 return st->send(st->client, tx_buf, 2);
345 }
346
347 static int max1363_set_scan_mode(struct max1363_state *st)
348 {
349 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
350 | MAX1363_SCAN_MASK
351 | MAX1363_SE_DE_MASK);
352 st->configbyte |= st->current_mode->conf;
353
354 return max1363_write_basic_config(st);
355 }
356
357 static int max1363_read_single_chan(struct iio_dev *indio_dev,
358 struct iio_chan_spec const *chan,
359 int *val,
360 long m)
361 {
362 int ret = 0;
363 s32 data;
364 u8 rxbuf[2];
365 struct max1363_state *st = iio_priv(indio_dev);
366 struct i2c_client *client = st->client;
367
368 mutex_lock(&indio_dev->mlock);
369 /*
370 * If monitor mode is enabled, the method for reading a single
371 * channel will have to be rather different and has not yet
372 * been implemented.
373 *
374 * Also, cannot read directly if buffered capture enabled.
375 */
376 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
377 ret = -EBUSY;
378 goto error_ret;
379 }
380
381 /* Check to see if current scan mode is correct */
382 if (st->current_mode != &max1363_mode_table[chan->address]) {
383 /* Update scan mode if needed */
384 st->current_mode = &max1363_mode_table[chan->address];
385 ret = max1363_set_scan_mode(st);
386 if (ret < 0)
387 goto error_ret;
388 }
389 if (st->chip_info->bits != 8) {
390 /* Get reading */
391 data = st->recv(client, rxbuf, 2);
392 if (data < 0) {
393 ret = data;
394 goto error_ret;
395 }
396 data = (rxbuf[1] | rxbuf[0] << 8) &
397 ((1 << st->chip_info->bits) - 1);
398 } else {
399 /* Get reading */
400 data = st->recv(client, rxbuf, 1);
401 if (data < 0) {
402 ret = data;
403 goto error_ret;
404 }
405 data = rxbuf[0];
406 }
407 *val = data;
408 error_ret:
409 mutex_unlock(&indio_dev->mlock);
410 return ret;
411
412 }
413
414 static int max1363_read_raw(struct iio_dev *indio_dev,
415 struct iio_chan_spec const *chan,
416 int *val,
417 int *val2,
418 long m)
419 {
420 struct max1363_state *st = iio_priv(indio_dev);
421 int ret;
422
423 switch (m) {
424 case IIO_CHAN_INFO_RAW:
425 ret = max1363_read_single_chan(indio_dev, chan, val, m);
426 if (ret < 0)
427 return ret;
428 return IIO_VAL_INT;
429 case IIO_CHAN_INFO_SCALE:
430 *val = st->vref_uv / 1000;
431 *val2 = st->chip_info->bits;
432 return IIO_VAL_FRACTIONAL_LOG2;
433 default:
434 return -EINVAL;
435 }
436 return 0;
437 }
438
439 /* Applies to max1363 */
440 static const enum max1363_modes max1363_mode_list[] = {
441 _s0, _s1, _s2, _s3,
442 s0to1, s0to2, s0to3,
443 d0m1, d2m3, d1m0, d3m2,
444 d0m1to2m3, d1m0to3m2,
445 };
446
447 static const struct iio_event_spec max1363_events[] = {
448 {
449 .type = IIO_EV_TYPE_THRESH,
450 .dir = IIO_EV_DIR_RISING,
451 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
452 BIT(IIO_EV_INFO_ENABLE),
453 }, {
454 .type = IIO_EV_TYPE_THRESH,
455 .dir = IIO_EV_DIR_FALLING,
456 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
457 BIT(IIO_EV_INFO_ENABLE),
458 },
459 };
460
461 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
462 { \
463 .type = IIO_VOLTAGE, \
464 .indexed = 1, \
465 .channel = num, \
466 .address = addr, \
467 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
468 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
469 .datasheet_name = "AIN"#num, \
470 .scan_type = { \
471 .sign = 'u', \
472 .realbits = bits, \
473 .storagebits = (bits > 8) ? 16 : 8, \
474 .endianness = IIO_BE, \
475 }, \
476 .scan_index = si, \
477 .event_spec = ev_spec, \
478 .num_event_specs = num_ev_spec, \
479 }
480
481 /* bipolar channel */
482 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
483 { \
484 .type = IIO_VOLTAGE, \
485 .differential = 1, \
486 .indexed = 1, \
487 .channel = num, \
488 .channel2 = num2, \
489 .address = addr, \
490 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
491 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
492 .datasheet_name = "AIN"#num"-AIN"#num2, \
493 .scan_type = { \
494 .sign = 's', \
495 .realbits = bits, \
496 .storagebits = (bits > 8) ? 16 : 8, \
497 .endianness = IIO_BE, \
498 }, \
499 .scan_index = si, \
500 .event_spec = ev_spec, \
501 .num_event_specs = num_ev_spec, \
502 }
503
504 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
505 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
512 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
513 IIO_CHAN_SOFT_TIMESTAMP(8) \
514 }
515
516 static const struct iio_chan_spec max1036_channels[] =
517 MAX1363_4X_CHANS(8, NULL, 0);
518 static const struct iio_chan_spec max1136_channels[] =
519 MAX1363_4X_CHANS(10, NULL, 0);
520 static const struct iio_chan_spec max1236_channels[] =
521 MAX1363_4X_CHANS(12, NULL, 0);
522 static const struct iio_chan_spec max1361_channels[] =
523 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
524 static const struct iio_chan_spec max1363_channels[] =
525 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
526
527 /* Applies to max1236, max1237 */
528 static const enum max1363_modes max1236_mode_list[] = {
529 _s0, _s1, _s2, _s3,
530 s0to1, s0to2, s0to3,
531 d0m1, d2m3, d1m0, d3m2,
532 d0m1to2m3, d1m0to3m2,
533 s2to3,
534 };
535
536 /* Applies to max1238, max1239 */
537 static const enum max1363_modes max1238_mode_list[] = {
538 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
539 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
540 s0to7, s0to8, s0to9, s0to10, s0to11,
541 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
542 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
543 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
544 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
545 s6to7, s6to8, s6to9, s6to10, s6to11,
546 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
547 };
548
549 #define MAX1363_12X_CHANS(bits) { \
550 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
551 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
552 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
553 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
554 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
555 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
556 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
557 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
558 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
559 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
560 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
561 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
562 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
563 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
564 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
565 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
566 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
567 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
568 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
569 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
570 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
571 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
572 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
573 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
574 IIO_CHAN_SOFT_TIMESTAMP(24) \
575 }
576 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
577 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
578 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
579
580 static const enum max1363_modes max11607_mode_list[] = {
581 _s0, _s1, _s2, _s3,
582 s0to1, s0to2, s0to3,
583 s2to3,
584 d0m1, d2m3, d1m0, d3m2,
585 d0m1to2m3, d1m0to3m2,
586 };
587
588 static const enum max1363_modes max11608_mode_list[] = {
589 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
590 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
591 s6to7,
592 d0m1, d2m3, d4m5, d6m7,
593 d1m0, d3m2, d5m4, d7m6,
594 d0m1to2m3, d0m1to4m5, d0m1to6m7,
595 d1m0to3m2, d1m0to5m4, d1m0to7m6,
596 };
597
598 #define MAX1363_8X_CHANS(bits) { \
599 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
600 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
601 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
602 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
603 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
604 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
605 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
606 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
607 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
608 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
609 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
610 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
611 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
612 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
613 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
614 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
615 IIO_CHAN_SOFT_TIMESTAMP(16) \
616 }
617 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
618 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
619 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
620
621 static const enum max1363_modes max11644_mode_list[] = {
622 _s0, _s1, s0to1, d0m1, d1m0,
623 };
624
625 #define MAX1363_2X_CHANS(bits) { \
626 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
627 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
628 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
629 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
630 IIO_CHAN_SOFT_TIMESTAMP(4) \
631 }
632
633 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
634 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
635
636 enum { max1361,
637 max1362,
638 max1363,
639 max1364,
640 max1036,
641 max1037,
642 max1038,
643 max1039,
644 max1136,
645 max1137,
646 max1138,
647 max1139,
648 max1236,
649 max1237,
650 max1238,
651 max1239,
652 max11600,
653 max11601,
654 max11602,
655 max11603,
656 max11604,
657 max11605,
658 max11606,
659 max11607,
660 max11608,
661 max11609,
662 max11610,
663 max11611,
664 max11612,
665 max11613,
666 max11614,
667 max11615,
668 max11616,
669 max11617,
670 max11644,
671 max11645,
672 max11646,
673 max11647
674 };
675
676 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
677 8300, 4200, 2000, 1000 };
678
679 static ssize_t max1363_monitor_show_freq(struct device *dev,
680 struct device_attribute *attr,
681 char *buf)
682 {
683 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
684 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
685 }
686
687 static ssize_t max1363_monitor_store_freq(struct device *dev,
688 struct device_attribute *attr,
689 const char *buf,
690 size_t len)
691 {
692 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
693 struct max1363_state *st = iio_priv(indio_dev);
694 int i, ret;
695 unsigned long val;
696 bool found = false;
697
698 ret = kstrtoul(buf, 10, &val);
699 if (ret)
700 return -EINVAL;
701 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
702 if (val == max1363_monitor_speeds[i]) {
703 found = true;
704 break;
705 }
706 if (!found)
707 return -EINVAL;
708
709 mutex_lock(&indio_dev->mlock);
710 st->monitor_speed = i;
711 mutex_unlock(&indio_dev->mlock);
712
713 return 0;
714 }
715
716 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
717 max1363_monitor_show_freq,
718 max1363_monitor_store_freq);
719
720 static IIO_CONST_ATTR(sampling_frequency_available,
721 "133000 665000 33300 16600 8300 4200 2000 1000");
722
723 static int max1363_read_thresh(struct iio_dev *indio_dev,
724 const struct iio_chan_spec *chan, enum iio_event_type type,
725 enum iio_event_direction dir, enum iio_event_info info, int *val,
726 int *val2)
727 {
728 struct max1363_state *st = iio_priv(indio_dev);
729 if (dir == IIO_EV_DIR_FALLING)
730 *val = st->thresh_low[chan->channel];
731 else
732 *val = st->thresh_high[chan->channel];
733 return IIO_VAL_INT;
734 }
735
736 static int max1363_write_thresh(struct iio_dev *indio_dev,
737 const struct iio_chan_spec *chan, enum iio_event_type type,
738 enum iio_event_direction dir, enum iio_event_info info, int val,
739 int val2)
740 {
741 struct max1363_state *st = iio_priv(indio_dev);
742 /* make it handle signed correctly as well */
743 switch (st->chip_info->bits) {
744 case 10:
745 if (val > 0x3FF)
746 return -EINVAL;
747 break;
748 case 12:
749 if (val > 0xFFF)
750 return -EINVAL;
751 break;
752 }
753
754 switch (dir) {
755 case IIO_EV_DIR_FALLING:
756 st->thresh_low[chan->channel] = val;
757 break;
758 case IIO_EV_DIR_RISING:
759 st->thresh_high[chan->channel] = val;
760 break;
761 default:
762 return -EINVAL;
763 }
764
765 return 0;
766 }
767
768 static const u64 max1363_event_codes[] = {
769 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
770 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
771 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
772 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
785 };
786
787 static irqreturn_t max1363_event_handler(int irq, void *private)
788 {
789 struct iio_dev *indio_dev = private;
790 struct max1363_state *st = iio_priv(indio_dev);
791 s64 timestamp = iio_get_time_ns();
792 unsigned long mask, loc;
793 u8 rx;
794 u8 tx[2] = { st->setupbyte,
795 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
796
797 st->recv(st->client, &rx, 1);
798 mask = rx;
799 for_each_set_bit(loc, &mask, 8)
800 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
801 st->send(st->client, tx, 2);
802
803 return IRQ_HANDLED;
804 }
805
806 static int max1363_read_event_config(struct iio_dev *indio_dev,
807 const struct iio_chan_spec *chan, enum iio_event_type type,
808 enum iio_event_direction dir)
809 {
810 struct max1363_state *st = iio_priv(indio_dev);
811 int val;
812 int number = chan->channel;
813
814 mutex_lock(&indio_dev->mlock);
815 if (dir == IIO_EV_DIR_FALLING)
816 val = (1 << number) & st->mask_low;
817 else
818 val = (1 << number) & st->mask_high;
819 mutex_unlock(&indio_dev->mlock);
820
821 return val;
822 }
823
824 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
825 {
826 u8 *tx_buf;
827 int ret, i = 3, j;
828 unsigned long numelements;
829 int len;
830 const long *modemask;
831
832 if (!enabled) {
833 /* transition to buffered capture is not currently supported */
834 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
835 st->configbyte &= ~MAX1363_SCAN_MASK;
836 st->monitor_on = false;
837 return max1363_write_basic_config(st);
838 }
839
840 /* Ensure we are in the relevant mode */
841 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
842 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
843 | MAX1363_SCAN_MASK
844 | MAX1363_SE_DE_MASK);
845 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
846 if ((st->mask_low | st->mask_high) & 0x0F) {
847 st->configbyte |= max1363_mode_table[s0to3].conf;
848 modemask = max1363_mode_table[s0to3].modemask;
849 } else if ((st->mask_low | st->mask_high) & 0x30) {
850 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
851 modemask = max1363_mode_table[d0m1to2m3].modemask;
852 } else {
853 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
854 modemask = max1363_mode_table[d1m0to3m2].modemask;
855 }
856 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
857 len = 3 * numelements + 3;
858 tx_buf = kmalloc(len, GFP_KERNEL);
859 if (!tx_buf) {
860 ret = -ENOMEM;
861 goto error_ret;
862 }
863 tx_buf[0] = st->configbyte;
864 tx_buf[1] = st->setupbyte;
865 tx_buf[2] = (st->monitor_speed << 1);
866
867 /*
868 * So we need to do yet another bit of nefarious scan mode
869 * setup to match what we need.
870 */
871 for (j = 0; j < 8; j++)
872 if (test_bit(j, modemask)) {
873 /* Establish the mode is in the scan */
874 if (st->mask_low & (1 << j)) {
875 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
876 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
877 } else if (j < 4) {
878 tx_buf[i] = 0;
879 tx_buf[i + 1] = 0;
880 } else {
881 tx_buf[i] = 0x80;
882 tx_buf[i + 1] = 0;
883 }
884 if (st->mask_high & (1 << j)) {
885 tx_buf[i + 1] |=
886 (st->thresh_high[j] >> 8) & 0x0F;
887 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
888 } else if (j < 4) {
889 tx_buf[i + 1] |= 0x0F;
890 tx_buf[i + 2] = 0xFF;
891 } else {
892 tx_buf[i + 1] |= 0x07;
893 tx_buf[i + 2] = 0xFF;
894 }
895 i += 3;
896 }
897
898
899 ret = st->send(st->client, tx_buf, len);
900 if (ret < 0)
901 goto error_ret;
902 if (ret != len) {
903 ret = -EIO;
904 goto error_ret;
905 }
906
907 /*
908 * Now that we hopefully have sensible thresholds in place it is
909 * time to turn the interrupts on.
910 * It is unclear from the data sheet if this should be necessary
911 * (i.e. whether monitor mode setup is atomic) but it appears to
912 * be in practice.
913 */
914 tx_buf[0] = st->setupbyte;
915 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
916 ret = st->send(st->client, tx_buf, 2);
917 if (ret < 0)
918 goto error_ret;
919 if (ret != 2) {
920 ret = -EIO;
921 goto error_ret;
922 }
923 ret = 0;
924 st->monitor_on = true;
925 error_ret:
926
927 kfree(tx_buf);
928
929 return ret;
930 }
931
932 /*
933 * To keep this manageable we always use one of 3 scan modes.
934 * Scan 0...3, 0-1,2-3 and 1-0,3-2
935 */
936
937 static inline int __max1363_check_event_mask(int thismask, int checkmask)
938 {
939 int ret = 0;
940 /* Is it unipolar */
941 if (thismask < 4) {
942 if (checkmask & ~0x0F) {
943 ret = -EBUSY;
944 goto error_ret;
945 }
946 } else if (thismask < 6) {
947 if (checkmask & ~0x30) {
948 ret = -EBUSY;
949 goto error_ret;
950 }
951 } else if (checkmask & ~0xC0)
952 ret = -EBUSY;
953 error_ret:
954 return ret;
955 }
956
957 static int max1363_write_event_config(struct iio_dev *indio_dev,
958 const struct iio_chan_spec *chan, enum iio_event_type type,
959 enum iio_event_direction dir, int state)
960 {
961 int ret = 0;
962 struct max1363_state *st = iio_priv(indio_dev);
963 u16 unifiedmask;
964 int number = chan->channel;
965
966 mutex_lock(&indio_dev->mlock);
967 unifiedmask = st->mask_low | st->mask_high;
968 if (dir == IIO_EV_DIR_FALLING) {
969
970 if (state == 0)
971 st->mask_low &= ~(1 << number);
972 else {
973 ret = __max1363_check_event_mask((1 << number),
974 unifiedmask);
975 if (ret)
976 goto error_ret;
977 st->mask_low |= (1 << number);
978 }
979 } else {
980 if (state == 0)
981 st->mask_high &= ~(1 << number);
982 else {
983 ret = __max1363_check_event_mask((1 << number),
984 unifiedmask);
985 if (ret)
986 goto error_ret;
987 st->mask_high |= (1 << number);
988 }
989 }
990
991 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
992 error_ret:
993 mutex_unlock(&indio_dev->mlock);
994
995 return ret;
996 }
997
998 /*
999 * As with scan_elements, only certain sets of these can
1000 * be combined.
1001 */
1002 static struct attribute *max1363_event_attributes[] = {
1003 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1004 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1005 NULL,
1006 };
1007
1008 static struct attribute_group max1363_event_attribute_group = {
1009 .attrs = max1363_event_attributes,
1010 .name = "events",
1011 };
1012
1013 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1014 const unsigned long *scan_mask)
1015 {
1016 struct max1363_state *st = iio_priv(indio_dev);
1017
1018 /*
1019 * Need to figure out the current mode based upon the requested
1020 * scan mask in iio_dev
1021 */
1022 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1023 if (!st->current_mode)
1024 return -EINVAL;
1025 max1363_set_scan_mode(st);
1026 return 0;
1027 }
1028
1029 static const struct iio_info max1238_info = {
1030 .read_raw = &max1363_read_raw,
1031 .driver_module = THIS_MODULE,
1032 .update_scan_mode = &max1363_update_scan_mode,
1033 };
1034
1035 static const struct iio_info max1363_info = {
1036 .read_event_value = &max1363_read_thresh,
1037 .write_event_value = &max1363_write_thresh,
1038 .read_event_config = &max1363_read_event_config,
1039 .write_event_config = &max1363_write_event_config,
1040 .read_raw = &max1363_read_raw,
1041 .update_scan_mode = &max1363_update_scan_mode,
1042 .driver_module = THIS_MODULE,
1043 .event_attrs = &max1363_event_attribute_group,
1044 };
1045
1046 /* max1363 and max1368 tested - rest from data sheet */
1047 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1048 [max1361] = {
1049 .bits = 10,
1050 .int_vref_mv = 2048,
1051 .mode_list = max1363_mode_list,
1052 .num_modes = ARRAY_SIZE(max1363_mode_list),
1053 .default_mode = s0to3,
1054 .channels = max1361_channels,
1055 .num_channels = ARRAY_SIZE(max1361_channels),
1056 .info = &max1363_info,
1057 },
1058 [max1362] = {
1059 .bits = 10,
1060 .int_vref_mv = 4096,
1061 .mode_list = max1363_mode_list,
1062 .num_modes = ARRAY_SIZE(max1363_mode_list),
1063 .default_mode = s0to3,
1064 .channels = max1361_channels,
1065 .num_channels = ARRAY_SIZE(max1361_channels),
1066 .info = &max1363_info,
1067 },
1068 [max1363] = {
1069 .bits = 12,
1070 .int_vref_mv = 2048,
1071 .mode_list = max1363_mode_list,
1072 .num_modes = ARRAY_SIZE(max1363_mode_list),
1073 .default_mode = s0to3,
1074 .channels = max1363_channels,
1075 .num_channels = ARRAY_SIZE(max1363_channels),
1076 .info = &max1363_info,
1077 },
1078 [max1364] = {
1079 .bits = 12,
1080 .int_vref_mv = 4096,
1081 .mode_list = max1363_mode_list,
1082 .num_modes = ARRAY_SIZE(max1363_mode_list),
1083 .default_mode = s0to3,
1084 .channels = max1363_channels,
1085 .num_channels = ARRAY_SIZE(max1363_channels),
1086 .info = &max1363_info,
1087 },
1088 [max1036] = {
1089 .bits = 8,
1090 .int_vref_mv = 4096,
1091 .mode_list = max1236_mode_list,
1092 .num_modes = ARRAY_SIZE(max1236_mode_list),
1093 .default_mode = s0to3,
1094 .info = &max1238_info,
1095 .channels = max1036_channels,
1096 .num_channels = ARRAY_SIZE(max1036_channels),
1097 },
1098 [max1037] = {
1099 .bits = 8,
1100 .int_vref_mv = 2048,
1101 .mode_list = max1236_mode_list,
1102 .num_modes = ARRAY_SIZE(max1236_mode_list),
1103 .default_mode = s0to3,
1104 .info = &max1238_info,
1105 .channels = max1036_channels,
1106 .num_channels = ARRAY_SIZE(max1036_channels),
1107 },
1108 [max1038] = {
1109 .bits = 8,
1110 .int_vref_mv = 4096,
1111 .mode_list = max1238_mode_list,
1112 .num_modes = ARRAY_SIZE(max1238_mode_list),
1113 .default_mode = s0to11,
1114 .info = &max1238_info,
1115 .channels = max1038_channels,
1116 .num_channels = ARRAY_SIZE(max1038_channels),
1117 },
1118 [max1039] = {
1119 .bits = 8,
1120 .int_vref_mv = 2048,
1121 .mode_list = max1238_mode_list,
1122 .num_modes = ARRAY_SIZE(max1238_mode_list),
1123 .default_mode = s0to11,
1124 .info = &max1238_info,
1125 .channels = max1038_channels,
1126 .num_channels = ARRAY_SIZE(max1038_channels),
1127 },
1128 [max1136] = {
1129 .bits = 10,
1130 .int_vref_mv = 4096,
1131 .mode_list = max1236_mode_list,
1132 .num_modes = ARRAY_SIZE(max1236_mode_list),
1133 .default_mode = s0to3,
1134 .info = &max1238_info,
1135 .channels = max1136_channels,
1136 .num_channels = ARRAY_SIZE(max1136_channels),
1137 },
1138 [max1137] = {
1139 .bits = 10,
1140 .int_vref_mv = 2048,
1141 .mode_list = max1236_mode_list,
1142 .num_modes = ARRAY_SIZE(max1236_mode_list),
1143 .default_mode = s0to3,
1144 .info = &max1238_info,
1145 .channels = max1136_channels,
1146 .num_channels = ARRAY_SIZE(max1136_channels),
1147 },
1148 [max1138] = {
1149 .bits = 10,
1150 .int_vref_mv = 4096,
1151 .mode_list = max1238_mode_list,
1152 .num_modes = ARRAY_SIZE(max1238_mode_list),
1153 .default_mode = s0to11,
1154 .info = &max1238_info,
1155 .channels = max1138_channels,
1156 .num_channels = ARRAY_SIZE(max1138_channels),
1157 },
1158 [max1139] = {
1159 .bits = 10,
1160 .int_vref_mv = 2048,
1161 .mode_list = max1238_mode_list,
1162 .num_modes = ARRAY_SIZE(max1238_mode_list),
1163 .default_mode = s0to11,
1164 .info = &max1238_info,
1165 .channels = max1138_channels,
1166 .num_channels = ARRAY_SIZE(max1138_channels),
1167 },
1168 [max1236] = {
1169 .bits = 12,
1170 .int_vref_mv = 4096,
1171 .mode_list = max1236_mode_list,
1172 .num_modes = ARRAY_SIZE(max1236_mode_list),
1173 .default_mode = s0to3,
1174 .info = &max1238_info,
1175 .channels = max1236_channels,
1176 .num_channels = ARRAY_SIZE(max1236_channels),
1177 },
1178 [max1237] = {
1179 .bits = 12,
1180 .int_vref_mv = 2048,
1181 .mode_list = max1236_mode_list,
1182 .num_modes = ARRAY_SIZE(max1236_mode_list),
1183 .default_mode = s0to3,
1184 .info = &max1238_info,
1185 .channels = max1236_channels,
1186 .num_channels = ARRAY_SIZE(max1236_channels),
1187 },
1188 [max1238] = {
1189 .bits = 12,
1190 .int_vref_mv = 4096,
1191 .mode_list = max1238_mode_list,
1192 .num_modes = ARRAY_SIZE(max1238_mode_list),
1193 .default_mode = s0to11,
1194 .info = &max1238_info,
1195 .channels = max1238_channels,
1196 .num_channels = ARRAY_SIZE(max1238_channels),
1197 },
1198 [max1239] = {
1199 .bits = 12,
1200 .int_vref_mv = 2048,
1201 .mode_list = max1238_mode_list,
1202 .num_modes = ARRAY_SIZE(max1238_mode_list),
1203 .default_mode = s0to11,
1204 .info = &max1238_info,
1205 .channels = max1238_channels,
1206 .num_channels = ARRAY_SIZE(max1238_channels),
1207 },
1208 [max11600] = {
1209 .bits = 8,
1210 .int_vref_mv = 4096,
1211 .mode_list = max11607_mode_list,
1212 .num_modes = ARRAY_SIZE(max11607_mode_list),
1213 .default_mode = s0to3,
1214 .info = &max1238_info,
1215 .channels = max1036_channels,
1216 .num_channels = ARRAY_SIZE(max1036_channels),
1217 },
1218 [max11601] = {
1219 .bits = 8,
1220 .int_vref_mv = 2048,
1221 .mode_list = max11607_mode_list,
1222 .num_modes = ARRAY_SIZE(max11607_mode_list),
1223 .default_mode = s0to3,
1224 .info = &max1238_info,
1225 .channels = max1036_channels,
1226 .num_channels = ARRAY_SIZE(max1036_channels),
1227 },
1228 [max11602] = {
1229 .bits = 8,
1230 .int_vref_mv = 4096,
1231 .mode_list = max11608_mode_list,
1232 .num_modes = ARRAY_SIZE(max11608_mode_list),
1233 .default_mode = s0to7,
1234 .info = &max1238_info,
1235 .channels = max11602_channels,
1236 .num_channels = ARRAY_SIZE(max11602_channels),
1237 },
1238 [max11603] = {
1239 .bits = 8,
1240 .int_vref_mv = 2048,
1241 .mode_list = max11608_mode_list,
1242 .num_modes = ARRAY_SIZE(max11608_mode_list),
1243 .default_mode = s0to7,
1244 .info = &max1238_info,
1245 .channels = max11602_channels,
1246 .num_channels = ARRAY_SIZE(max11602_channels),
1247 },
1248 [max11604] = {
1249 .bits = 8,
1250 .int_vref_mv = 4096,
1251 .mode_list = max1238_mode_list,
1252 .num_modes = ARRAY_SIZE(max1238_mode_list),
1253 .default_mode = s0to11,
1254 .info = &max1238_info,
1255 .channels = max1038_channels,
1256 .num_channels = ARRAY_SIZE(max1038_channels),
1257 },
1258 [max11605] = {
1259 .bits = 8,
1260 .int_vref_mv = 2048,
1261 .mode_list = max1238_mode_list,
1262 .num_modes = ARRAY_SIZE(max1238_mode_list),
1263 .default_mode = s0to11,
1264 .info = &max1238_info,
1265 .channels = max1038_channels,
1266 .num_channels = ARRAY_SIZE(max1038_channels),
1267 },
1268 [max11606] = {
1269 .bits = 10,
1270 .int_vref_mv = 4096,
1271 .mode_list = max11607_mode_list,
1272 .num_modes = ARRAY_SIZE(max11607_mode_list),
1273 .default_mode = s0to3,
1274 .info = &max1238_info,
1275 .channels = max1136_channels,
1276 .num_channels = ARRAY_SIZE(max1136_channels),
1277 },
1278 [max11607] = {
1279 .bits = 10,
1280 .int_vref_mv = 2048,
1281 .mode_list = max11607_mode_list,
1282 .num_modes = ARRAY_SIZE(max11607_mode_list),
1283 .default_mode = s0to3,
1284 .info = &max1238_info,
1285 .channels = max1136_channels,
1286 .num_channels = ARRAY_SIZE(max1136_channels),
1287 },
1288 [max11608] = {
1289 .bits = 10,
1290 .int_vref_mv = 4096,
1291 .mode_list = max11608_mode_list,
1292 .num_modes = ARRAY_SIZE(max11608_mode_list),
1293 .default_mode = s0to7,
1294 .info = &max1238_info,
1295 .channels = max11608_channels,
1296 .num_channels = ARRAY_SIZE(max11608_channels),
1297 },
1298 [max11609] = {
1299 .bits = 10,
1300 .int_vref_mv = 2048,
1301 .mode_list = max11608_mode_list,
1302 .num_modes = ARRAY_SIZE(max11608_mode_list),
1303 .default_mode = s0to7,
1304 .info = &max1238_info,
1305 .channels = max11608_channels,
1306 .num_channels = ARRAY_SIZE(max11608_channels),
1307 },
1308 [max11610] = {
1309 .bits = 10,
1310 .int_vref_mv = 4096,
1311 .mode_list = max1238_mode_list,
1312 .num_modes = ARRAY_SIZE(max1238_mode_list),
1313 .default_mode = s0to11,
1314 .info = &max1238_info,
1315 .channels = max1138_channels,
1316 .num_channels = ARRAY_SIZE(max1138_channels),
1317 },
1318 [max11611] = {
1319 .bits = 10,
1320 .int_vref_mv = 2048,
1321 .mode_list = max1238_mode_list,
1322 .num_modes = ARRAY_SIZE(max1238_mode_list),
1323 .default_mode = s0to11,
1324 .info = &max1238_info,
1325 .channels = max1138_channels,
1326 .num_channels = ARRAY_SIZE(max1138_channels),
1327 },
1328 [max11612] = {
1329 .bits = 12,
1330 .int_vref_mv = 4096,
1331 .mode_list = max11607_mode_list,
1332 .num_modes = ARRAY_SIZE(max11607_mode_list),
1333 .default_mode = s0to3,
1334 .info = &max1238_info,
1335 .channels = max1363_channels,
1336 .num_channels = ARRAY_SIZE(max1363_channels),
1337 },
1338 [max11613] = {
1339 .bits = 12,
1340 .int_vref_mv = 2048,
1341 .mode_list = max11607_mode_list,
1342 .num_modes = ARRAY_SIZE(max11607_mode_list),
1343 .default_mode = s0to3,
1344 .info = &max1238_info,
1345 .channels = max1363_channels,
1346 .num_channels = ARRAY_SIZE(max1363_channels),
1347 },
1348 [max11614] = {
1349 .bits = 12,
1350 .int_vref_mv = 4096,
1351 .mode_list = max11608_mode_list,
1352 .num_modes = ARRAY_SIZE(max11608_mode_list),
1353 .default_mode = s0to7,
1354 .info = &max1238_info,
1355 .channels = max11614_channels,
1356 .num_channels = ARRAY_SIZE(max11614_channels),
1357 },
1358 [max11615] = {
1359 .bits = 12,
1360 .int_vref_mv = 2048,
1361 .mode_list = max11608_mode_list,
1362 .num_modes = ARRAY_SIZE(max11608_mode_list),
1363 .default_mode = s0to7,
1364 .info = &max1238_info,
1365 .channels = max11614_channels,
1366 .num_channels = ARRAY_SIZE(max11614_channels),
1367 },
1368 [max11616] = {
1369 .bits = 12,
1370 .int_vref_mv = 4096,
1371 .mode_list = max1238_mode_list,
1372 .num_modes = ARRAY_SIZE(max1238_mode_list),
1373 .default_mode = s0to11,
1374 .info = &max1238_info,
1375 .channels = max1238_channels,
1376 .num_channels = ARRAY_SIZE(max1238_channels),
1377 },
1378 [max11617] = {
1379 .bits = 12,
1380 .int_vref_mv = 2048,
1381 .mode_list = max1238_mode_list,
1382 .num_modes = ARRAY_SIZE(max1238_mode_list),
1383 .default_mode = s0to11,
1384 .info = &max1238_info,
1385 .channels = max1238_channels,
1386 .num_channels = ARRAY_SIZE(max1238_channels),
1387 },
1388 [max11644] = {
1389 .bits = 12,
1390 .int_vref_mv = 2048,
1391 .mode_list = max11644_mode_list,
1392 .num_modes = ARRAY_SIZE(max11644_mode_list),
1393 .default_mode = s0to1,
1394 .info = &max1238_info,
1395 .channels = max11644_channels,
1396 .num_channels = ARRAY_SIZE(max11644_channels),
1397 },
1398 [max11645] = {
1399 .bits = 12,
1400 .int_vref_mv = 4096,
1401 .mode_list = max11644_mode_list,
1402 .num_modes = ARRAY_SIZE(max11644_mode_list),
1403 .default_mode = s0to1,
1404 .info = &max1238_info,
1405 .channels = max11644_channels,
1406 .num_channels = ARRAY_SIZE(max11644_channels),
1407 },
1408 [max11646] = {
1409 .bits = 10,
1410 .int_vref_mv = 2048,
1411 .mode_list = max11644_mode_list,
1412 .num_modes = ARRAY_SIZE(max11644_mode_list),
1413 .default_mode = s0to1,
1414 .info = &max1238_info,
1415 .channels = max11646_channels,
1416 .num_channels = ARRAY_SIZE(max11646_channels),
1417 },
1418 [max11647] = {
1419 .bits = 10,
1420 .int_vref_mv = 4096,
1421 .mode_list = max11644_mode_list,
1422 .num_modes = ARRAY_SIZE(max11644_mode_list),
1423 .default_mode = s0to1,
1424 .info = &max1238_info,
1425 .channels = max11646_channels,
1426 .num_channels = ARRAY_SIZE(max11646_channels),
1427 },
1428 };
1429
1430 static int max1363_initial_setup(struct max1363_state *st)
1431 {
1432 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1433 | MAX1363_SETUP_UNIPOLAR
1434 | MAX1363_SETUP_NORESET;
1435
1436 if (st->vref)
1437 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1438 else
1439 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1440 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1441
1442 /* Set scan mode writes the config anyway so wait until then */
1443 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1444 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1445 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1446
1447 return max1363_set_scan_mode(st);
1448 }
1449
1450 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1451 {
1452 struct max1363_state *st = iio_priv(indio_dev);
1453 unsigned long *masks;
1454 int i;
1455
1456 masks = devm_kzalloc(&indio_dev->dev,
1457 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) *
1458 (st->chip_info->num_modes + 1), GFP_KERNEL);
1459 if (!masks)
1460 return -ENOMEM;
1461
1462 for (i = 0; i < st->chip_info->num_modes; i++)
1463 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1464 max1363_mode_table[st->chip_info->mode_list[i]]
1465 .modemask, MAX1363_MAX_CHANNELS);
1466
1467 indio_dev->available_scan_masks = masks;
1468
1469 return 0;
1470 }
1471
1472 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1473 {
1474 struct iio_poll_func *pf = p;
1475 struct iio_dev *indio_dev = pf->indio_dev;
1476 struct max1363_state *st = iio_priv(indio_dev);
1477 __u8 *rxbuf;
1478 int b_sent;
1479 size_t d_size;
1480 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1481 MAX1363_MAX_CHANNELS);
1482
1483 /* Ensure the timestamp is 8 byte aligned */
1484 if (st->chip_info->bits != 8)
1485 d_size = numvals*2;
1486 else
1487 d_size = numvals;
1488 if (indio_dev->scan_timestamp) {
1489 d_size += sizeof(s64);
1490 if (d_size % sizeof(s64))
1491 d_size += sizeof(s64) - (d_size % sizeof(s64));
1492 }
1493 /* Monitor mode prevents reading. Whilst not currently implemented
1494 * might as well have this test in here in the meantime as it does
1495 * no harm.
1496 */
1497 if (numvals == 0)
1498 goto done;
1499
1500 rxbuf = kmalloc(d_size, GFP_KERNEL);
1501 if (rxbuf == NULL)
1502 goto done;
1503 if (st->chip_info->bits != 8)
1504 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1505 else
1506 b_sent = st->recv(st->client, rxbuf, numvals);
1507 if (b_sent < 0)
1508 goto done_free;
1509
1510 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf, iio_get_time_ns());
1511
1512 done_free:
1513 kfree(rxbuf);
1514 done:
1515 iio_trigger_notify_done(indio_dev->trig);
1516
1517 return IRQ_HANDLED;
1518 }
1519
1520 static int max1363_probe(struct i2c_client *client,
1521 const struct i2c_device_id *id)
1522 {
1523 int ret;
1524 struct max1363_state *st;
1525 struct iio_dev *indio_dev;
1526 struct regulator *vref;
1527
1528 indio_dev = devm_iio_device_alloc(&client->dev,
1529 sizeof(struct max1363_state));
1530 if (!indio_dev)
1531 return -ENOMEM;
1532
1533 indio_dev->dev.of_node = client->dev.of_node;
1534 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1535 if (ret < 0)
1536 return ret;
1537
1538 st = iio_priv(indio_dev);
1539
1540 st->reg = devm_regulator_get(&client->dev, "vcc");
1541 if (IS_ERR(st->reg)) {
1542 ret = PTR_ERR(st->reg);
1543 goto error_unregister_map;
1544 }
1545
1546 ret = regulator_enable(st->reg);
1547 if (ret)
1548 goto error_unregister_map;
1549
1550 /* this is only used for device removal purposes */
1551 i2c_set_clientdata(client, indio_dev);
1552
1553 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1554 st->client = client;
1555
1556 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1557 vref = devm_regulator_get_optional(&client->dev, "vref");
1558 if (!IS_ERR(vref)) {
1559 int vref_uv;
1560
1561 ret = regulator_enable(vref);
1562 if (ret)
1563 goto error_disable_reg;
1564 st->vref = vref;
1565 vref_uv = regulator_get_voltage(vref);
1566 if (vref_uv <= 0) {
1567 ret = -EINVAL;
1568 goto error_disable_reg;
1569 }
1570 st->vref_uv = vref_uv;
1571 }
1572
1573 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1574 st->send = i2c_master_send;
1575 st->recv = i2c_master_recv;
1576 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1577 && st->chip_info->bits == 8) {
1578 st->send = max1363_smbus_send;
1579 st->recv = max1363_smbus_recv;
1580 } else {
1581 ret = -EOPNOTSUPP;
1582 goto error_disable_reg;
1583 }
1584
1585 ret = max1363_alloc_scan_masks(indio_dev);
1586 if (ret)
1587 goto error_disable_reg;
1588
1589 /* Establish that the iio_dev is a child of the i2c device */
1590 indio_dev->dev.parent = &client->dev;
1591 indio_dev->name = id->name;
1592 indio_dev->channels = st->chip_info->channels;
1593 indio_dev->num_channels = st->chip_info->num_channels;
1594 indio_dev->info = st->chip_info->info;
1595 indio_dev->modes = INDIO_DIRECT_MODE;
1596 ret = max1363_initial_setup(st);
1597 if (ret < 0)
1598 goto error_disable_reg;
1599
1600 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1601 &max1363_trigger_handler, NULL);
1602 if (ret)
1603 goto error_disable_reg;
1604
1605 if (client->irq) {
1606 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1607 NULL,
1608 &max1363_event_handler,
1609 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1610 "max1363_event",
1611 indio_dev);
1612
1613 if (ret)
1614 goto error_uninit_buffer;
1615 }
1616
1617 ret = iio_device_register(indio_dev);
1618 if (ret < 0)
1619 goto error_uninit_buffer;
1620
1621 return 0;
1622
1623 error_uninit_buffer:
1624 iio_triggered_buffer_cleanup(indio_dev);
1625 error_disable_reg:
1626 if (st->vref)
1627 regulator_disable(st->vref);
1628 regulator_disable(st->reg);
1629 error_unregister_map:
1630 iio_map_array_unregister(indio_dev);
1631 return ret;
1632 }
1633
1634 static int max1363_remove(struct i2c_client *client)
1635 {
1636 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1637 struct max1363_state *st = iio_priv(indio_dev);
1638
1639 iio_device_unregister(indio_dev);
1640 iio_triggered_buffer_cleanup(indio_dev);
1641 if (st->vref)
1642 regulator_disable(st->vref);
1643 regulator_disable(st->reg);
1644 iio_map_array_unregister(indio_dev);
1645
1646 return 0;
1647 }
1648
1649 static const struct i2c_device_id max1363_id[] = {
1650 { "max1361", max1361 },
1651 { "max1362", max1362 },
1652 { "max1363", max1363 },
1653 { "max1364", max1364 },
1654 { "max1036", max1036 },
1655 { "max1037", max1037 },
1656 { "max1038", max1038 },
1657 { "max1039", max1039 },
1658 { "max1136", max1136 },
1659 { "max1137", max1137 },
1660 { "max1138", max1138 },
1661 { "max1139", max1139 },
1662 { "max1236", max1236 },
1663 { "max1237", max1237 },
1664 { "max1238", max1238 },
1665 { "max1239", max1239 },
1666 { "max11600", max11600 },
1667 { "max11601", max11601 },
1668 { "max11602", max11602 },
1669 { "max11603", max11603 },
1670 { "max11604", max11604 },
1671 { "max11605", max11605 },
1672 { "max11606", max11606 },
1673 { "max11607", max11607 },
1674 { "max11608", max11608 },
1675 { "max11609", max11609 },
1676 { "max11610", max11610 },
1677 { "max11611", max11611 },
1678 { "max11612", max11612 },
1679 { "max11613", max11613 },
1680 { "max11614", max11614 },
1681 { "max11615", max11615 },
1682 { "max11616", max11616 },
1683 { "max11617", max11617 },
1684 {}
1685 };
1686
1687 MODULE_DEVICE_TABLE(i2c, max1363_id);
1688
1689 static struct i2c_driver max1363_driver = {
1690 .driver = {
1691 .name = "max1363",
1692 },
1693 .probe = max1363_probe,
1694 .remove = max1363_remove,
1695 .id_table = max1363_id,
1696 };
1697 module_i2c_driver(max1363_driver);
1698
1699 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1700 MODULE_DESCRIPTION("Maxim 1363 ADC");
1701 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support