| blob | 3312be6c82cc6aac4cd98f0a1ebb03b1404c2763 |
1 /*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
49 #include "skeleton.dtsi"
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
55 / {
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
59 aliases {
60 gpio0 = &gpio0;
61 gpio1 = &gpio1;
62 serial0 = &uart0;
63 serial1 = &uart1;
64 };
66 pmu {
67 compatible = "arm,cortex-a9-pmu";
68 interrupts-extended = <&mpic 3>;
69 };
71 soc {
72 compatible = "marvell,armada380-mbus", "simple-bus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 controller = <&mbusc>;
76 interrupt-parent = <&gic>;
77 pcie-mem-aperture = <0xe0000000 0x8000000>;
78 pcie-io-aperture = <0xe8000000 0x100000>;
80 bootrom {
81 compatible = "marvell,bootrom";
82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
83 };
85 devbus-bootcs {
86 compatible = "marvell,mvebu-devbus";
87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 clocks = <&coreclk 0>;
92 status = "disabled";
93 };
95 devbus-cs0 {
96 compatible = "marvell,mvebu-devbus";
97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 clocks = <&coreclk 0>;
102 status = "disabled";
103 };
105 devbus-cs1 {
106 compatible = "marvell,mvebu-devbus";
107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 clocks = <&coreclk 0>;
112 status = "disabled";
113 };
115 devbus-cs2 {
116 compatible = "marvell,mvebu-devbus";
117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 clocks = <&coreclk 0>;
122 status = "disabled";
123 };
125 devbus-cs3 {
126 compatible = "marvell,mvebu-devbus";
127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
135 internal-regs {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
141 L2: cache-controller@8000 {
142 compatible = "arm,pl310-cache";
143 reg = <0x8000 0x1000>;
144 cache-unified;
145 cache-level = <2>;
146 arm,double-linefill-incr = <1>;
147 arm,double-linefill-wrap = <0>;
148 arm,double-linefill = <1>;
149 prefetch-data = <1>;
150 };
152 scu@c000 {
153 compatible = "arm,cortex-a9-scu";
154 reg = <0xc000 0x58>;
155 };
157 timer@c600 {
158 compatible = "arm,cortex-a9-twd-timer";
159 reg = <0xc600 0x20>;
160 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
161 clocks = <&coreclk 2>;
162 };
164 gic: interrupt-controller@d000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 #size-cells = <0>;
168 interrupt-controller;
169 reg = <0xd000 0x1000>,
170 <0xc100 0x100>;
171 };
173 spi0: spi@10600 {
174 compatible = "marvell,armada-380-spi",
175 "marvell,orion-spi";
176 reg = <0x10600 0x50>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 cell-index = <0>;
180 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&coreclk 0>;
182 status = "disabled";
183 };
185 spi1: spi@10680 {
186 compatible = "marvell,armada-380-spi",
187 "marvell,orion-spi";
188 reg = <0x10680 0x50>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 cell-index = <1>;
192 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&coreclk 0>;
194 status = "disabled";
195 };
197 i2c0: i2c@11000 {
198 compatible = "marvell,mv64xxx-i2c";
199 reg = <0x11000 0x20>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
203 timeout-ms = <1000>;
204 clocks = <&coreclk 0>;
205 status = "disabled";
206 };
208 i2c1: i2c@11100 {
209 compatible = "marvell,mv64xxx-i2c";
210 reg = <0x11100 0x20>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
214 timeout-ms = <1000>;
215 clocks = <&coreclk 0>;
216 status = "disabled";
217 };
219 uart0: serial@12000 {
220 compatible = "snps,dw-apb-uart";
221 reg = <0x12000 0x100>;
222 reg-shift = <2>;
223 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
224 reg-io-width = <1>;
225 clocks = <&coreclk 0>;
226 status = "disabled";
227 };
229 uart1: serial@12100 {
230 compatible = "snps,dw-apb-uart";
231 reg = <0x12100 0x100>;
232 reg-shift = <2>;
233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
234 reg-io-width = <1>;
235 clocks = <&coreclk 0>;
236 status = "disabled";
237 };
239 pinctrl: pinctrl@18000 {
240 reg = <0x18000 0x20>;
242 ge0_rgmii_pins: ge-rgmii-pins-0 {
243 marvell,pins = "mpp6", "mpp7", "mpp8",
244 "mpp9", "mpp10", "mpp11",
245 "mpp12", "mpp13", "mpp14",
246 "mpp15", "mpp16", "mpp17";
247 marvell,function = "ge0";
248 };
250 ge1_rgmii_pins: ge-rgmii-pins-1 {
251 marvell,pins = "mpp21", "mpp27", "mpp28",
252 "mpp29", "mpp30", "mpp31",
253 "mpp32", "mpp37", "mpp38",
254 "mpp39", "mpp40", "mpp41";
255 marvell,function = "ge1";
256 };
258 i2c0_pins: i2c-pins-0 {
259 marvell,pins = "mpp2", "mpp3";
260 marvell,function = "i2c0";
261 };
263 mdio_pins: mdio-pins {
264 marvell,pins = "mpp4", "mpp5";
265 marvell,function = "ge";
266 };
268 ref_clk0_pins: ref-clk-pins-0 {
269 marvell,pins = "mpp45";
270 marvell,function = "ref";
271 };
273 ref_clk1_pins: ref-clk-pins-1 {
274 marvell,pins = "mpp46";
275 marvell,function = "ref";
276 };
278 spi0_pins: spi-pins-0 {
279 marvell,pins = "mpp22", "mpp23", "mpp24",
280 "mpp25";
281 marvell,function = "spi0";
282 };
284 spi1_pins: spi-pins-1 {
285 marvell,pins = "mpp56", "mpp57", "mpp58",
286 "mpp59";
287 marvell,function = "spi1";
288 };
290 uart0_pins: uart-pins-0 {
291 marvell,pins = "mpp0", "mpp1";
292 marvell,function = "ua0";
293 };
295 uart1_pins: uart-pins-1 {
296 marvell,pins = "mpp19", "mpp20";
297 marvell,function = "ua1";
298 };
300 sdhci_pins: sdhci-pins {
301 marvell,pins = "mpp48", "mpp49", "mpp50",
302 "mpp52", "mpp53", "mpp54",
303 "mpp55", "mpp57", "mpp58",
304 "mpp59";
305 marvell,function = "sd0";
306 };
308 sata0_pins: sata-pins-0 {
309 marvell,pins = "mpp20";
310 marvell,function = "sata0";
311 };
313 sata1_pins: sata-pins-1 {
314 marvell,pins = "mpp19";
315 marvell,function = "sata1";
316 };
318 sata2_pins: sata-pins-2 {
319 marvell,pins = "mpp47";
320 marvell,function = "sata2";
321 };
323 sata3_pins: sata-pins-3 {
324 marvell,pins = "mpp44";
325 marvell,function = "sata3";
326 };
327 };
329 gpio0: gpio@18100 {
330 compatible = "marvell,orion-gpio";
331 reg = <0x18100 0x40>;
332 ngpios = <32>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
341 };
343 gpio1: gpio@18140 {
344 compatible = "marvell,orion-gpio";
345 reg = <0x18140 0x40>;
346 ngpios = <28>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
355 };
357 system-controller@18200 {
358 compatible = "marvell,armada-380-system-controller",
359 "marvell,armada-370-xp-system-controller";
360 reg = <0x18200 0x100>;
361 };
363 gateclk: clock-gating-control@18220 {
364 compatible = "marvell,armada-380-gating-clock";
365 reg = <0x18220 0x4>;
366 clocks = <&coreclk 0>;
367 #clock-cells = <1>;
368 };
370 coreclk: mvebu-sar@18600 {
371 compatible = "marvell,armada-380-core-clock";
372 reg = <0x18600 0x04>;
373 #clock-cells = <1>;
374 };
376 mbusc: mbus-controller@20000 {
377 compatible = "marvell,mbus-controller";
378 reg = <0x20000 0x100>, <0x20180 0x20>;
379 };
381 mpic: interrupt-controller@20a00 {
382 compatible = "marvell,mpic";
383 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
384 #interrupt-cells = <1>;
385 #size-cells = <1>;
386 interrupt-controller;
387 msi-controller;
388 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
389 };
391 timer@20300 {
392 compatible = "marvell,armada-380-timer",
393 "marvell,armada-xp-timer";
394 reg = <0x20300 0x30>, <0x21040 0x30>;
395 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
396 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
397 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
398 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
399 <&mpic 5>,
400 <&mpic 6>;
401 clocks = <&coreclk 2>, <&refclk>;
402 clock-names = "nbclk", "fixed";
403 };
405 watchdog@20300 {
406 compatible = "marvell,armada-380-wdt";
407 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
408 clocks = <&coreclk 2>, <&refclk>;
409 clock-names = "nbclk", "fixed";
410 };
412 cpurst@20800 {
413 compatible = "marvell,armada-370-cpu-reset";
414 reg = <0x20800 0x10>;
415 };
417 mpcore-soc-ctrl@20d20 {
418 compatible = "marvell,armada-380-mpcore-soc-ctrl";
419 reg = <0x20d20 0x6c>;
420 };
422 coherency-fabric@21010 {
423 compatible = "marvell,armada-380-coherency-fabric";
424 reg = <0x21010 0x1c>;
425 };
427 pmsu@22000 {
428 compatible = "marvell,armada-380-pmsu";
429 reg = <0x22000 0x1000>;
430 };
432 /*
433 * As a special exception to the "order by
434 * register address" rule, the eth0 node is
435 * placed here to ensure that it gets
436 * registered as the first interface, since
437 * the network subsystem doesn't allow naming
438 * interfaces using DT aliases. Without this,
439 * the ordering of interfaces is different
440 * from the one used in U-Boot and the
441 * labeling of interfaces on the boards, which
442 * is very confusing for users.
443 */
444 eth0: ethernet@70000 {
445 compatible = "marvell,armada-370-neta";
446 reg = <0x70000 0x4000>;
447 interrupts-extended = <&mpic 8>;
448 clocks = <&gateclk 4>;
449 tx-csum-limit = <9800>;
450 status = "disabled";
451 };
453 eth1: ethernet@30000 {
454 compatible = "marvell,armada-370-neta";
455 reg = <0x30000 0x4000>;
456 interrupts-extended = <&mpic 10>;
457 clocks = <&gateclk 3>;
458 status = "disabled";
459 };
461 eth2: ethernet@34000 {
462 compatible = "marvell,armada-370-neta";
463 reg = <0x34000 0x4000>;
464 interrupts-extended = <&mpic 12>;
465 clocks = <&gateclk 2>;
466 status = "disabled";
467 };
469 usb@58000 {
470 compatible = "marvell,orion-ehci";
471 reg = <0x58000 0x500>;
472 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gateclk 18>;
474 status = "disabled";
475 };
477 xor@60800 {
478 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
479 reg = <0x60800 0x100
480 0x60a00 0x100>;
481 clocks = <&gateclk 22>;
482 status = "okay";
484 xor00 {
485 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
486 dmacap,memcpy;
487 dmacap,xor;
488 };
489 xor01 {
490 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
491 dmacap,memcpy;
492 dmacap,xor;
493 dmacap,memset;
494 };
495 };
497 xor@60900 {
498 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
499 reg = <0x60900 0x100
500 0x60b00 0x100>;
501 clocks = <&gateclk 28>;
502 status = "okay";
504 xor10 {
505 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
506 dmacap,memcpy;
507 dmacap,xor;
508 };
509 xor11 {
510 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
511 dmacap,memcpy;
512 dmacap,xor;
513 dmacap,memset;
514 };
515 };
517 mdio: mdio@72004 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 compatible = "marvell,orion-mdio";
521 reg = <0x72004 0x4>;
522 clocks = <&gateclk 4>;
523 };
525 crypto@90000 {
526 compatible = "marvell,armada-38x-crypto";
527 reg = <0x90000 0x10000>;
528 reg-names = "regs";
529 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&gateclk 23>, <&gateclk 21>,
532 <&gateclk 14>, <&gateclk 16>;
533 clock-names = "cesa0", "cesa1",
534 "cesaz0", "cesaz1";
535 marvell,crypto-srams = <&crypto_sram0>,
536 <&crypto_sram1>;
537 marvell,crypto-sram-size = <0x800>;
538 };
540 rtc@a3800 {
541 compatible = "marvell,armada-380-rtc";
542 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
543 reg-names = "rtc", "rtc-soc";
544 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
545 };
547 sata@a8000 {
548 compatible = "marvell,armada-380-ahci";
549 reg = <0xa8000 0x2000>;
550 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gateclk 15>;
552 status = "disabled";
553 };
555 bm: bm@c8000 {
556 compatible = "marvell,armada-380-neta-bm";
557 reg = <0xc8000 0xac>;
558 clocks = <&gateclk 13>;
559 internal-mem = <&bm_bppi>;
560 status = "disabled";
561 };
563 sata@e0000 {
564 compatible = "marvell,armada-380-ahci";
565 reg = <0xe0000 0x2000>;
566 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&gateclk 30>;
568 status = "disabled";
569 };
571 coredivclk: clock@e4250 {
572 compatible = "marvell,armada-380-corediv-clock";
573 reg = <0xe4250 0xc>;
574 #clock-cells = <1>;
575 clocks = <&mainpll>;
576 clock-output-names = "nand";
577 };
579 thermal@e8078 {
580 compatible = "marvell,armada380-thermal";
581 reg = <0xe4078 0x4>, <0xe4074 0x4>;
582 status = "okay";
583 };
585 flash@d0000 {
586 compatible = "marvell,armada370-nand";
587 reg = <0xd0000 0x54>;
588 #address-cells = <1>;
589 #size-cells = <1>;
590 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&coredivclk 0>;
592 status = "disabled";
593 };
595 sdhci@d8000 {
596 compatible = "marvell,armada-380-sdhci";
597 reg-names = "sdhci", "mbus", "conf-sdio3";
598 reg = <0xd8000 0x1000>,
599 <0xdc000 0x100>,
600 <0x18454 0x4>;
601 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&gateclk 17>;
603 mrvl,clk-delay-cycles = <0x1F>;
604 status = "disabled";
605 };
607 usb3@f0000 {
608 compatible = "marvell,armada-380-xhci";
609 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
610 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&gateclk 9>;
612 status = "disabled";
613 };
615 usb3@f8000 {
616 compatible = "marvell,armada-380-xhci";
617 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
618 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&gateclk 10>;
620 status = "disabled";
621 };
622 };
624 crypto_sram0: sa-sram0 {
625 compatible = "mmio-sram";
626 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
627 clocks = <&gateclk 23>;
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
631 };
633 crypto_sram1: sa-sram1 {
634 compatible = "mmio-sram";
635 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
636 clocks = <&gateclk 21>;
637 #address-cells = <1>;
638 #size-cells = <1>;
639 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
640 };
642 bm_bppi: bm-bppi {
643 compatible = "mmio-sram";
644 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
645 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
646 #address-cells = <1>;
647 #size-cells = <1>;
648 clocks = <&gateclk 13>;
649 no-memory-wc;
650 status = "disabled";
651 };
652 };
654 clocks {
655 /* 2 GHz fixed main PLL */
656 mainpll: mainpll {
657 compatible = "fixed-clock";
658 #clock-cells = <0>;
659 clock-frequency = <1000000000>;
660 };
662 /* 25 MHz reference crystal */
663 refclk: oscillator {
664 compatible = "fixed-clock";
665 #clock-cells = <0>;
666 clock-frequency = <25000000>;
667 };
668 };
669 };