| blob | f6cb7a80a2f55abdf23214fc3d5b58ec89b8dc80 |
1 /*
2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on at91sam9260.dtsi
9 *
10 * Licensed under GPLv2 or later.
11 */
13 #include "skeleton.dtsi"
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
19 / {
20 model = "Atmel AT91RM9200 family SoC";
21 compatible = "atmel,at91rm9200";
22 interrupt-parent = <&aic>;
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 tcb0 = &tcb0;
35 tcb1 = &tcb1;
36 i2c0 = &i2c0;
37 ssc0 = &ssc0;
38 ssc1 = &ssc1;
39 ssc2 = &ssc2;
40 };
41 cpus {
42 #address-cells = <0>;
43 #size-cells = <0>;
45 cpu {
46 compatible = "arm,arm920t";
47 device_type = "cpu";
48 };
49 };
51 memory {
52 reg = <0x20000000 0x04000000>;
53 };
55 clocks {
56 slow_xtal: slow_xtal {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <0>;
60 };
62 main_xtal: main_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67 };
69 sram: sram@00200000 {
70 compatible = "mmio-sram";
71 reg = <0x00200000 0x4000>;
72 };
74 ahb {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
80 apb {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
86 aic: interrupt-controller@fffff000 {
87 #interrupt-cells = <3>;
88 compatible = "atmel,at91rm9200-aic";
89 interrupt-controller;
90 reg = <0xfffff000 0x200>;
91 atmel,external-irqs = <25 26 27 28 29 30 31>;
92 };
94 ramc0: ramc@ffffff00 {
95 compatible = "atmel,at91rm9200-sdramc", "syscon";
96 reg = <0xffffff00 0x100>;
97 };
99 pmc: pmc@fffffc00 {
100 compatible = "atmel,at91rm9200-pmc", "syscon";
101 reg = <0xfffffc00 0x100>;
102 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
103 interrupt-controller;
104 #address-cells = <1>;
105 #size-cells = <0>;
106 #interrupt-cells = <1>;
108 main_osc: main_osc {
109 compatible = "atmel,at91rm9200-clk-main-osc";
110 #clock-cells = <0>;
111 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
112 clocks = <&main_xtal>;
113 };
115 main: mainck {
116 compatible = "atmel,at91rm9200-clk-main";
117 #clock-cells = <0>;
118 clocks = <&main_osc>;
119 };
121 plla: pllack {
122 compatible = "atmel,at91rm9200-clk-pll";
123 #clock-cells = <0>;
124 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
125 clocks = <&main>;
126 reg = <0>;
127 atmel,clk-input-range = <1000000 32000000>;
128 #atmel,pll-clk-output-range-cells = <3>;
129 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
130 <150000000 180000000 2>;
131 };
133 pllb: pllbck {
134 compatible = "atmel,at91rm9200-clk-pll";
135 #clock-cells = <0>;
136 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
137 clocks = <&main>;
138 reg = <1>;
139 atmel,clk-input-range = <1000000 32000000>;
140 #atmel,pll-clk-output-range-cells = <3>;
141 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
142 <150000000 180000000 2>;
143 };
145 mck: masterck {
146 compatible = "atmel,at91rm9200-clk-master";
147 #clock-cells = <0>;
148 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
149 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
150 atmel,clk-output-range = <0 80000000>;
151 atmel,clk-divisors = <1 2 3 4>;
152 };
154 usb: usbck {
155 compatible = "atmel,at91rm9200-clk-usb";
156 #clock-cells = <0>;
157 atmel,clk-divisors = <1 2 0 0>;
158 clocks = <&pllb>;
159 };
161 prog: progck {
162 compatible = "atmel,at91rm9200-clk-programmable";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupt-parent = <&pmc>;
166 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
168 prog0: prog0 {
169 #clock-cells = <0>;
170 reg = <0>;
171 interrupts = <AT91_PMC_PCKRDY(0)>;
172 };
174 prog1: prog1 {
175 #clock-cells = <0>;
176 reg = <1>;
177 interrupts = <AT91_PMC_PCKRDY(1)>;
178 };
180 prog2: prog2 {
181 #clock-cells = <0>;
182 reg = <2>;
183 interrupts = <AT91_PMC_PCKRDY(2)>;
184 };
186 prog3: prog3 {
187 #clock-cells = <0>;
188 reg = <3>;
189 interrupts = <AT91_PMC_PCKRDY(3)>;
190 };
191 };
193 systemck {
194 compatible = "atmel,at91rm9200-clk-system";
195 #address-cells = <1>;
196 #size-cells = <0>;
198 udpck: udpck {
199 #clock-cells = <0>;
200 reg = <2>;
201 clocks = <&usb>;
202 };
204 uhpck: uhpck {
205 #clock-cells = <0>;
206 reg = <4>;
207 clocks = <&usb>;
208 };
210 pck0: pck0 {
211 #clock-cells = <0>;
212 reg = <8>;
213 clocks = <&prog0>;
214 };
216 pck1: pck1 {
217 #clock-cells = <0>;
218 reg = <9>;
219 clocks = <&prog1>;
220 };
222 pck2: pck2 {
223 #clock-cells = <0>;
224 reg = <10>;
225 clocks = <&prog2>;
226 };
228 pck3: pck3 {
229 #clock-cells = <0>;
230 reg = <11>;
231 clocks = <&prog3>;
232 };
233 };
235 periphck {
236 compatible = "atmel,at91rm9200-clk-peripheral";
237 #address-cells = <1>;
238 #size-cells = <0>;
239 clocks = <&mck>;
241 pioA_clk: pioA_clk {
242 #clock-cells = <0>;
243 reg = <2>;
244 };
246 pioB_clk: pioB_clk {
247 #clock-cells = <0>;
248 reg = <3>;
249 };
251 pioC_clk: pioC_clk {
252 #clock-cells = <0>;
253 reg = <4>;
254 };
256 pioD_clk: pioD_clk {
257 #clock-cells = <0>;
258 reg = <5>;
259 };
261 usart0_clk: usart0_clk {
262 #clock-cells = <0>;
263 reg = <6>;
264 };
266 usart1_clk: usart1_clk {
267 #clock-cells = <0>;
268 reg = <7>;
269 };
271 usart2_clk: usart2_clk {
272 #clock-cells = <0>;
273 reg = <8>;
274 };
276 usart3_clk: usart3_clk {
277 #clock-cells = <0>;
278 reg = <9>;
279 };
281 mci0_clk: mci0_clk {
282 #clock-cells = <0>;
283 reg = <10>;
284 };
286 udc_clk: udc_clk {
287 #clock-cells = <0>;
288 reg = <11>;
289 };
291 twi0_clk: twi0_clk {
292 reg = <12>;
293 #clock-cells = <0>;
294 };
296 spi0_clk: spi0_clk {
297 #clock-cells = <0>;
298 reg = <13>;
299 };
301 ssc0_clk: ssc0_clk {
302 #clock-cells = <0>;
303 reg = <14>;
304 };
306 ssc1_clk: ssc1_clk {
307 #clock-cells = <0>;
308 reg = <15>;
309 };
311 ssc2_clk: ssc2_clk {
312 #clock-cells = <0>;
313 reg = <16>;
314 };
316 tc0_clk: tc0_clk {
317 #clock-cells = <0>;
318 reg = <17>;
319 };
321 tc1_clk: tc1_clk {
322 #clock-cells = <0>;
323 reg = <18>;
324 };
326 tc2_clk: tc2_clk {
327 #clock-cells = <0>;
328 reg = <19>;
329 };
331 tc3_clk: tc3_clk {
332 #clock-cells = <0>;
333 reg = <20>;
334 };
336 tc4_clk: tc4_clk {
337 #clock-cells = <0>;
338 reg = <21>;
339 };
341 tc5_clk: tc5_clk {
342 #clock-cells = <0>;
343 reg = <22>;
344 };
346 ohci_clk: ohci_clk {
347 #clock-cells = <0>;
348 reg = <23>;
349 };
351 macb0_clk: macb0_clk {
352 #clock-cells = <0>;
353 reg = <24>;
354 };
355 };
356 };
358 st: timer@fffffd00 {
359 compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
360 reg = <0xfffffd00 0x100>;
361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
362 clocks = <&slow_xtal>;
364 watchdog {
365 compatible = "atmel,at91rm9200-wdt";
366 };
367 };
369 rtc: rtc@fffffe00 {
370 compatible = "atmel,at91rm9200-rtc";
371 reg = <0xfffffe00 0x40>;
372 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
373 clocks = <&slow_xtal>;
374 status = "disabled";
375 };
377 tcb0: timer@fffa0000 {
378 compatible = "atmel,at91rm9200-tcb";
379 reg = <0xfffa0000 0x100>;
380 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
381 18 IRQ_TYPE_LEVEL_HIGH 0
382 19 IRQ_TYPE_LEVEL_HIGH 0>;
383 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
384 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
385 };
387 tcb1: timer@fffa4000 {
388 compatible = "atmel,at91rm9200-tcb";
389 reg = <0xfffa4000 0x100>;
390 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
391 21 IRQ_TYPE_LEVEL_HIGH 0
392 22 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
394 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
395 };
397 i2c0: i2c@fffb8000 {
398 compatible = "atmel,at91rm9200-i2c";
399 reg = <0xfffb8000 0x4000>;
400 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_twi>;
403 clocks = <&twi0_clk>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 status = "disabled";
407 };
409 mmc0: mmc@fffb4000 {
410 compatible = "atmel,hsmci";
411 reg = <0xfffb4000 0x4000>;
412 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
413 clocks = <&mci0_clk>;
414 clock-names = "mci_clk";
415 #address-cells = <1>;
416 #size-cells = <0>;
417 pinctrl-names = "default";
418 status = "disabled";
419 };
421 ssc0: ssc@fffd0000 {
422 compatible = "atmel,at91rm9200-ssc";
423 reg = <0xfffd0000 0x4000>;
424 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
427 clocks = <&ssc0_clk>;
428 clock-names = "pclk";
429 status = "disabled";
430 };
432 ssc1: ssc@fffd4000 {
433 compatible = "atmel,at91rm9200-ssc";
434 reg = <0xfffd4000 0x4000>;
435 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
438 clocks = <&ssc1_clk>;
439 clock-names = "pclk";
440 status = "disabled";
441 };
443 ssc2: ssc@fffd8000 {
444 compatible = "atmel,at91rm9200-ssc";
445 reg = <0xfffd8000 0x4000>;
446 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
449 clocks = <&ssc2_clk>;
450 clock-names = "pclk";
451 status = "disabled";
452 };
454 macb0: ethernet@fffbc000 {
455 compatible = "cdns,at91rm9200-emac", "cdns,emac";
456 reg = <0xfffbc000 0x4000>;
457 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
458 phy-mode = "rmii";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_macb_rmii>;
461 clocks = <&macb0_clk>;
462 clock-names = "ether_clk";
463 status = "disabled";
464 };
466 pinctrl@fffff400 {
467 #address-cells = <1>;
468 #size-cells = <1>;
469 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
470 ranges = <0xfffff400 0xfffff400 0x800>;
472 atmel,mux-mask = <
473 /* A B */
474 0xffffffff 0xffffffff /* pioA */
475 0xffffffff 0x083fffff /* pioB */
476 0xffff3fff 0x00000000 /* pioC */
477 0x03ff87ff 0x0fffff80 /* pioD */
478 >;
480 /* shared pinctrl settings */
481 dbgu {
482 pinctrl_dbgu: dbgu-0 {
483 atmel,pins =
484 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
485 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
486 };
487 };
489 uart0 {
490 pinctrl_uart0: uart0-0 {
491 atmel,pins =
492 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
493 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
494 };
496 pinctrl_uart0_cts: uart0_cts-0 {
497 atmel,pins =
498 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
499 };
501 pinctrl_uart0_rts: uart0_rts-0 {
502 atmel,pins =
503 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
504 };
505 };
507 uart1 {
508 pinctrl_uart1: uart1-0 {
509 atmel,pins =
510 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
511 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
512 };
514 pinctrl_uart1_rts: uart1_rts-0 {
515 atmel,pins =
516 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
517 };
519 pinctrl_uart1_cts: uart1_cts-0 {
520 atmel,pins =
521 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
522 };
524 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
525 atmel,pins =
526 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
527 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
528 };
530 pinctrl_uart1_dcd: uart1_dcd-0 {
531 atmel,pins =
532 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
533 };
535 pinctrl_uart1_ri: uart1_ri-0 {
536 atmel,pins =
537 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
538 };
539 };
541 uart2 {
542 pinctrl_uart2: uart2-0 {
543 atmel,pins =
544 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
545 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
546 };
548 pinctrl_uart2_rts: uart2_rts-0 {
549 atmel,pins =
550 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
551 };
553 pinctrl_uart2_cts: uart2_cts-0 {
554 atmel,pins =
555 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
556 };
557 };
559 uart3 {
560 pinctrl_uart3: uart3-0 {
561 atmel,pins =
562 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
563 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
564 };
566 pinctrl_uart3_rts: uart3_rts-0 {
567 atmel,pins =
568 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
569 };
571 pinctrl_uart3_cts: uart3_cts-0 {
572 atmel,pins =
573 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
574 };
575 };
577 nand {
578 pinctrl_nand: nand-0 {
579 atmel,pins =
580 <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
581 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
582 };
583 };
585 macb {
586 pinctrl_macb_rmii: macb_rmii-0 {
587 atmel,pins =
588 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
589 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
590 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
591 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
592 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
593 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
594 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
595 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
596 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
597 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
598 };
600 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
601 atmel,pins =
602 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
603 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
604 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
605 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
606 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
607 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
608 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
609 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
610 };
611 };
613 mmc0 {
614 pinctrl_mmc0_clk: mmc0_clk-0 {
615 atmel,pins =
616 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
617 };
619 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
620 atmel,pins =
621 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
622 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
623 };
625 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
626 atmel,pins =
627 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
628 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
629 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
630 };
632 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
633 atmel,pins =
634 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
635 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
636 };
638 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
639 atmel,pins =
640 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
641 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
642 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
643 };
644 };
646 ssc0 {
647 pinctrl_ssc0_tx: ssc0_tx-0 {
648 atmel,pins =
649 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
650 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
651 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
652 };
654 pinctrl_ssc0_rx: ssc0_rx-0 {
655 atmel,pins =
656 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
657 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
658 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
659 };
660 };
662 ssc1 {
663 pinctrl_ssc1_tx: ssc1_tx-0 {
664 atmel,pins =
665 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
666 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
667 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
668 };
670 pinctrl_ssc1_rx: ssc1_rx-0 {
671 atmel,pins =
672 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
673 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
674 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
675 };
676 };
678 ssc2 {
679 pinctrl_ssc2_tx: ssc2_tx-0 {
680 atmel,pins =
681 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
682 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
683 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
684 };
686 pinctrl_ssc2_rx: ssc2_rx-0 {
687 atmel,pins =
688 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
689 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
690 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
691 };
692 };
694 twi {
695 pinctrl_twi: twi-0 {
696 atmel,pins =
697 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
698 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
699 };
701 pinctrl_twi_gpio: twi_gpio-0 {
702 atmel,pins =
703 <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
704 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
705 };
706 };
708 tcb0 {
709 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
710 atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
711 };
713 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
714 atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
715 };
717 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
718 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
719 };
721 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
722 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
723 };
725 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
726 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
727 };
729 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
730 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
731 };
733 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
734 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
735 };
737 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
738 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
739 };
741 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
742 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
743 };
744 };
746 tcb1 {
747 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
748 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
749 };
751 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
752 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
753 };
755 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
756 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
757 };
759 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
760 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
761 };
763 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
764 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
765 };
767 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
768 atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
769 };
771 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
772 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
773 };
775 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
776 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
777 };
779 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
780 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
781 };
782 };
784 spi0 {
785 pinctrl_spi0: spi0-0 {
786 atmel,pins =
787 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
788 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
789 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
790 };
791 };
793 pioA: gpio@fffff400 {
794 compatible = "atmel,at91rm9200-gpio";
795 reg = <0xfffff400 0x200>;
796 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
797 #gpio-cells = <2>;
798 gpio-controller;
799 interrupt-controller;
800 #interrupt-cells = <2>;
801 clocks = <&pioA_clk>;
802 };
804 pioB: gpio@fffff600 {
805 compatible = "atmel,at91rm9200-gpio";
806 reg = <0xfffff600 0x200>;
807 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
808 #gpio-cells = <2>;
809 gpio-controller;
810 interrupt-controller;
811 #interrupt-cells = <2>;
812 clocks = <&pioB_clk>;
813 };
815 pioC: gpio@fffff800 {
816 compatible = "atmel,at91rm9200-gpio";
817 reg = <0xfffff800 0x200>;
818 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
819 #gpio-cells = <2>;
820 gpio-controller;
821 interrupt-controller;
822 #interrupt-cells = <2>;
823 clocks = <&pioC_clk>;
824 };
826 pioD: gpio@fffffa00 {
827 compatible = "atmel,at91rm9200-gpio";
828 reg = <0xfffffa00 0x200>;
829 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
830 #gpio-cells = <2>;
831 gpio-controller;
832 interrupt-controller;
833 #interrupt-cells = <2>;
834 clocks = <&pioD_clk>;
835 };
836 };
838 dbgu: serial@fffff200 {
839 compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
840 reg = <0xfffff200 0x200>;
841 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
842 pinctrl-names = "default";
843 pinctrl-0 = <&pinctrl_dbgu>;
844 clocks = <&mck>;
845 clock-names = "usart";
846 status = "disabled";
847 };
849 usart0: serial@fffc0000 {
850 compatible = "atmel,at91rm9200-usart";
851 reg = <0xfffc0000 0x200>;
852 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
853 atmel,use-dma-rx;
854 atmel,use-dma-tx;
855 pinctrl-names = "default";
856 pinctrl-0 = <&pinctrl_uart0>;
857 clocks = <&usart0_clk>;
858 clock-names = "usart";
859 status = "disabled";
860 };
862 usart1: serial@fffc4000 {
863 compatible = "atmel,at91rm9200-usart";
864 reg = <0xfffc4000 0x200>;
865 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
866 atmel,use-dma-rx;
867 atmel,use-dma-tx;
868 pinctrl-names = "default";
869 pinctrl-0 = <&pinctrl_uart1>;
870 clocks = <&usart1_clk>;
871 clock-names = "usart";
872 status = "disabled";
873 };
875 usart2: serial@fffc8000 {
876 compatible = "atmel,at91rm9200-usart";
877 reg = <0xfffc8000 0x200>;
878 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
879 atmel,use-dma-rx;
880 atmel,use-dma-tx;
881 pinctrl-names = "default";
882 pinctrl-0 = <&pinctrl_uart2>;
883 clocks = <&usart2_clk>;
884 clock-names = "usart";
885 status = "disabled";
886 };
888 usart3: serial@fffcc000 {
889 compatible = "atmel,at91rm9200-usart";
890 reg = <0xfffcc000 0x200>;
891 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
892 atmel,use-dma-rx;
893 atmel,use-dma-tx;
894 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_uart3>;
896 clocks = <&usart3_clk>;
897 clock-names = "usart";
898 status = "disabled";
899 };
901 usb1: gadget@fffb0000 {
902 compatible = "atmel,at91rm9200-udc";
903 reg = <0xfffb0000 0x4000>;
904 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
905 clocks = <&udc_clk>, <&udpck>;
906 clock-names = "pclk", "hclk";
907 status = "disabled";
908 };
910 spi0: spi@fffe0000 {
911 #address-cells = <1>;
912 #size-cells = <0>;
913 compatible = "atmel,at91rm9200-spi";
914 reg = <0xfffe0000 0x200>;
915 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
916 pinctrl-names = "default";
917 pinctrl-0 = <&pinctrl_spi0>;
918 clocks = <&spi0_clk>;
919 clock-names = "spi_clk";
920 status = "disabled";
921 };
922 };
924 nand0: nand@40000000 {
925 compatible = "atmel,at91rm9200-nand";
926 #address-cells = <1>;
927 #size-cells = <1>;
928 reg = <0x40000000 0x10000000>;
929 atmel,nand-addr-offset = <21>;
930 atmel,nand-cmd-offset = <22>;
931 pinctrl-names = "default";
932 pinctrl-0 = <&pinctrl_nand>;
933 nand-ecc-mode = "soft";
934 gpios = <&pioC 2 GPIO_ACTIVE_HIGH
935 0
936 &pioB 1 GPIO_ACTIVE_HIGH
937 >;
938 status = "disabled";
939 };
941 usb0: ohci@00300000 {
942 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
943 reg = <0x00300000 0x100000>;
944 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
945 clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
946 clock-names = "ohci_clk", "hclk", "uhpck";
947 status = "disabled";
948 };
949 };
951 i2c@0 {
952 compatible = "i2c-gpio";
953 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
954 &pioA 26 GPIO_ACTIVE_HIGH /* scl */
955 >;
956 i2c-gpio,sda-open-drain;
957 i2c-gpio,scl-open-drain;
958 i2c-gpio,delay-us = <2>; /* ~100 kHz */
959 pinctrl-names = "default";
960 pinctrl-0 = <&pinctrl_twi_gpio>;
961 #address-cells = <1>;
962 #size-cells = <0>;
963 status = "disabled";
964 };
965 };