| blob | 6d06b6118d8373844f6bfb957419c28de353277e |
1 /*
2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
42 #include "skeleton.dtsi"
43 #include <dt-bindings/clock/berlin2.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 / {
47 model = "Marvell Armada 1500-mini (BG2CD) SoC";
48 compatible = "marvell,berlin2cd", "marvell,berlin";
50 aliases {
51 serial0 = &uart0;
52 serial1 = &uart1;
53 };
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
59 cpu@0 {
60 compatible = "arm,cortex-a9";
61 device_type = "cpu";
62 next-level-cache = <&l2>;
63 reg = <0>;
65 clocks = <&chip_clk CLKID_CPU>;
66 clock-latency = <100000>;
67 operating-points = <
68 /* kHz uV */
69 800000 1200000
70 600000 1200000
71 >;
72 };
73 };
75 refclk: oscillator {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <25000000>;
79 };
81 soc {
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 interrupt-parent = <&gic>;
87 ranges = <0 0xf7000000 0x1000000>;
89 pmu {
90 compatible = "arm,cortex-a9-pmu";
91 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
92 };
94 sdhci0: sdhci@ab0000 {
95 compatible = "mrvl,pxav3-mmc";
96 reg = <0xab0000 0x200>;
97 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
98 clock-names = "io", "core";
99 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
100 status = "disabled";
101 };
103 l2: l2-cache-controller@ac0000 {
104 compatible = "arm,pl310-cache";
105 reg = <0xac0000 0x1000>;
106 cache-unified;
107 cache-level = <2>;
108 };
110 gic: interrupt-controller@ad1000 {
111 compatible = "arm,cortex-a9-gic";
112 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
115 };
117 local-timer@ad0600 {
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0xad0600 0x20>;
120 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
121 clocks = <&chip_clk CLKID_TWD>;
122 };
124 usb_phy0: usb-phy@b74000 {
125 compatible = "marvell,berlin2cd-usb-phy";
126 reg = <0xb74000 0x128>;
127 #phy-cells = <0>;
128 resets = <&chip_rst 0x178 23>;
129 status = "disabled";
130 };
132 usb_phy1: usb-phy@b78000 {
133 compatible = "marvell,berlin2cd-usb-phy";
134 reg = <0xb78000 0x128>;
135 #phy-cells = <0>;
136 resets = <&chip_rst 0x178 24>;
137 status = "disabled";
138 };
140 eth1: ethernet@b90000 {
141 compatible = "marvell,pxa168-eth";
142 reg = <0xb90000 0x10000>;
143 clocks = <&chip_clk CLKID_GETH1>;
144 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
145 /* set by bootloader */
146 local-mac-address = [00 00 00 00 00 00];
147 #address-cells = <1>;
148 #size-cells = <0>;
149 phy-connection-type = "mii";
150 phy-handle = <ðphy1>;
151 status = "disabled";
153 ethphy1: ethernet-phy@0 {
154 reg = <0>;
155 };
156 };
158 eth0: ethernet@e50000 {
159 compatible = "marvell,pxa168-eth";
160 reg = <0xe50000 0x10000>;
161 clocks = <&chip_clk CLKID_GETH0>;
162 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
163 /* set by bootloader */
164 local-mac-address = [00 00 00 00 00 00];
165 #address-cells = <1>;
166 #size-cells = <0>;
167 phy-connection-type = "mii";
168 phy-handle = <ðphy0>;
169 status = "disabled";
171 ethphy0: ethernet-phy@0 {
172 reg = <0>;
173 };
174 };
176 apb@e80000 {
177 compatible = "simple-bus";
178 #address-cells = <1>;
179 #size-cells = <1>;
181 ranges = <0 0xe80000 0x10000>;
182 interrupt-parent = <&aic>;
184 gpio0: gpio@0400 {
185 compatible = "snps,dw-apb-gpio";
186 reg = <0x0400 0x400>;
187 #address-cells = <1>;
188 #size-cells = <0>;
190 porta: gpio-port@0 {
191 compatible = "snps,dw-apb-gpio-port";
192 gpio-controller;
193 #gpio-cells = <2>;
194 snps,nr-gpios = <8>;
195 reg = <0>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 interrupts = <0>;
199 };
200 };
202 gpio1: gpio@0800 {
203 compatible = "snps,dw-apb-gpio";
204 reg = <0x0800 0x400>;
205 #address-cells = <1>;
206 #size-cells = <0>;
208 portb: gpio-port@1 {
209 compatible = "snps,dw-apb-gpio-port";
210 gpio-controller;
211 #gpio-cells = <2>;
212 snps,nr-gpios = <8>;
213 reg = <0>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
216 interrupts = <1>;
217 };
218 };
220 gpio2: gpio@0c00 {
221 compatible = "snps,dw-apb-gpio";
222 reg = <0x0c00 0x400>;
223 #address-cells = <1>;
224 #size-cells = <0>;
226 portc: gpio-port@2 {
227 compatible = "snps,dw-apb-gpio-port";
228 gpio-controller;
229 #gpio-cells = <2>;
230 snps,nr-gpios = <8>;
231 reg = <0>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
234 interrupts = <2>;
235 };
236 };
238 gpio3: gpio@1000 {
239 compatible = "snps,dw-apb-gpio";
240 reg = <0x1000 0x400>;
241 #address-cells = <1>;
242 #size-cells = <0>;
244 portd: gpio-port@3 {
245 compatible = "snps,dw-apb-gpio-port";
246 gpio-controller;
247 #gpio-cells = <2>;
248 snps,nr-gpios = <8>;
249 reg = <0>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 interrupts = <3>;
253 };
254 };
256 timer0: timer@2c00 {
257 compatible = "snps,dw-apb-timer";
258 reg = <0x2c00 0x14>;
259 interrupts = <8>;
260 clocks = <&chip_clk CLKID_CFG>;
261 clock-names = "timer";
262 status = "okay";
263 };
265 timer1: timer@2c14 {
266 compatible = "snps,dw-apb-timer";
267 reg = <0x2c14 0x14>;
268 interrupts = <9>;
269 clocks = <&chip_clk CLKID_CFG>;
270 clock-names = "timer";
271 status = "okay";
272 };
274 timer2: timer@2c28 {
275 compatible = "snps,dw-apb-timer";
276 reg = <0x2c28 0x14>;
277 interrupts = <10>;
278 clocks = <&chip_clk CLKID_CFG>;
279 clock-names = "timer";
280 status = "disabled";
281 };
283 timer3: timer@2c3c {
284 compatible = "snps,dw-apb-timer";
285 reg = <0x2c3c 0x14>;
286 interrupts = <11>;
287 clocks = <&chip_clk CLKID_CFG>;
288 clock-names = "timer";
289 status = "disabled";
290 };
292 timer4: timer@2c50 {
293 compatible = "snps,dw-apb-timer";
294 reg = <0x2c50 0x14>;
295 interrupts = <12>;
296 clocks = <&chip_clk CLKID_CFG>;
297 clock-names = "timer";
298 status = "disabled";
299 };
301 timer5: timer@2c64 {
302 compatible = "snps,dw-apb-timer";
303 reg = <0x2c64 0x14>;
304 interrupts = <13>;
305 clocks = <&chip_clk CLKID_CFG>;
306 clock-names = "timer";
307 status = "disabled";
308 };
310 timer6: timer@2c78 {
311 compatible = "snps,dw-apb-timer";
312 reg = <0x2c78 0x14>;
313 interrupts = <14>;
314 clocks = <&chip_clk CLKID_CFG>;
315 clock-names = "timer";
316 status = "disabled";
317 };
319 timer7: timer@2c8c {
320 compatible = "snps,dw-apb-timer";
321 reg = <0x2c8c 0x14>;
322 interrupts = <15>;
323 clocks = <&chip_clk CLKID_CFG>;
324 clock-names = "timer";
325 status = "disabled";
326 };
328 aic: interrupt-controller@3000 {
329 compatible = "snps,dw-apb-ictl";
330 reg = <0x3000 0xc00>;
331 interrupt-controller;
332 #interrupt-cells = <1>;
333 interrupt-parent = <&gic>;
334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
335 };
336 };
338 chip: chip-control@ea0000 {
339 compatible = "simple-mfd", "syscon";
340 reg = <0xea0000 0x400>;
342 chip_clk: clock {
343 compatible = "marvell,berlin2-clk";
344 #clock-cells = <1>;
345 clocks = <&refclk>;
346 clock-names = "refclk";
347 };
349 soc_pinctrl: pin-controller {
350 compatible = "marvell,berlin2cd-soc-pinctrl";
352 uart0_pmux: uart0-pmux {
353 groups = "G6";
354 function = "uart0";
355 };
356 };
358 chip_rst: reset {
359 compatible = "marvell,berlin2-reset";
360 #reset-cells = <2>;
361 };
362 };
364 usb0: usb@ed0000 {
365 compatible = "chipidea,usb2";
366 reg = <0xed0000 0x200>;
367 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&chip_clk CLKID_USB0>;
369 phys = <&usb_phy0>;
370 phy-names = "usb-phy";
371 status = "disabled";
372 };
374 usb1: usb@ee0000 {
375 compatible = "chipidea,usb2";
376 reg = <0xee0000 0x200>;
377 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&chip_clk CLKID_USB1>;
379 phys = <&usb_phy1>;
380 phy-names = "usb-phy";
381 status = "disabled";
382 };
384 pwm: pwm@f20000 {
385 compatible = "marvell,berlin-pwm";
386 reg = <0xf20000 0x40>;
387 clocks = <&chip_clk CLKID_CFG>;
388 #pwm-cells = <3>;
389 };
391 apb@fc0000 {
392 compatible = "simple-bus";
393 #address-cells = <1>;
394 #size-cells = <1>;
396 ranges = <0 0xfc0000 0x10000>;
397 interrupt-parent = <&sic>;
399 wdt0: watchdog@1000 {
400 compatible = "snps,dw-wdt";
401 reg = <0x1000 0x100>;
402 clocks = <&refclk>;
403 interrupts = <0>;
404 };
406 wdt1: watchdog@2000 {
407 compatible = "snps,dw-wdt";
408 reg = <0x2000 0x100>;
409 clocks = <&refclk>;
410 interrupts = <1>;
411 status = "disabled";
412 };
414 wdt2: watchdog@3000 {
415 compatible = "snps,dw-wdt";
416 reg = <0x3000 0x100>;
417 clocks = <&refclk>;
418 interrupts = <2>;
419 status = "disabled";
420 };
422 sm_gpio1: gpio@5000 {
423 compatible = "snps,dw-apb-gpio";
424 reg = <0x5000 0x400>;
425 #address-cells = <1>;
426 #size-cells = <0>;
428 portf: gpio-port@5 {
429 compatible = "snps,dw-apb-gpio-port";
430 gpio-controller;
431 #gpio-cells = <2>;
432 snps,nr-gpios = <8>;
433 reg = <0>;
434 };
435 };
437 sm_gpio0: gpio@c000 {
438 compatible = "snps,dw-apb-gpio";
439 reg = <0xc000 0x400>;
440 #address-cells = <1>;
441 #size-cells = <0>;
443 porte: gpio-port@4 {
444 compatible = "snps,dw-apb-gpio-port";
445 gpio-controller;
446 #gpio-cells = <2>;
447 snps,nr-gpios = <8>;
448 reg = <0>;
449 };
450 };
452 uart0: serial@9000 {
453 compatible = "snps,dw-apb-uart";
454 reg = <0x9000 0x100>;
455 reg-shift = <2>;
456 reg-io-width = <1>;
457 interrupts = <8>;
458 clocks = <&refclk>;
459 pinctrl-0 = <&uart0_pmux>;
460 pinctrl-names = "default";
461 status = "disabled";
462 };
464 uart1: serial@a000 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0xa000 0x100>;
467 reg-shift = <2>;
468 reg-io-width = <1>;
469 interrupts = <9>;
470 clocks = <&refclk>;
471 status = "disabled";
472 };
474 sysctrl: system-controller@d000 {
475 compatible = "simple-mfd", "syscon";
476 reg = <0xd000 0x100>;
478 sys_pinctrl: pin-controller {
479 compatible = "marvell,berlin2cd-system-pinctrl";
480 };
481 };
483 sic: interrupt-controller@e000 {
484 compatible = "snps,dw-apb-ictl";
485 reg = <0xe000 0x400>;
486 interrupt-controller;
487 #interrupt-cells = <1>;
488 interrupt-parent = <&gic>;
489 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
490 };
491 };
492 };
493 };