arch/arm/boot/dts/exynos4212.dtsi

   1 /*
   2  * Samsung's Exynos4212 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4x12.dtsi"
  21
  22 / {
  23         compatible = "samsung,exynos4212", "samsung,exynos4";
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@A00 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <0xA00>;
  33                         clocks = <&clock CLK_ARM_CLK>;
  34                         clock-names = "cpu";
  35                         operating-points-v2 = <&cpu0_opp_table>;
  36                         cooling-min-level = <13>;
  37                         cooling-max-level = <7>;
  38                         #cooling-cells = <2>; /* min followed by max */
  39                 };
  40
  41                 cpu@A01 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <0xA01>;
  45                         operating-points-v2 = <&cpu0_opp_table>;
  46                 };
  47         };
  48
  49         cpu0_opp_table: opp_table0 {
  50                 compatible = "operating-points-v2";
  51                 opp-shared;
  52
  53                 opp00 {
  54                         opp-hz = /bits/ 64 <200000000>;
  55                         opp-microvolt = <900000>;
  56                         clock-latency-ns = <200000>;
  57                 };
  58                 opp01 {
  59                         opp-hz = /bits/ 64 <300000000>;
  60                         opp-microvolt = <900000>;
  61                         clock-latency-ns = <200000>;
  62                 };
  63                 opp02 {
  64                         opp-hz = /bits/ 64 <400000000>;
  65                         opp-microvolt = <925000>;
  66                         clock-latency-ns = <200000>;
  67                 };
  68                 opp03 {
  69                         opp-hz = /bits/ 64 <500000000>;
  70                         opp-microvolt = <950000>;
  71                         clock-latency-ns = <200000>;
  72                 };
  73                 opp04 {
  74                         opp-hz = /bits/ 64 <600000000>;
  75                         opp-microvolt = <975000>;
  76                         clock-latency-ns = <200000>;
  77                 };
  78                 opp05 {
  79                         opp-hz = /bits/ 64 <700000000>;
  80                         opp-microvolt = <987500>;
  81                         clock-latency-ns = <200000>;
  82                 };
  83                 opp06 {
  84                         opp-hz = /bits/ 64 <800000000>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <200000>;
  87                 };
  88                 opp07 {
  89                         opp-hz = /bits/ 64 <900000000>;
  90                         opp-microvolt = <1037500>;
  91                         clock-latency-ns = <200000>;
  92                 };
  93                 opp08 {
  94                         opp-hz = /bits/ 64 <1000000000>;
  95                         opp-microvolt = <1087500>;
  96                         clock-latency-ns = <200000>;
  97                 };
  98                 opp09 {
  99                         opp-hz = /bits/ 64 <1100000000>;
 100                         opp-microvolt = <1137500>;
 101                         clock-latency-ns = <200000>;
 102                 };
 103                 opp10 {
 104                         opp-hz = /bits/ 64 <1200000000>;
 105                         opp-microvolt = <1187500>;
 106                         clock-latency-ns = <200000>;
 107                 };
 108                 opp11 {
 109                         opp-hz = /bits/ 64 <1300000000>;
 110                         opp-microvolt = <1250000>;
 111                         clock-latency-ns = <200000>;
 112                 };
 113                 opp12 {
 114                         opp-hz = /bits/ 64 <1400000000>;
 115                         opp-microvolt = <1287500>;
 116                         clock-latency-ns = <200000>;
 117                 };
 118                 opp13 {
 119                         opp-hz = /bits/ 64 <1500000000>;
 120                         opp-microvolt = <1350000>;
 121                         clock-latency-ns = <200000>;
 122                         turbo-mode;
 123                 };
 124         };
 125 };
 126
 127 &combiner {
 128         samsung,combiner-nr = <18>;
 129 };
 130
 131 &gic {
 132         cpu-offset = <0x8000>;
 133 };