| blob | c85d07e6db6121c39870b3bb5f07f58700975901 |
1 /*
2 * Hisilicon Ltd. Hi3620 SoC
3 *
4 * Copyright (C) 2012-2013 Hisilicon Ltd.
5 * Copyright (C) 2012-2013 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * publishhed by the Free Software Foundation.
12 */
14 #include "skeleton.dtsi"
15 #include <dt-bindings/clock/hi3620-clock.h>
17 / {
18 aliases {
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 };
26 pclk: clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <26000000>;
30 clock-output-names = "apb_pclk";
31 };
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "hisilicon,hi3620-smp";
38 cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0x0>;
42 next-level-cache = <&L2>;
43 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
47 device_type = "cpu";
48 reg = <1>;
49 next-level-cache = <&L2>;
50 };
52 cpu@2 {
53 compatible = "arm,cortex-a9";
54 device_type = "cpu";
55 reg = <2>;
56 next-level-cache = <&L2>;
57 };
59 cpu@3 {
60 compatible = "arm,cortex-a9";
61 device_type = "cpu";
62 reg = <3>;
63 next-level-cache = <&L2>;
64 };
65 };
67 amba {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 interrupt-parent = <&gic>;
73 ranges = <0 0xfc000000 0x2000000>;
75 L2: l2-cache {
76 compatible = "arm,pl310-cache";
77 reg = <0x100000 0x100000>;
78 interrupts = <0 15 4>;
79 cache-unified;
80 cache-level = <2>;
81 };
83 gic: interrupt-controller@1000 {
84 compatible = "arm,cortex-a9-gic";
85 #interrupt-cells = <3>;
86 #address-cells = <0>;
87 interrupt-controller;
88 /* gic dist base, gic cpu base */
89 reg = <0x1000 0x1000>, <0x100 0x100>;
90 };
92 sysctrl: system-controller@802000 {
93 compatible = "hisilicon,sysctrl";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x802000 0x1000>;
97 reg = <0x802000 0x1000>;
99 smp-offset = <0x31c>;
100 resume-offset = <0x308>;
101 reboot-offset = <0x4>;
103 clock: clock@0 {
104 compatible = "hisilicon,hi3620-clock";
105 reg = <0 0x10000>;
106 #clock-cells = <1>;
107 };
108 };
110 dual_timer0: dual_timer@800000 {
111 compatible = "arm,sp804", "arm,primecell";
112 reg = <0x800000 0x1000>;
113 /* timer00 & timer01 */
114 interrupts = <0 0 4>, <0 1 4>;
115 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
116 clock-names = "apb_pclk";
117 status = "disabled";
118 };
120 dual_timer1: dual_timer@801000 {
121 compatible = "arm,sp804", "arm,primecell";
122 reg = <0x801000 0x1000>;
123 /* timer10 & timer11 */
124 interrupts = <0 2 4>, <0 3 4>;
125 clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
126 clock-names = "apb_pclk";
127 status = "disabled";
128 };
130 dual_timer2: dual_timer@a01000 {
131 compatible = "arm,sp804", "arm,primecell";
132 reg = <0xa01000 0x1000>;
133 /* timer20 & timer21 */
134 interrupts = <0 4 4>, <0 5 4>;
135 clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
136 clock-names = "apb_pclk";
137 status = "disabled";
138 };
140 dual_timer3: dual_timer@a02000 {
141 compatible = "arm,sp804", "arm,primecell";
142 reg = <0xa02000 0x1000>;
143 /* timer30 & timer31 */
144 interrupts = <0 6 4>, <0 7 4>;
145 clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
146 clock-names = "apb_pclk";
147 status = "disabled";
148 };
150 dual_timer4: dual_timer@a03000 {
151 compatible = "arm,sp804", "arm,primecell";
152 reg = <0xa03000 0x1000>;
153 /* timer40 & timer41 */
154 interrupts = <0 96 4>, <0 97 4>;
155 clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
156 clock-names = "apb_pclk";
157 status = "disabled";
158 };
160 timer5: timer@600 {
161 compatible = "arm,cortex-a9-twd-timer";
162 reg = <0x600 0x20>;
163 interrupts = <1 13 0xf01>;
164 };
166 uart0: uart@b00000 {
167 compatible = "arm,pl011", "arm,primecell";
168 reg = <0xb00000 0x1000>;
169 interrupts = <0 20 4>;
170 clocks = <&clock HI3620_UARTCLK0>;
171 clock-names = "apb_pclk";
172 status = "disabled";
173 };
175 uart1: uart@b01000 {
176 compatible = "arm,pl011", "arm,primecell";
177 reg = <0xb01000 0x1000>;
178 interrupts = <0 21 4>;
179 clocks = <&clock HI3620_UARTCLK1>;
180 clock-names = "apb_pclk";
181 status = "disabled";
182 };
184 uart2: uart@b02000 {
185 compatible = "arm,pl011", "arm,primecell";
186 reg = <0xb02000 0x1000>;
187 interrupts = <0 22 4>;
188 clocks = <&clock HI3620_UARTCLK2>;
189 clock-names = "apb_pclk";
190 status = "disabled";
191 };
193 uart3: uart@b03000 {
194 compatible = "arm,pl011", "arm,primecell";
195 reg = <0xb03000 0x1000>;
196 interrupts = <0 23 4>;
197 clocks = <&clock HI3620_UARTCLK3>;
198 clock-names = "apb_pclk";
199 status = "disabled";
200 };
202 uart4: uart@b04000 {
203 compatible = "arm,pl011", "arm,primecell";
204 reg = <0xb04000 0x1000>;
205 interrupts = <0 24 4>;
206 clocks = <&clock HI3620_UARTCLK4>;
207 clock-names = "apb_pclk";
208 status = "disabled";
209 };
211 gpio0: gpio@806000 {
212 compatible = "arm,pl061", "arm,primecell";
213 reg = <0x806000 0x1000>;
214 interrupts = <0 64 0x4>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
218 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 clocks = <&clock HI3620_GPIOCLK0>;
222 clock-names = "apb_pclk";
223 };
225 gpio1: gpio@807000 {
226 compatible = "arm,pl061", "arm,primecell";
227 reg = <0x807000 0x1000>;
228 interrupts = <0 65 0x4>;
229 gpio-controller;
230 #gpio-cells = <2>;
231 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
232 &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
233 &pmx0 6 5 1 &pmx0 7 6 1>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 clocks = <&clock HI3620_GPIOCLK1>;
237 clock-names = "apb_pclk";
238 };
240 gpio2: gpio@808000 {
241 compatible = "arm,pl061", "arm,primecell";
242 reg = <0x808000 0x1000>;
243 interrupts = <0 66 0x4>;
244 gpio-controller;
245 #gpio-cells = <2>;
246 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
247 &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
248 &pmx0 6 3 1 &pmx0 7 3 1>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 clocks = <&clock HI3620_GPIOCLK2>;
252 clock-names = "apb_pclk";
253 };
255 gpio3: gpio@809000 {
256 compatible = "arm,pl061", "arm,primecell";
257 reg = <0x809000 0x1000>;
258 interrupts = <0 67 0x4>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
262 &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
263 &pmx0 6 11 1 &pmx0 7 11 1>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 clocks = <&clock HI3620_GPIOCLK3>;
267 clock-names = "apb_pclk";
268 };
270 gpio4: gpio@80a000 {
271 compatible = "arm,pl061", "arm,primecell";
272 reg = <0x80a000 0x1000>;
273 interrupts = <0 68 0x4>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
277 &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
278 &pmx0 6 13 1 &pmx0 7 13 1>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 clocks = <&clock HI3620_GPIOCLK4>;
282 clock-names = "apb_pclk";
283 };
285 gpio5: gpio@80b000 {
286 compatible = "arm,pl061", "arm,primecell";
287 reg = <0x80b000 0x1000>;
288 interrupts = <0 69 0x4>;
289 gpio-controller;
290 #gpio-cells = <2>;
291 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
292 &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
293 &pmx0 6 16 1 &pmx0 7 16 1>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 clocks = <&clock HI3620_GPIOCLK5>;
297 clock-names = "apb_pclk";
298 };
300 gpio6: gpio@80c000 {
301 compatible = "arm,pl061", "arm,primecell";
302 reg = <0x80c000 0x1000>;
303 interrupts = <0 70 0x4>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
307 &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
308 &pmx0 6 18 1 &pmx0 7 19 1>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 clocks = <&clock HI3620_GPIOCLK6>;
312 clock-names = "apb_pclk";
313 };
315 gpio7: gpio@80d000 {
316 compatible = "arm,pl061", "arm,primecell";
317 reg = <0x80d000 0x1000>;
318 interrupts = <0 71 0x4>;
319 gpio-controller;
320 #gpio-cells = <2>;
321 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
322 &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
323 &pmx0 6 25 1 &pmx0 7 26 1>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 clocks = <&clock HI3620_GPIOCLK7>;
327 clock-names = "apb_pclk";
328 };
330 gpio8: gpio@80e000 {
331 compatible = "arm,pl061", "arm,primecell";
332 reg = <0x80e000 0x1000>;
333 interrupts = <0 72 0x4>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
337 &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
338 &pmx0 6 33 1 &pmx0 7 34 1>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 clocks = <&clock HI3620_GPIOCLK8>;
342 clock-names = "apb_pclk";
343 };
345 gpio9: gpio@80f000 {
346 compatible = "arm,pl061", "arm,primecell";
347 reg = <0x80f000 0x1000>;
348 interrupts = <0 73 0x4>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
352 &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
353 &pmx0 6 41 1>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 clocks = <&clock HI3620_GPIOCLK9>;
357 clock-names = "apb_pclk";
358 };
360 gpio10: gpio@810000 {
361 compatible = "arm,pl061", "arm,primecell";
362 reg = <0x810000 0x1000>;
363 interrupts = <0 74 0x4>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
367 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 clocks = <&clock HI3620_GPIOCLK10>;
371 clock-names = "apb_pclk";
372 };
374 gpio11: gpio@811000 {
375 compatible = "arm,pl061", "arm,primecell";
376 reg = <0x811000 0x1000>;
377 interrupts = <0 75 0x4>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
381 &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
382 &pmx0 6 49 1 &pmx0 7 49 1>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
385 clocks = <&clock HI3620_GPIOCLK11>;
386 clock-names = "apb_pclk";
387 };
389 gpio12: gpio@812000 {
390 compatible = "arm,pl061", "arm,primecell";
391 reg = <0x812000 0x1000>;
392 interrupts = <0 76 0x4>;
393 gpio-controller;
394 #gpio-cells = <2>;
395 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
396 &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
397 &pmx0 6 51 1 &pmx0 7 52 1>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 clocks = <&clock HI3620_GPIOCLK12>;
401 clock-names = "apb_pclk";
402 };
404 gpio13: gpio@813000 {
405 compatible = "arm,pl061", "arm,primecell";
406 reg = <0x813000 0x1000>;
407 interrupts = <0 77 0x4>;
408 gpio-controller;
409 #gpio-cells = <2>;
410 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
411 &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
412 &pmx0 6 55 1 &pmx0 7 56 1>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 clocks = <&clock HI3620_GPIOCLK13>;
416 clock-names = "apb_pclk";
417 };
419 gpio14: gpio@814000 {
420 compatible = "arm,pl061", "arm,primecell";
421 reg = <0x814000 0x1000>;
422 interrupts = <0 78 0x4>;
423 gpio-controller;
424 #gpio-cells = <2>;
425 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
426 &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
427 &pmx0 6 60 1 &pmx0 7 61 1>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 clocks = <&clock HI3620_GPIOCLK14>;
431 clock-names = "apb_pclk";
432 };
434 gpio15: gpio@815000 {
435 compatible = "arm,pl061", "arm,primecell";
436 reg = <0x815000 0x1000>;
437 interrupts = <0 79 0x4>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
441 &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
442 &pmx0 6 64 1 &pmx0 7 65 1>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 clocks = <&clock HI3620_GPIOCLK15>;
446 clock-names = "apb_pclk";
447 };
449 gpio16: gpio@816000 {
450 compatible = "arm,pl061", "arm,primecell";
451 reg = <0x816000 0x1000>;
452 interrupts = <0 80 0x4>;
453 gpio-controller;
454 #gpio-cells = <2>;
455 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
456 &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
457 &pmx0 6 72 1 &pmx0 7 73 1>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 clocks = <&clock HI3620_GPIOCLK16>;
461 clock-names = "apb_pclk";
462 };
464 gpio17: gpio@817000 {
465 compatible = "arm,pl061", "arm,primecell";
466 reg = <0x817000 0x1000>;
467 interrupts = <0 81 0x4>;
468 gpio-controller;
469 #gpio-cells = <2>;
470 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
471 &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
472 &pmx0 6 80 1 &pmx0 7 81 1>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
475 clocks = <&clock HI3620_GPIOCLK17>;
476 clock-names = "apb_pclk";
477 };
479 gpio18: gpio@818000 {
480 compatible = "arm,pl061", "arm,primecell";
481 reg = <0x818000 0x1000>;
482 interrupts = <0 82 0x4>;
483 gpio-controller;
484 #gpio-cells = <2>;
485 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
486 &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
487 &pmx0 6 86 1 &pmx0 7 87 1>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 clocks = <&clock HI3620_GPIOCLK18>;
491 clock-names = "apb_pclk";
492 };
494 gpio19: gpio@819000 {
495 compatible = "arm,pl061", "arm,primecell";
496 reg = <0x819000 0x1000>;
497 interrupts = <0 83 0x4>;
498 gpio-controller;
499 #gpio-cells = <2>;
500 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
501 &pmx0 3 88 1>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
504 clocks = <&clock HI3620_GPIOCLK19>;
505 clock-names = "apb_pclk";
506 };
508 gpio20: gpio@81a000 {
509 compatible = "arm,pl061", "arm,primecell";
510 reg = <0x81a000 0x1000>;
511 interrupts = <0 84 0x4>;
512 gpio-controller;
513 #gpio-cells = <2>;
514 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
515 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 clocks = <&clock HI3620_GPIOCLK20>;
519 clock-names = "apb_pclk";
520 };
522 gpio21: gpio@81b000 {
523 compatible = "arm,pl061", "arm,primecell";
524 reg = <0x81b000 0x1000>;
525 interrupts = <0 85 0x4>;
526 gpio-controller;
527 #gpio-cells = <2>;
528 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
531 clocks = <&clock HI3620_GPIOCLK21>;
532 clock-names = "apb_pclk";
533 };
535 pmx0: pinmux@803000 {
536 compatible = "pinctrl-single";
537 reg = <0x803000 0x188>;
538 #address-cells = <1>;
539 #size-cells = <1>;
540 #gpio-range-cells = <3>;
541 ranges;
543 pinctrl-single,register-width = <32>;
544 pinctrl-single,function-mask = <7>;
545 /* pin base, nr pins & gpio function */
546 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
547 &range 12 1 0 &range 13 29 1
548 &range 43 1 0 &range 44 49 1
549 &range 94 1 1 &range 96 2 1>;
551 range: gpio-range {
552 #pinctrl-single,gpio-range-cells = <3>;
553 };
554 };
556 pmx1: pinmux@803800 {
557 compatible = "pinconf-single";
558 reg = <0x803800 0x2dc>;
559 #address-cells = <1>;
560 #size-cells = <1>;
561 ranges;
563 pinctrl-single,register-width = <32>;
564 };
565 };
566 };