arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         memory {
  17                 reg = <0x10000000 0x80000000>;
  18         };
  19
  20         leds {
  21                 compatible = "gpio-leds";
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&pinctrl_gpio_leds>;
  24
  25                 user {
  26                         label = "debug";
  27                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  28                 };
  29         };
  30
  31         clocks {
  32                 codec_osc: anaclk2 {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <24576000>;
  36                 };
  37         };
  38
  39         regulators {
  40                 compatible = "simple-bus";
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 reg_audio: regulator@0 {
  45                         compatible = "regulator-fixed";
  46                         reg = <0>;
  47                         regulator-name = "cs42888_supply";
  48                         regulator-min-microvolt = <3300000>;
  49                         regulator-max-microvolt = <3300000>;
  50                         regulator-always-on;
  51                 };
  52
  53                 reg_usb_h1_vbus: regulator@1 {
  54                         compatible = "regulator-fixed";
  55                         reg = <1>;
  56                         regulator-name = "usb_h1_vbus";
  57                         regulator-min-microvolt = <5000000>;
  58                         regulator-max-microvolt = <5000000>;
  59                         gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
  60                         enable-active-high;
  61                 };
  62
  63                 reg_usb_otg_vbus: regulator@2 {
  64                         compatible = "regulator-fixed";
  65                         reg = <2>;
  66                         regulator-name = "usb_otg_vbus";
  67                         regulator-min-microvolt = <5000000>;
  68                         regulator-max-microvolt = <5000000>;
  69                         gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
  70                         enable-active-high;
  71                 };
  72         };
  73
  74         sound-cs42888 {
  75                 compatible = "fsl,imx6-sabreauto-cs42888",
  76                         "fsl,imx-audio-cs42888";
  77                 model = "imx-cs42888";
  78                 audio-cpu = <&esai>;
  79                 audio-asrc = <&asrc>;
  80                 audio-codec = <&codec>;
  81                 audio-routing =
  82                         "Line Out Jack", "AOUT1L",
  83                         "Line Out Jack", "AOUT1R",
  84                         "Line Out Jack", "AOUT2L",
  85                         "Line Out Jack", "AOUT2R",
  86                         "Line Out Jack", "AOUT3L",
  87                         "Line Out Jack", "AOUT3R",
  88                         "Line Out Jack", "AOUT4L",
  89                         "Line Out Jack", "AOUT4R",
  90                         "AIN1L", "Line In Jack",
  91                         "AIN1R", "Line In Jack",
  92                         "AIN2L", "Line In Jack",
  93                         "AIN2R", "Line In Jack";
  94         };
  95
  96         sound-spdif {
  97                 compatible = "fsl,imx-audio-spdif",
  98                            "fsl,imx-sabreauto-spdif";
  99                 model = "imx-spdif";
 100                 spdif-controller = <&spdif>;
 101                 spdif-in;
 102         };
 103
 104         backlight {
 105                 compatible = "pwm-backlight";
 106                 pwms = <&pwm3 0 5000000>;
 107                 brightness-levels = <0 4 8 16 32 64 128 255>;
 108                 default-brightness-level = <7>;
 109                 status = "okay";
 110         };
 111 };
 112
 113 &clks {
 114         assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 115                           <&clks IMX6QDL_PLL4_BYPASS>,
 116                           <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 117                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 118                           <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
 119         assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
 120                                  <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 121                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 122                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 123         assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
 124 };
 125
 126 &ecspi1 {
 127         fsl,spi-num-chipselects = <1>;
 128         cs-gpios = <&gpio3 19 0>;
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
 131         status = "disabled"; /* pin conflict with WEIM NOR */
 132
 133         flash: m25p80@0 {
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 compatible = "st,m25p32", "jedec,spi-nor";
 137                 spi-max-frequency = <20000000>;
 138                 reg = <0>;
 139         };
 140 };
 141
 142 &esai {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_esai>;
 145         assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
 146                           <&clks IMX6QDL_CLK_ESAI_EXTAL>;
 147         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
 148         assigned-clock-rates = <0>, <24576000>;
 149         status = "okay";
 150 };
 151
 152 &fec {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_enet>;
 155         phy-mode = "rgmii";
 156         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 157                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 158         status = "okay";
 159 };
 160
 161 &gpmi {
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_gpmi_nand>;
 164         status = "okay";
 165 };
 166
 167 &hdmi {
 168         status = "okay";
 169 };
 170
 171 &i2c2 {
 172         clock-frequency = <100000>;
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_i2c2>;
 175         status = "okay";
 176
 177         pmic: pfuze100@08 {
 178                 compatible = "fsl,pfuze100";
 179                 reg = <0x08>;
 180
 181                 regulators {
 182                         sw1a_reg: sw1ab {
 183                                 regulator-min-microvolt = <300000>;
 184                                 regulator-max-microvolt = <1875000>;
 185                                 regulator-boot-on;
 186                                 regulator-always-on;
 187                                 regulator-ramp-delay = <6250>;
 188                         };
 189
 190                         sw1c_reg: sw1c {
 191                                 regulator-min-microvolt = <300000>;
 192                                 regulator-max-microvolt = <1875000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                                 regulator-ramp-delay = <6250>;
 196                         };
 197
 198                         sw2_reg: sw2 {
 199                                 regulator-min-microvolt = <800000>;
 200                                 regulator-max-microvolt = <3300000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         sw3a_reg: sw3a {
 206                                 regulator-min-microvolt = <400000>;
 207                                 regulator-max-microvolt = <1975000>;
 208                                 regulator-boot-on;
 209                                 regulator-always-on;
 210                         };
 211
 212                         sw3b_reg: sw3b {
 213                                 regulator-min-microvolt = <400000>;
 214                                 regulator-max-microvolt = <1975000>;
 215                                 regulator-boot-on;
 216                                 regulator-always-on;
 217                         };
 218
 219                         sw4_reg: sw4 {
 220                                 regulator-min-microvolt = <800000>;
 221                                 regulator-max-microvolt = <3300000>;
 222                         };
 223
 224                         swbst_reg: swbst {
 225                                 regulator-min-microvolt = <5000000>;
 226                                 regulator-max-microvolt = <5150000>;
 227                         };
 228
 229                         snvs_reg: vsnvs {
 230                                 regulator-min-microvolt = <1000000>;
 231                                 regulator-max-microvolt = <3000000>;
 232                                 regulator-boot-on;
 233                                 regulator-always-on;
 234                         };
 235
 236                         vref_reg: vrefddr {
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                         };
 240
 241                         vgen1_reg: vgen1 {
 242                                 regulator-min-microvolt = <800000>;
 243                                 regulator-max-microvolt = <1550000>;
 244                         };
 245
 246                         vgen2_reg: vgen2 {
 247                                 regulator-min-microvolt = <800000>;
 248                                 regulator-max-microvolt = <1550000>;
 249                         };
 250
 251                         vgen3_reg: vgen3 {
 252                                 regulator-min-microvolt = <1800000>;
 253                                 regulator-max-microvolt = <3300000>;
 254                         };
 255
 256                         vgen4_reg: vgen4 {
 257                                 regulator-min-microvolt = <1800000>;
 258                                 regulator-max-microvolt = <3300000>;
 259                                 regulator-always-on;
 260                         };
 261
 262                         vgen5_reg: vgen5 {
 263                                 regulator-min-microvolt = <1800000>;
 264                                 regulator-max-microvolt = <3300000>;
 265                                 regulator-always-on;
 266                         };
 267
 268                         vgen6_reg: vgen6 {
 269                                 regulator-min-microvolt = <1800000>;
 270                                 regulator-max-microvolt = <3300000>;
 271                                 regulator-always-on;
 272                         };
 273                 };
 274         };
 275
 276         codec: cs42888@48 {
 277                 compatible = "cirrus,cs42888";
 278                 reg = <0x48>;
 279                 clocks = <&codec_osc>;
 280                 clock-names = "mclk";
 281                 VA-supply = <&reg_audio>;
 282                 VD-supply = <&reg_audio>;
 283                 VLS-supply = <&reg_audio>;
 284                 VLC-supply = <&reg_audio>;
 285         };
 286
 287 };
 288
 289 &i2c3 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_i2c3>;
 292         status = "okay";
 293
 294         max7310_a: gpio@30 {
 295                 compatible = "maxim,max7310";
 296                 reg = <0x30>;
 297                 gpio-controller;
 298                 #gpio-cells = <2>;
 299         };
 300
 301         max7310_b: gpio@32 {
 302                 compatible = "maxim,max7310";
 303                 reg = <0x32>;
 304                 gpio-controller;
 305                 #gpio-cells = <2>;
 306         };
 307
 308         max7310_c: gpio@34 {
 309                 compatible = "maxim,max7310";
 310                 reg = <0x34>;
 311                 gpio-controller;
 312                 #gpio-cells = <2>;
 313         };
 314 };
 315
 316 &iomuxc {
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_hog>;
 319
 320         imx6qdl-sabreauto {
 321                 pinctrl_hog: hoggrp {
 322                         fsl,pins = <
 323                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 324                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 325                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 326                         >;
 327                 };
 328
 329                 pinctrl_ecspi1: ecspi1grp {
 330                         fsl,pins = <
 331                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 332                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 333                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 334                         >;
 335                 };
 336
 337                 pinctrl_ecspi1_cs: ecspi1cs {
 338                         fsl,pins = <
 339                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 340                         >;
 341                 };
 342
 343                 pinctrl_enet: enetgrp {
 344                         fsl,pins = <
 345                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 346                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 347                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 348                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 349                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 350                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 351                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 352                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 353                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 354                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 355                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 356                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 357                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 358                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 359                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 360                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 361                         >;
 362                 };
 363
 364                 pinctrl_esai: esaigrp {
 365                         fsl,pins = <
 366                                 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
 367                                 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
 368                                 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
 369                                 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
 370                                 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
 371                                 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
 372                                 MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
 373                                 MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
 374                                 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
 375                                 MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
 376                         >;
 377                 };
 378
 379                 pinctrl_gpio_leds: gpioledsgrp {
 380                         fsl,pins = <
 381                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 382                         >;
 383                 };
 384
 385                 pinctrl_gpmi_nand: gpminandgrp {
 386                         fsl,pins = <
 387                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 388                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 389                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 390                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 391                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 392                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 393                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 394                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 395                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 396                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 397                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 398                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 399                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 400                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 401                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 402                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 403                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 404                         >;
 405                 };
 406
 407                 pinctrl_i2c2: i2c2grp {
 408                         fsl,pins = <
 409                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 410                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 411                         >;
 412                 };
 413
 414                 pinctrl_i2c3: i2c3grp {
 415                         fsl,pins = <
 416                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 417                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 418                         >;
 419                 };
 420
 421                 pinctrl_pwm3: pwm1grp {
 422                         fsl,pins = <
 423                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 424                         >;
 425                 };
 426
 427                 pinctrl_spdif: spdifgrp {
 428                         fsl,pins = <
 429                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 430                         >;
 431                 };
 432
 433                 pinctrl_uart4: uart4grp {
 434                         fsl,pins = <
 435                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 436                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 437                         >;
 438                 };
 439
 440                 pinctrl_usbotg: usbotggrp {
 441                         fsl,pins = <
 442                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 443                         >;
 444                 };
 445
 446                 pinctrl_usdhc3: usdhc3grp {
 447                         fsl,pins = <
 448                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 449                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 450                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 451                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 452                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 453                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 454                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 455                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 456                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 457                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 458                         >;
 459                 };
 460
 461                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 462                         fsl,pins = <
 463                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 464                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 465                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 466                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 467                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 468                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 469                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 470                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 471                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 472                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 473                         >;
 474                 };
 475
 476                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 477                         fsl,pins = <
 478                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 479                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 480                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 481                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 482                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 483                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 484                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 485                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 486                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 487                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 488                         >;
 489                 };
 490
 491                 pinctrl_weim_cs0: weimcs0grp {
 492                         fsl,pins = <
 493                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 494                         >;
 495                 };
 496
 497                 pinctrl_weim_nor: weimnorgrp {
 498                         fsl,pins = <
 499                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 500                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 501                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 502                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 503                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 504                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 505                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 506                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 507                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 508                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 509                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 510                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 511                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 512                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 513                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 514                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 515                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 516                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 517                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 518                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 519                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 520                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 521                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 522                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 523                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 524                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 525                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 526                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 527                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 528                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 529                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 530                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 531                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 532                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 533                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 534                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 535                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 536                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 537                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 538                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 539                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 540                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 541                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 542                         >;
 543                 };
 544         };
 545 };
 546
 547 &ldb {
 548         status = "okay";
 549
 550         lvds-channel@0 {
 551                 fsl,data-mapping = "spwg";
 552                 fsl,data-width = <18>;
 553                 status = "okay";
 554
 555                 display-timings {
 556                         native-mode = <&timing0>;
 557                         timing0: hsd100pxn1 {
 558                                 clock-frequency = <65000000>;
 559                                 hactive = <1024>;
 560                                 vactive = <768>;
 561                                 hback-porch = <220>;
 562                                 hfront-porch = <40>;
 563                                 vback-porch = <21>;
 564                                 vfront-porch = <7>;
 565                                 hsync-len = <60>;
 566                                 vsync-len = <10>;
 567                         };
 568                 };
 569         };
 570 };
 571
 572 &pwm3 {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&pinctrl_pwm3>;
 575         status = "okay";
 576 };
 577
 578 &spdif {
 579         pinctrl-names = "default";
 580         pinctrl-0 = <&pinctrl_spdif>;
 581         status = "okay";
 582 };
 583
 584 &uart4 {
 585         pinctrl-names = "default";
 586         pinctrl-0 = <&pinctrl_uart4>;
 587         status = "okay";
 588 };
 589
 590 &usbh1 {
 591         vbus-supply = <&reg_usb_h1_vbus>;
 592         status = "okay";
 593 };
 594
 595 &usbotg {
 596         vbus-supply = <&reg_usb_otg_vbus>;
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&pinctrl_usbotg>;
 599         status = "okay";
 600 };
 601
 602 &usdhc3 {
 603         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 604         pinctrl-0 = <&pinctrl_usdhc3>;
 605         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 606         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 607         cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 608         wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 609         status = "okay";
 610 };
 611
 612 &weim {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 615         #address-cells = <2>;
 616         #size-cells = <1>;
 617         ranges = <0 0 0x08000000 0x08000000>;
 618         status = "disabled"; /* pin conflict with SPI NOR */
 619
 620         nor@0,0 {
 621                 compatible = "cfi-flash";
 622                 reg = <0 0 0x02000000>;
 623                 #address-cells = <1>;
 624                 #size-cells = <1>;
 625                 bank-width = <2>;
 626                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 627                                 0x0000c000 0x1404a38e 0x00000000>;
 628         };
 629 };