2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include "skeleton.dtsi"
11 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
14 model = "Marvell Orion5x SoC";
15 compatible = "marvell,orion5x";
16 interrupt-parent = <&intc>;
25 controller = <&mbusc>;
27 devbus_bootcs: devbus-bootcs {
28 compatible = "marvell,orion-devbus";
29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
33 clocks = <&core_clk 0>;
37 devbus_cs0: devbus-cs0 {
38 compatible = "marvell,orion-devbus";
39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
43 clocks = <&core_clk 0>;
47 devbus_cs1: devbus-cs1 {
48 compatible = "marvell,orion-devbus";
49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
53 clocks = <&core_clk 0>;
57 devbus_cs2: devbus-cs2 {
58 compatible = "marvell,orion-devbus";
59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
60 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
63 clocks = <&core_clk 0>;
68 compatible = "simple-bus";
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
74 compatible = "marvell,orion-gpio";
80 #interrupt-cells = <2>;
81 interrupts = <6>, <7>, <8>, <9>;
85 compatible = "marvell,orion-spi";
94 compatible = "marvell,mv64xxx-i2c";
99 clocks = <&core_clk 0>;
103 uart0: serial@12000 {
104 compatible = "ns16550a";
105 reg = <0x12000 0x100>;
108 clocks = <&core_clk 0>;
112 uart1: serial@12100 {
113 compatible = "ns16550a";
114 reg = <0x12100 0x100>;
117 clocks = <&core_clk 0>;
121 bridge_intc: bridge-interrupt-ctrl@20110 {
122 compatible = "marvell,orion-bridge-intc";
123 interrupt-controller;
124 #interrupt-cells = <1>;
127 marvell,#interrupts = <4>;
130 intc: interrupt-controller@20200 {
131 compatible = "marvell,orion-intc";
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 reg = <0x20200 0x08>;
138 compatible = "marvell,orion-timer";
139 reg = <0x20300 0x20>;
140 interrupt-parent = <&bridge_intc>;
141 interrupts = <1>, <2>;
142 clocks = <&core_clk 0>;
146 compatible = "marvell,orion-wdt";
147 reg = <0x20300 0x28>;
148 interrupt-parent = <&bridge_intc>;
154 compatible = "marvell,orion-ehci";
155 reg = <0x50000 0x1000>;
160 xor: dma-controller@60900 {
161 compatible = "marvell,orion-xor";
179 eth: ethernet-controller@72000 {
180 compatible = "marvell,orion-eth";
181 #address-cells = <1>;
183 reg = <0x72000 0x4000>;
184 marvell,tx-checksum-limit = <1600>;
187 ethport: ethernet-port@0 {
188 compatible = "marvell,orion-eth-port";
191 /* overwrite MAC address in bootloader */
192 local-mac-address = [00 00 00 00 00 00];
193 /* set phy-handle property in board file */
197 mdio: mdio-bus@72004 {
198 compatible = "marvell,orion-mdio";
199 #address-cells = <1>;
201 reg = <0x72004 0x84>;
205 /* add phy nodes in board file */
209 compatible = "marvell,orion-sata";
210 reg = <0x80000 0x5000>;
216 compatible = "marvell,orion-crypto";
217 reg = <0x90000 0x10000>;
220 marvell,crypto-srams = <&crypto_sram>;
221 marvell,crypto-sram-size = <0x800>;
226 compatible = "marvell,orion-ehci";
227 reg = <0xa0000 0x1000>;
233 crypto_sram: sa-sram {
234 compatible = "mmio-sram";
235 reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;
236 #address-cells = <1>;