| blob | df96ccdc9bb4728c5561fa79e5274ecc2e991691 |
1 /dts-v1/;
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 / {
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
14 reserved-memory {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
19 smem_region: smem@80000000 {
20 reg = <0x80000000 0x200000>;
21 no-map;
22 };
23 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu@0 {
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
32 device_type = "cpu";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc0>;
36 qcom,saw = <&saw0>;
37 cpu-idle-states = <&CPU_SPC>;
38 };
40 cpu@1 {
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc1>;
47 qcom,saw = <&saw1>;
48 cpu-idle-states = <&CPU_SPC>;
49 };
51 cpu@2 {
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
54 device_type = "cpu";
55 reg = <2>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc2>;
58 qcom,saw = <&saw2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
62 cpu@3 {
63 compatible = "qcom,krait";
64 enable-method = "qcom,kpss-acc-v1";
65 device_type = "cpu";
66 reg = <3>;
67 next-level-cache = <&L2>;
68 qcom,acc = <&acc3>;
69 qcom,saw = <&saw3>;
70 cpu-idle-states = <&CPU_SPC>;
71 };
73 L2: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 };
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 entry-latency-us = <400>;
83 exit-latency-us = <900>;
84 min-residency-us = <3000>;
85 };
86 };
87 };
89 cpu-pmu {
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 10 0x304>;
92 };
94 clocks {
95 cxo_board {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <19200000>;
99 };
101 pxo_board {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <27000000>;
105 };
107 sleep_clk {
108 compatible = "fixed-clock";
109 #clock-cells = <0>;
110 clock-frequency = <32768>;
111 };
112 };
114 sfpb_mutex: hwmutex {
115 compatible = "qcom,sfpb-mutex";
116 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
117 #hwlock-cells = <1>;
118 };
120 smem {
121 compatible = "qcom,smem";
122 memory-region = <&smem_region>;
124 hwlocks = <&sfpb_mutex 3>;
125 };
127 smd {
128 compatible = "qcom,smd";
130 modem@0 {
131 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
133 qcom,ipc = <&l2cc 8 3>;
134 qcom,smd-edge = <0>;
136 status = "disabled";
137 };
139 q6@1 {
140 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
142 qcom,ipc = <&l2cc 8 15>;
143 qcom,smd-edge = <1>;
145 status = "disabled";
146 };
148 dsps@3 {
149 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
151 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
152 qcom,smd-edge = <3>;
154 status = "disabled";
155 };
157 riva@6 {
158 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
160 qcom,ipc = <&l2cc 8 25>;
161 qcom,smd-edge = <6>;
163 status = "disabled";
164 };
165 };
167 smsm {
168 compatible = "qcom,smsm";
170 #address-cells = <1>;
171 #size-cells = <0>;
173 qcom,ipc-1 = <&l2cc 8 4>;
174 qcom,ipc-2 = <&l2cc 8 14>;
175 qcom,ipc-3 = <&l2cc 8 23>;
176 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
178 apps_smsm: apps@0 {
179 reg = <0>;
180 #qcom,state-cells = <1>;
181 };
183 modem_smsm: modem@1 {
184 reg = <1>;
185 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
189 };
191 q6_smsm: q6@2 {
192 reg = <2>;
193 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
199 wcnss_smsm: wcnss@3 {
200 reg = <3>;
201 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
207 dsps_smsm: dsps@4 {
208 reg = <4>;
209 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 };
214 };
216 soc: soc {
217 #address-cells = <1>;
218 #size-cells = <1>;
219 ranges;
220 compatible = "simple-bus";
222 tlmm_pinmux: pinctrl@800000 {
223 compatible = "qcom,apq8064-pinctrl";
224 reg = <0x800000 0x4000>;
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&ps_hold>;
234 };
236 sfpb_wrapper_mutex: syscon@1200000 {
237 compatible = "syscon";
238 reg = <0x01200000 0x8000>;
239 };
241 intc: interrupt-controller@2000000 {
242 compatible = "qcom,msm-qgic2";
243 interrupt-controller;
244 #interrupt-cells = <3>;
245 reg = <0x02000000 0x1000>,
246 <0x02002000 0x1000>;
247 };
249 timer@200a000 {
250 compatible = "qcom,kpss-timer", "qcom,msm-timer";
251 interrupts = <1 1 0x301>,
252 <1 2 0x301>,
253 <1 3 0x301>;
254 reg = <0x0200a000 0x100>;
255 clock-frequency = <27000000>,
256 <32768>;
257 cpu-offset = <0x80000>;
258 };
260 acc0: clock-controller@2088000 {
261 compatible = "qcom,kpss-acc-v1";
262 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
263 };
265 acc1: clock-controller@2098000 {
266 compatible = "qcom,kpss-acc-v1";
267 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
268 };
270 acc2: clock-controller@20a8000 {
271 compatible = "qcom,kpss-acc-v1";
272 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
273 };
275 acc3: clock-controller@20b8000 {
276 compatible = "qcom,kpss-acc-v1";
277 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
278 };
280 saw0: power-controller@2089000 {
281 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
282 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
283 regulator;
284 };
286 saw1: power-controller@2099000 {
287 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
288 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
289 regulator;
290 };
292 saw2: power-controller@20a9000 {
293 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
294 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
295 regulator;
296 };
298 saw3: power-controller@20b9000 {
299 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
300 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
301 regulator;
302 };
304 sps_sic_non_secure: sps-sic-non-secure@12100000 {
305 compatible = "syscon";
306 reg = <0x12100000 0x10000>;
307 };
309 gsbi1: gsbi@12440000 {
310 status = "disabled";
311 compatible = "qcom,gsbi-v1.0.0";
312 cell-index = <1>;
313 reg = <0x12440000 0x100>;
314 clocks = <&gcc GSBI1_H_CLK>;
315 clock-names = "iface";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges;
320 syscon-tcsr = <&tcsr>;
322 gsbi1_serial: serial@12450000 {
323 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
324 reg = <0x12450000 0x100>,
325 <0x12400000 0x03>;
326 interrupts = <0 193 0x0>;
327 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
328 clock-names = "core", "iface";
329 status = "disabled";
330 };
332 gsbi1_i2c: i2c@12460000 {
333 compatible = "qcom,i2c-qup-v1.1.1";
334 pinctrl-0 = <&i2c1_pins>;
335 pinctrl-1 = <&i2c1_pins_sleep>;
336 pinctrl-names = "default", "sleep";
337 reg = <0x12460000 0x1000>;
338 interrupts = <0 194 IRQ_TYPE_NONE>;
339 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
340 clock-names = "core", "iface";
341 #address-cells = <1>;
342 #size-cells = <0>;
343 };
345 };
347 gsbi2: gsbi@12480000 {
348 status = "disabled";
349 compatible = "qcom,gsbi-v1.0.0";
350 cell-index = <2>;
351 reg = <0x12480000 0x100>;
352 clocks = <&gcc GSBI2_H_CLK>;
353 clock-names = "iface";
354 #address-cells = <1>;
355 #size-cells = <1>;
356 ranges;
358 syscon-tcsr = <&tcsr>;
360 gsbi2_i2c: i2c@124a0000 {
361 compatible = "qcom,i2c-qup-v1.1.1";
362 reg = <0x124a0000 0x1000>;
363 pinctrl-0 = <&i2c2_pins>;
364 pinctrl-1 = <&i2c2_pins_sleep>;
365 pinctrl-names = "default", "sleep";
366 interrupts = <0 196 IRQ_TYPE_NONE>;
367 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
368 clock-names = "core", "iface";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 };
372 };
374 gsbi3: gsbi@16200000 {
375 status = "disabled";
376 compatible = "qcom,gsbi-v1.0.0";
377 cell-index = <3>;
378 reg = <0x16200000 0x100>;
379 clocks = <&gcc GSBI3_H_CLK>;
380 clock-names = "iface";
381 #address-cells = <1>;
382 #size-cells = <1>;
383 ranges;
384 gsbi3_i2c: i2c@16280000 {
385 compatible = "qcom,i2c-qup-v1.1.1";
386 pinctrl-0 = <&i2c3_pins>;
387 pinctrl-1 = <&i2c3_pins_sleep>;
388 pinctrl-names = "default", "sleep";
389 reg = <0x16280000 0x1000>;
390 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
391 clocks = <&gcc GSBI3_QUP_CLK>,
392 <&gcc GSBI3_H_CLK>;
393 clock-names = "core", "iface";
394 #address-cells = <1>;
395 #size-cells = <0>;
396 };
397 };
399 gsbi4: gsbi@16300000 {
400 status = "disabled";
401 compatible = "qcom,gsbi-v1.0.0";
402 cell-index = <4>;
403 reg = <0x16300000 0x03>;
404 clocks = <&gcc GSBI4_H_CLK>;
405 clock-names = "iface";
406 #address-cells = <1>;
407 #size-cells = <1>;
408 ranges;
410 gsbi4_i2c: i2c@16380000 {
411 compatible = "qcom,i2c-qup-v1.1.1";
412 pinctrl-0 = <&i2c4_pins>;
413 pinctrl-1 = <&i2c4_pins_sleep>;
414 pinctrl-names = "default", "sleep";
415 reg = <0x16380000 0x1000>;
416 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
417 clocks = <&gcc GSBI4_QUP_CLK>,
418 <&gcc GSBI4_H_CLK>;
419 clock-names = "core", "iface";
420 };
421 };
423 gsbi5: gsbi@1a200000 {
424 status = "disabled";
425 compatible = "qcom,gsbi-v1.0.0";
426 cell-index = <5>;
427 reg = <0x1a200000 0x03>;
428 clocks = <&gcc GSBI5_H_CLK>;
429 clock-names = "iface";
430 #address-cells = <1>;
431 #size-cells = <1>;
432 ranges;
434 gsbi5_serial: serial@1a240000 {
435 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
436 reg = <0x1a240000 0x100>,
437 <0x1a200000 0x03>;
438 interrupts = <0 154 0x0>;
439 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
440 clock-names = "core", "iface";
441 status = "disabled";
442 };
444 gsbi5_spi: spi@1a280000 {
445 compatible = "qcom,spi-qup-v1.1.1";
446 reg = <0x1a280000 0x1000>;
447 interrupts = <0 155 0>;
448 pinctrl-0 = <&spi5_default>;
449 pinctrl-1 = <&spi5_sleep>;
450 pinctrl-names = "default", "sleep";
451 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
452 clock-names = "core", "iface";
453 status = "disabled";
454 #address-cells = <1>;
455 #size-cells = <0>;
456 };
457 };
459 gsbi6: gsbi@16500000 {
460 status = "disabled";
461 compatible = "qcom,gsbi-v1.0.0";
462 cell-index = <6>;
463 reg = <0x16500000 0x03>;
464 clocks = <&gcc GSBI6_H_CLK>;
465 clock-names = "iface";
466 #address-cells = <1>;
467 #size-cells = <1>;
468 ranges;
470 gsbi6_serial: serial@16540000 {
471 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
472 reg = <0x16540000 0x100>,
473 <0x16500000 0x03>;
474 interrupts = <0 156 0x0>;
475 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
476 clock-names = "core", "iface";
477 status = "disabled";
478 };
480 gsbi6_i2c: i2c@16580000 {
481 compatible = "qcom,i2c-qup-v1.1.1";
482 pinctrl-0 = <&i2c6_pins>;
483 pinctrl-1 = <&i2c6_pins_sleep>;
484 pinctrl-names = "default", "sleep";
485 reg = <0x16580000 0x1000>;
486 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
487 clocks = <&gcc GSBI6_QUP_CLK>,
488 <&gcc GSBI6_H_CLK>;
489 clock-names = "core", "iface";
490 };
491 };
493 gsbi7: gsbi@16600000 {
494 status = "disabled";
495 compatible = "qcom,gsbi-v1.0.0";
496 cell-index = <7>;
497 reg = <0x16600000 0x100>;
498 clocks = <&gcc GSBI7_H_CLK>;
499 clock-names = "iface";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges;
503 syscon-tcsr = <&tcsr>;
505 gsbi7_serial: serial@16640000 {
506 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
507 reg = <0x16640000 0x1000>,
508 <0x16600000 0x1000>;
509 interrupts = <0 158 0x0>;
510 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
511 clock-names = "core", "iface";
512 status = "disabled";
513 };
515 gsbi7_i2c: i2c@16680000 {
516 compatible = "qcom,i2c-qup-v1.1.1";
517 pinctrl-0 = <&i2c7_pins>;
518 pinctrl-1 = <&i2c7_pins_sleep>;
519 pinctrl-names = "default", "sleep";
520 reg = <0x16680000 0x1000>;
521 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
522 clocks = <&gcc GSBI7_QUP_CLK>,
523 <&gcc GSBI7_H_CLK>;
524 clock-names = "core", "iface";
525 status = "disabled";
526 };
527 };
529 rng@1a500000 {
530 compatible = "qcom,prng";
531 reg = <0x1a500000 0x200>;
532 clocks = <&gcc PRNG_CLK>;
533 clock-names = "core";
534 };
536 qcom,ssbi@500000 {
537 compatible = "qcom,ssbi";
538 reg = <0x00500000 0x1000>;
539 qcom,controller-type = "pmic-arbiter";
541 pmicintc: pmic@0 {
542 compatible = "qcom,pm8921";
543 interrupt-parent = <&tlmm_pinmux>;
544 interrupts = <74 8>;
545 #interrupt-cells = <2>;
546 interrupt-controller;
547 #address-cells = <1>;
548 #size-cells = <0>;
550 pm8921_gpio: gpio@150 {
552 compatible = "qcom,pm8921-gpio",
553 "qcom,ssbi-gpio";
554 reg = <0x150>;
555 interrupts = <192 1>, <193 1>, <194 1>,
556 <195 1>, <196 1>, <197 1>,
557 <198 1>, <199 1>, <200 1>,
558 <201 1>, <202 1>, <203 1>,
559 <204 1>, <205 1>, <206 1>,
560 <207 1>, <208 1>, <209 1>,
561 <210 1>, <211 1>, <212 1>,
562 <213 1>, <214 1>, <215 1>,
563 <216 1>, <217 1>, <218 1>,
564 <219 1>, <220 1>, <221 1>,
565 <222 1>, <223 1>, <224 1>,
566 <225 1>, <226 1>, <227 1>,
567 <228 1>, <229 1>, <230 1>,
568 <231 1>, <232 1>, <233 1>,
569 <234 1>, <235 1>;
571 gpio-controller;
572 #gpio-cells = <2>;
574 };
576 pm8921_mpps: mpps@50 {
577 compatible = "qcom,pm8921-mpp",
578 "qcom,ssbi-mpp";
579 reg = <0x50>;
580 gpio-controller;
581 #gpio-cells = <2>;
582 interrupts =
583 <128 1>, <129 1>, <130 1>, <131 1>,
584 <132 1>, <133 1>, <134 1>, <135 1>,
585 <136 1>, <137 1>, <138 1>, <139 1>;
586 };
588 rtc@11d {
589 compatible = "qcom,pm8921-rtc";
590 interrupt-parent = <&pmicintc>;
591 interrupts = <39 1>;
592 reg = <0x11d>;
593 allow-set-time;
594 };
596 pwrkey@1c {
597 compatible = "qcom,pm8921-pwrkey";
598 reg = <0x1c>;
599 interrupt-parent = <&pmicintc>;
600 interrupts = <50 1>, <51 1>;
601 debounce = <15625>;
602 pull-up;
603 };
604 };
605 };
607 gcc: clock-controller@900000 {
608 compatible = "qcom,gcc-apq8064";
609 reg = <0x00900000 0x4000>;
610 #clock-cells = <1>;
611 #reset-cells = <1>;
612 };
614 lcc: clock-controller@28000000 {
615 compatible = "qcom,lcc-apq8064";
616 reg = <0x28000000 0x1000>;
617 #clock-cells = <1>;
618 #reset-cells = <1>;
619 };
621 mmcc: clock-controller@4000000 {
622 compatible = "qcom,mmcc-apq8064";
623 reg = <0x4000000 0x1000>;
624 #clock-cells = <1>;
625 #reset-cells = <1>;
626 };
628 l2cc: clock-controller@2011000 {
629 compatible = "syscon";
630 reg = <0x2011000 0x1000>;
631 };
633 rpm@108000 {
634 compatible = "qcom,rpm-apq8064";
635 reg = <0x108000 0x1000>;
636 qcom,ipc = <&l2cc 0x8 2>;
638 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
639 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
640 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
641 interrupt-names = "ack", "err", "wakeup";
643 rpmcc: clock-controller {
644 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
645 #clock-cells = <1>;
646 };
648 regulators {
649 compatible = "qcom,rpm-pm8921-regulators";
651 pm8921_s1: s1 {};
652 pm8921_s2: s2 {};
653 pm8921_s3: s3 {};
654 pm8921_s4: s4 {};
655 pm8921_s7: s7 {};
656 pm8921_s8: s8 {};
658 pm8921_l1: l1 {};
659 pm8921_l2: l2 {};
660 pm8921_l3: l3 {};
661 pm8921_l4: l4 {};
662 pm8921_l5: l5 {};
663 pm8921_l6: l6 {};
664 pm8921_l7: l7 {};
665 pm8921_l8: l8 {};
666 pm8921_l9: l9 {};
667 pm8921_l10: l10 {};
668 pm8921_l11: l11 {};
669 pm8921_l12: l12 {};
670 pm8921_l14: l14 {};
671 pm8921_l15: l15 {};
672 pm8921_l16: l16 {};
673 pm8921_l17: l17 {};
674 pm8921_l18: l18 {};
675 pm8921_l21: l21 {};
676 pm8921_l22: l22 {};
677 pm8921_l23: l23 {};
678 pm8921_l24: l24 {};
679 pm8921_l25: l25 {};
680 pm8921_l26: l26 {};
681 pm8921_l27: l27 {};
682 pm8921_l28: l28 {};
683 pm8921_l29: l29 {};
685 pm8921_lvs1: lvs1 {};
686 pm8921_lvs2: lvs2 {};
687 pm8921_lvs3: lvs3 {};
688 pm8921_lvs4: lvs4 {};
689 pm8921_lvs5: lvs5 {};
690 pm8921_lvs6: lvs6 {};
691 pm8921_lvs7: lvs7 {};
693 pm8921_usb_switch: usb-switch {};
695 pm8921_hdmi_switch: hdmi-switch {
696 bias-pull-down;
697 };
699 pm8921_ncp: ncp {};
700 };
701 };
703 usb1_phy: phy@12500000 {
704 compatible = "qcom,usb-otg-ci";
705 reg = <0x12500000 0x400>;
706 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
707 status = "disabled";
708 dr_mode = "host";
710 clocks = <&gcc USB_HS1_XCVR_CLK>,
711 <&gcc USB_HS1_H_CLK>;
712 clock-names = "core", "iface";
714 resets = <&gcc USB_HS1_RESET>;
715 reset-names = "link";
716 };
718 usb3_phy: phy@12520000 {
719 compatible = "qcom,usb-otg-ci";
720 reg = <0x12520000 0x400>;
721 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
722 status = "disabled";
723 dr_mode = "host";
725 clocks = <&gcc USB_HS3_XCVR_CLK>,
726 <&gcc USB_HS3_H_CLK>;
727 clock-names = "core", "iface";
729 resets = <&gcc USB_HS3_RESET>;
730 reset-names = "link";
731 };
733 usb4_phy: phy@12530000 {
734 compatible = "qcom,usb-otg-ci";
735 reg = <0x12530000 0x400>;
736 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
737 status = "disabled";
738 dr_mode = "host";
740 clocks = <&gcc USB_HS4_XCVR_CLK>,
741 <&gcc USB_HS4_H_CLK>;
742 clock-names = "core", "iface";
744 resets = <&gcc USB_HS4_RESET>;
745 reset-names = "link";
746 };
748 gadget1: gadget@12500000 {
749 compatible = "qcom,ci-hdrc";
750 reg = <0x12500000 0x400>;
751 status = "disabled";
752 dr_mode = "peripheral";
753 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
754 usb-phy = <&usb1_phy>;
755 };
757 usb1: usb@12500000 {
758 compatible = "qcom,ehci-host";
759 reg = <0x12500000 0x400>;
760 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
761 status = "disabled";
762 usb-phy = <&usb1_phy>;
763 };
765 usb3: usb@12520000 {
766 compatible = "qcom,ehci-host";
767 reg = <0x12520000 0x400>;
768 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
769 status = "disabled";
770 usb-phy = <&usb3_phy>;
771 };
773 usb4: usb@12530000 {
774 compatible = "qcom,ehci-host";
775 reg = <0x12530000 0x400>;
776 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
777 status = "disabled";
778 usb-phy = <&usb4_phy>;
779 };
781 sata_phy0: phy@1b400000 {
782 compatible = "qcom,apq8064-sata-phy";
783 status = "disabled";
784 reg = <0x1b400000 0x200>;
785 reg-names = "phy_mem";
786 clocks = <&gcc SATA_PHY_CFG_CLK>;
787 clock-names = "cfg";
788 #phy-cells = <0>;
789 };
791 sata0: sata@29000000 {
792 compatible = "qcom,apq8064-ahci", "generic-ahci";
793 status = "disabled";
794 reg = <0x29000000 0x180>;
795 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
797 clocks = <&gcc SFAB_SATA_S_H_CLK>,
798 <&gcc SATA_H_CLK>,
799 <&gcc SATA_A_CLK>,
800 <&gcc SATA_RXOOB_CLK>,
801 <&gcc SATA_PMALIVE_CLK>;
802 clock-names = "slave_iface",
803 "iface",
804 "bus",
805 "rxoob",
806 "core_pmalive";
808 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
809 <&gcc SATA_PMALIVE_CLK>;
810 assigned-clock-rates = <100000000>, <100000000>;
812 phys = <&sata_phy0>;
813 phy-names = "sata-phy";
814 ports-implemented = <0x1>;
815 };
817 /* Temporary fixed regulator */
818 sdcc1bam:dma@12402000{
819 compatible = "qcom,bam-v1.3.0";
820 reg = <0x12402000 0x8000>;
821 interrupts = <0 98 0>;
822 clocks = <&gcc SDC1_H_CLK>;
823 clock-names = "bam_clk";
824 #dma-cells = <1>;
825 qcom,ee = <0>;
826 };
828 sdcc3bam:dma@12182000{
829 compatible = "qcom,bam-v1.3.0";
830 reg = <0x12182000 0x8000>;
831 interrupts = <0 96 0>;
832 clocks = <&gcc SDC3_H_CLK>;
833 clock-names = "bam_clk";
834 #dma-cells = <1>;
835 qcom,ee = <0>;
836 };
838 sdcc4bam:dma@121c2000{
839 compatible = "qcom,bam-v1.3.0";
840 reg = <0x121c2000 0x8000>;
841 interrupts = <0 95 0>;
842 clocks = <&gcc SDC4_H_CLK>;
843 clock-names = "bam_clk";
844 #dma-cells = <1>;
845 qcom,ee = <0>;
846 };
848 amba {
849 compatible = "simple-bus";
850 #address-cells = <1>;
851 #size-cells = <1>;
852 ranges;
853 sdcc1: sdcc@12400000 {
854 status = "disabled";
855 compatible = "arm,pl18x", "arm,primecell";
856 arm,primecell-periphid = <0x00051180>;
857 reg = <0x12400000 0x2000>;
858 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
859 interrupt-names = "cmd_irq";
860 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
861 clock-names = "mclk", "apb_pclk";
862 bus-width = <8>;
863 max-frequency = <96000000>;
864 non-removable;
865 cap-sd-highspeed;
866 cap-mmc-highspeed;
867 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
868 dma-names = "tx", "rx";
869 };
871 sdcc3: sdcc@12180000 {
872 compatible = "arm,pl18x", "arm,primecell";
873 arm,primecell-periphid = <0x00051180>;
874 status = "disabled";
875 reg = <0x12180000 0x2000>;
876 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
877 interrupt-names = "cmd_irq";
878 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
879 clock-names = "mclk", "apb_pclk";
880 bus-width = <4>;
881 cap-sd-highspeed;
882 cap-mmc-highspeed;
883 max-frequency = <192000000>;
884 no-1-8-v;
885 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
886 dma-names = "tx", "rx";
887 };
889 sdcc4: sdcc@121c0000 {
890 compatible = "arm,pl18x", "arm,primecell";
891 arm,primecell-periphid = <0x00051180>;
892 status = "disabled";
893 reg = <0x121c0000 0x2000>;
894 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
895 interrupt-names = "cmd_irq";
896 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
897 clock-names = "mclk", "apb_pclk";
898 bus-width = <4>;
899 cap-sd-highspeed;
900 cap-mmc-highspeed;
901 max-frequency = <48000000>;
902 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
903 dma-names = "tx", "rx";
904 pinctrl-names = "default";
905 pinctrl-0 = <&sdc4_gpios>;
906 };
907 };
909 tcsr: syscon@1a400000 {
910 compatible = "qcom,tcsr-apq8064", "syscon";
911 reg = <0x1a400000 0x100>;
912 };
914 pcie: pci@1b500000 {
915 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
916 reg = <0x1b500000 0x1000
917 0x1b502000 0x80
918 0x1b600000 0x100
919 0x0ff00000 0x100000>;
920 reg-names = "dbi", "elbi", "parf", "config";
921 device_type = "pci";
922 linux,pci-domain = <0>;
923 bus-range = <0x00 0xff>;
924 num-lanes = <1>;
925 #address-cells = <3>;
926 #size-cells = <2>;
927 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
928 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
929 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
930 interrupt-names = "msi";
931 #interrupt-cells = <1>;
932 interrupt-map-mask = <0 0 0 0x7>;
933 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
934 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
935 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
936 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
937 clocks = <&gcc PCIE_A_CLK>,
938 <&gcc PCIE_H_CLK>,
939 <&gcc PCIE_PHY_REF_CLK>;
940 clock-names = "core", "iface", "phy";
941 resets = <&gcc PCIE_ACLK_RESET>,
942 <&gcc PCIE_HCLK_RESET>,
943 <&gcc PCIE_POR_RESET>,
944 <&gcc PCIE_PCI_RESET>,
945 <&gcc PCIE_PHY_RESET>;
946 reset-names = "axi", "ahb", "por", "pci", "phy";
947 status = "disabled";
948 };
949 };
950 };
951 #include "qcom-apq8064-pins.dtsi"