arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   6 #include <dt-bindings/soc/qcom,gsbi.h>
   7
   8 / {
   9         model = "Qualcomm IPQ8064";
  10         compatible = "qcom,ipq8064";
  11         interrupt-parent = <&intc>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu@0 {
  18                         compatible = "qcom,krait";
  19                         enable-method = "qcom,kpss-acc-v1";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                         qcom,acc = <&acc0>;
  24                         qcom,saw = <&saw0>;
  25                 };
  26
  27                 cpu@1 {
  28                         compatible = "qcom,krait";
  29                         enable-method = "qcom,kpss-acc-v1";
  30                         device_type = "cpu";
  31                         reg = <1>;
  32                         next-level-cache = <&L2>;
  33                         qcom,acc = <&acc1>;
  34                         qcom,saw = <&saw1>;
  35                 };
  36
  37                 L2: l2-cache {
  38                         compatible = "cache";
  39                         cache-level = <2>;
  40                 };
  41         };
  42
  43         cpu-pmu {
  44                 compatible = "qcom,krait-pmu";
  45                 interrupts = <1 10 0x304>;
  46         };
  47
  48         reserved-memory {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52
  53                 nss@40000000 {
  54                         reg = <0x40000000 0x1000000>;
  55                         no-map;
  56                 };
  57
  58                 smem@41000000 {
  59                         reg = <0x41000000 0x200000>;
  60                         no-map;
  61                 };
  62         };
  63
  64         clocks {
  65                 cxo_board {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-frequency = <19200000>;
  69                 };
  70
  71                 pxo_board {
  72                         compatible = "fixed-clock";
  73                         #clock-cells = <0>;
  74                         clock-frequency = <27000000>;
  75                 };
  76
  77                 sleep_clk: sleep_clk {
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <32768>;
  80                         #clock-cells = <0>;
  81                 };
  82         };
  83
  84         soc: soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 compatible = "simple-bus";
  89
  90                 lpass@28100000 {
  91                         compatible = "qcom,lpass-cpu";
  92                         status = "disabled";
  93                         clocks = <&lcc AHBIX_CLK>,
  94                                         <&lcc MI2S_OSR_CLK>,
  95                                         <&lcc MI2S_BIT_CLK>;
  96                         clock-names = "ahbix-clk",
  97                                         "mi2s-osr-clk",
  98                                         "mi2s-bit-clk";
  99                         interrupts = <0 85 1>;
 100                         interrupt-names = "lpass-irq-lpaif";
 101                         reg = <0x28100000 0x10000>;
 102                         reg-names = "lpass-lpaif";
 103                 };
 104
 105                 qcom_pinmux: pinmux@800000 {
 106                         compatible = "qcom,ipq8064-pinctrl";
 107                         reg = <0x800000 0x4000>;
 108
 109                         gpio-controller;
 110                         #gpio-cells = <2>;
 111                         interrupt-controller;
 112                         #interrupt-cells = <2>;
 113                         interrupts = <0 16 0x4>;
 114                 };
 115
 116                 intc: interrupt-controller@2000000 {
 117                         compatible = "qcom,msm-qgic2";
 118                         interrupt-controller;
 119                         #interrupt-cells = <3>;
 120                         reg = <0x02000000 0x1000>,
 121                               <0x02002000 0x1000>;
 122                 };
 123
 124                 timer@200a000 {
 125                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 126                         interrupts = <1 1 0x301>,
 127                                      <1 2 0x301>,
 128                                      <1 3 0x301>,
 129                                      <1 4 0x301>,
 130                                      <1 5 0x301>;
 131                         reg = <0x0200a000 0x100>;
 132                         clock-frequency = <25000000>,
 133                                           <32768>;
 134                         clocks = <&sleep_clk>;
 135                         clock-names = "sleep";
 136                         cpu-offset = <0x80000>;
 137                 };
 138
 139                 acc0: clock-controller@2088000 {
 140                         compatible = "qcom,kpss-acc-v1";
 141                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 142                 };
 143
 144                 acc1: clock-controller@2098000 {
 145                         compatible = "qcom,kpss-acc-v1";
 146                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 147                 };
 148
 149                 saw0: regulator@2089000 {
 150                         compatible = "qcom,saw2";
 151                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 152                         regulator;
 153                 };
 154
 155                 saw1: regulator@2099000 {
 156                         compatible = "qcom,saw2";
 157                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 158                         regulator;
 159                 };
 160
 161                 gsbi2: gsbi@12480000 {
 162                         compatible = "qcom,gsbi-v1.0.0";
 163                         cell-index = <2>;
 164                         reg = <0x12480000 0x100>;
 165                         clocks = <&gcc GSBI2_H_CLK>;
 166                         clock-names = "iface";
 167                         #address-cells = <1>;
 168                         #size-cells = <1>;
 169                         ranges;
 170                         status = "disabled";
 171
 172                         syscon-tcsr = <&tcsr>;
 173
 174                         serial@12490000 {
 175                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 176                                 reg = <0x12490000 0x1000>,
 177                                       <0x12480000 0x1000>;
 178                                 interrupts = <0 195 0x0>;
 179                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 180                                 clock-names = "core", "iface";
 181                                 status = "disabled";
 182                         };
 183
 184                         i2c@124a0000 {
 185                                 compatible = "qcom,i2c-qup-v1.1.1";
 186                                 reg = <0x124a0000 0x1000>;
 187                                 interrupts = <0 196 0>;
 188
 189                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 190                                 clock-names = "core", "iface";
 191                                 status = "disabled";
 192
 193                                 #address-cells = <1>;
 194                                 #size-cells = <0>;
 195                         };
 196
 197                 };
 198
 199                 gsbi4: gsbi@16300000 {
 200                         compatible = "qcom,gsbi-v1.0.0";
 201                         cell-index = <4>;
 202                         reg = <0x16300000 0x100>;
 203                         clocks = <&gcc GSBI4_H_CLK>;
 204                         clock-names = "iface";
 205                         #address-cells = <1>;
 206                         #size-cells = <1>;
 207                         ranges;
 208                         status = "disabled";
 209
 210                         syscon-tcsr = <&tcsr>;
 211
 212                         gsbi4_serial: serial@16340000 {
 213                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 214                                 reg = <0x16340000 0x1000>,
 215                                       <0x16300000 0x1000>;
 216                                 interrupts = <0 152 0x0>;
 217                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 218                                 clock-names = "core", "iface";
 219                                 status = "disabled";
 220                         };
 221
 222                         i2c@16380000 {
 223                                 compatible = "qcom,i2c-qup-v1.1.1";
 224                                 reg = <0x16380000 0x1000>;
 225                                 interrupts = <0 153 0>;
 226
 227                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 228                                 clock-names = "core", "iface";
 229                                 status = "disabled";
 230
 231                                 #address-cells = <1>;
 232                                 #size-cells = <0>;
 233                         };
 234                 };
 235
 236                 gsbi5: gsbi@1a200000 {
 237                         compatible = "qcom,gsbi-v1.0.0";
 238                         cell-index = <5>;
 239                         reg = <0x1a200000 0x100>;
 240                         clocks = <&gcc GSBI5_H_CLK>;
 241                         clock-names = "iface";
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         ranges;
 245                         status = "disabled";
 246
 247                         syscon-tcsr = <&tcsr>;
 248
 249                         serial@1a240000 {
 250                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 251                                 reg = <0x1a240000 0x1000>,
 252                                       <0x1a200000 0x1000>;
 253                                 interrupts = <0 154 0x0>;
 254                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 255                                 clock-names = "core", "iface";
 256                                 status = "disabled";
 257                         };
 258
 259                         i2c@1a280000 {
 260                                 compatible = "qcom,i2c-qup-v1.1.1";
 261                                 reg = <0x1a280000 0x1000>;
 262                                 interrupts = <0 155 0>;
 263
 264                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 265                                 clock-names = "core", "iface";
 266                                 status = "disabled";
 267
 268                                 #address-cells = <1>;
 269                                 #size-cells = <0>;
 270                         };
 271
 272                         spi@1a280000 {
 273                                 compatible = "qcom,spi-qup-v1.1.1";
 274                                 reg = <0x1a280000 0x1000>;
 275                                 interrupts = <0 155 0>;
 276
 277                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 278                                 clock-names = "core", "iface";
 279                                 status = "disabled";
 280
 281                                 #address-cells = <1>;
 282                                 #size-cells = <0>;
 283                         };
 284                 };
 285
 286                 sata_phy: sata-phy@1b400000 {
 287                         compatible = "qcom,ipq806x-sata-phy";
 288                         reg = <0x1b400000 0x200>;
 289
 290                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 291                         clock-names = "cfg";
 292
 293                         #phy-cells = <0>;
 294                         status = "disabled";
 295                 };
 296
 297                 sata@29000000 {
 298                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 299                         reg = <0x29000000 0x180>;
 300
 301                         interrupts = <0 209 0x0>;
 302
 303                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 304                                  <&gcc SATA_H_CLK>,
 305                                  <&gcc SATA_A_CLK>,
 306                                  <&gcc SATA_RXOOB_CLK>,
 307                                  <&gcc SATA_PMALIVE_CLK>;
 308                         clock-names = "slave_face", "iface", "core",
 309                                         "rxoob", "pmalive";
 310
 311                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 312                         assigned-clock-rates = <100000000>, <100000000>;
 313
 314                         phys = <&sata_phy>;
 315                         phy-names = "sata-phy";
 316                         status = "disabled";
 317                 };
 318
 319                 qcom,ssbi@500000 {
 320                         compatible = "qcom,ssbi";
 321                         reg = <0x00500000 0x1000>;
 322                         qcom,controller-type = "pmic-arbiter";
 323                 };
 324
 325                 gcc: clock-controller@900000 {
 326                         compatible = "qcom,gcc-ipq8064";
 327                         reg = <0x00900000 0x4000>;
 328                         #clock-cells = <1>;
 329                         #reset-cells = <1>;
 330                 };
 331
 332                 tcsr: syscon@1a400000 {
 333                         compatible = "qcom,tcsr-ipq8064", "syscon";
 334                         reg = <0x1a400000 0x100>;
 335                 };
 336
 337                 lcc: clock-controller@28000000 {
 338                         compatible = "qcom,lcc-ipq8064";
 339                         reg = <0x28000000 0x1000>;
 340                         #clock-cells = <1>;
 341                         #reset-cells = <1>;
 342                 };
 343
 344         };
 345 };