| blob | 83cf23cd26bb51e6632cffb9e87a12cdc2ea442f |
1 /*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
13 #include <dt-bindings/clock/r8a7790-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/power/r8a7790-sysc.h>
18 / {
19 compatible = "renesas,r8a7790";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
24 aliases {
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 i2c4 = &iic0;
30 i2c5 = &iic1;
31 i2c6 = &iic2;
32 i2c7 = &iic3;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 spi4 = &msiof3;
38 vin0 = &vin0;
39 vin1 = &vin1;
40 vin2 = &vin2;
41 vin3 = &vin3;
42 };
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a15";
51 reg = <0>;
52 clock-frequency = <1300000000>;
53 voltage-tolerance = <1>; /* 1% */
54 clocks = <&cpg_clocks R8A7790_CLK_Z>;
55 clock-latency = <300000>; /* 300 us */
56 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
57 next-level-cache = <&L2_CA15>;
59 /* kHz - uV - OPPs unknown yet */
60 operating-points = <1400000 1000000>,
61 <1225000 1000000>,
62 <1050000 1000000>,
63 < 875000 1000000>,
64 < 700000 1000000>,
65 < 350000 1000000>;
66 };
68 cpu1: cpu@1 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a15";
71 reg = <1>;
72 clock-frequency = <1300000000>;
73 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
74 next-level-cache = <&L2_CA15>;
75 };
77 cpu2: cpu@2 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a15";
80 reg = <2>;
81 clock-frequency = <1300000000>;
82 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
83 next-level-cache = <&L2_CA15>;
84 };
86 cpu3: cpu@3 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a15";
89 reg = <3>;
90 clock-frequency = <1300000000>;
91 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
92 next-level-cache = <&L2_CA15>;
93 };
95 cpu4: cpu@4 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a7";
98 reg = <0x100>;
99 clock-frequency = <780000000>;
100 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
101 next-level-cache = <&L2_CA7>;
102 };
104 cpu5: cpu@5 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a7";
107 reg = <0x101>;
108 clock-frequency = <780000000>;
109 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
110 next-level-cache = <&L2_CA7>;
111 };
113 cpu6: cpu@6 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a7";
116 reg = <0x102>;
117 clock-frequency = <780000000>;
118 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
119 next-level-cache = <&L2_CA7>;
120 };
122 cpu7: cpu@7 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a7";
125 reg = <0x103>;
126 clock-frequency = <780000000>;
127 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
128 next-level-cache = <&L2_CA7>;
129 };
130 };
132 thermal-zones {
133 cpu_thermal: cpu-thermal {
134 polling-delay-passive = <0>;
135 polling-delay = <0>;
137 thermal-sensors = <&thermal>;
139 trips {
140 cpu-crit {
141 temperature = <115000>;
142 hysteresis = <0>;
143 type = "critical";
144 };
145 };
146 cooling-maps {
147 };
148 };
149 };
151 L2_CA15: cache-controller@0 {
152 compatible = "cache";
153 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
154 cache-unified;
155 cache-level = <2>;
156 };
158 L2_CA7: cache-controller@1 {
159 compatible = "cache";
160 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
161 cache-unified;
162 cache-level = <2>;
163 };
165 gic: interrupt-controller@f1001000 {
166 compatible = "arm,gic-400";
167 #interrupt-cells = <3>;
168 #address-cells = <0>;
169 interrupt-controller;
170 reg = <0 0xf1001000 0 0x1000>,
171 <0 0xf1002000 0 0x1000>,
172 <0 0xf1004000 0 0x2000>,
173 <0 0xf1006000 0 0x2000>;
174 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
175 };
177 gpio0: gpio@e6050000 {
178 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
179 reg = <0 0xe6050000 0 0x50>;
180 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
181 #gpio-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pfc 0 0 32>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
187 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
188 };
190 gpio1: gpio@e6051000 {
191 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
192 reg = <0 0xe6051000 0 0x50>;
193 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
194 #gpio-cells = <2>;
195 gpio-controller;
196 gpio-ranges = <&pfc 0 32 30>;
197 #interrupt-cells = <2>;
198 interrupt-controller;
199 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
200 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
201 };
203 gpio2: gpio@e6052000 {
204 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
205 reg = <0 0xe6052000 0 0x50>;
206 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
207 #gpio-cells = <2>;
208 gpio-controller;
209 gpio-ranges = <&pfc 0 64 30>;
210 #interrupt-cells = <2>;
211 interrupt-controller;
212 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
213 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
214 };
216 gpio3: gpio@e6053000 {
217 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
218 reg = <0 0xe6053000 0 0x50>;
219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
220 #gpio-cells = <2>;
221 gpio-controller;
222 gpio-ranges = <&pfc 0 96 32>;
223 #interrupt-cells = <2>;
224 interrupt-controller;
225 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
226 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
227 };
229 gpio4: gpio@e6054000 {
230 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
231 reg = <0 0xe6054000 0 0x50>;
232 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 128 32>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
239 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
240 };
242 gpio5: gpio@e6055000 {
243 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
244 reg = <0 0xe6055000 0 0x50>;
245 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
246 #gpio-cells = <2>;
247 gpio-controller;
248 gpio-ranges = <&pfc 0 160 32>;
249 #interrupt-cells = <2>;
250 interrupt-controller;
251 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
252 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
253 };
255 thermal: thermal@e61f0000 {
256 compatible = "renesas,thermal-r8a7790",
257 "renesas,rcar-gen2-thermal",
258 "renesas,rcar-thermal";
259 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
260 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
262 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
263 #thermal-sensor-cells = <0>;
264 };
266 timer {
267 compatible = "arm,armv7-timer";
268 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
269 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
270 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
271 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
272 };
274 cmt0: timer@ffca0000 {
275 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
276 reg = <0 0xffca0000 0 0x1004>;
277 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
280 clock-names = "fck";
281 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
283 renesas,channels-mask = <0x60>;
285 status = "disabled";
286 };
288 cmt1: timer@e6130000 {
289 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
290 reg = <0 0xe6130000 0 0x1004>;
291 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
300 clock-names = "fck";
301 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
303 renesas,channels-mask = <0xff>;
305 status = "disabled";
306 };
308 irqc0: interrupt-controller@e61c0000 {
309 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
310 #interrupt-cells = <2>;
311 interrupt-controller;
312 reg = <0 0xe61c0000 0 0x200>;
313 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
318 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
319 };
321 dmac0: dma-controller@e6700000 {
322 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
323 reg = <0 0xe6700000 0 0x20000>;
324 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "error",
341 "ch0", "ch1", "ch2", "ch3",
342 "ch4", "ch5", "ch6", "ch7",
343 "ch8", "ch9", "ch10", "ch11",
344 "ch12", "ch13", "ch14";
345 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
346 clock-names = "fck";
347 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
348 #dma-cells = <1>;
349 dma-channels = <15>;
350 };
352 dmac1: dma-controller@e6720000 {
353 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
354 reg = <0 0xe6720000 0 0x20000>;
355 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-names = "error",
372 "ch0", "ch1", "ch2", "ch3",
373 "ch4", "ch5", "ch6", "ch7",
374 "ch8", "ch9", "ch10", "ch11",
375 "ch12", "ch13", "ch14";
376 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
377 clock-names = "fck";
378 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
379 #dma-cells = <1>;
380 dma-channels = <15>;
381 };
383 audma0: dma-controller@ec700000 {
384 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
385 reg = <0 0xec700000 0 0x10000>;
386 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
397 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
398 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
399 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
400 interrupt-names = "error",
401 "ch0", "ch1", "ch2", "ch3",
402 "ch4", "ch5", "ch6", "ch7",
403 "ch8", "ch9", "ch10", "ch11",
404 "ch12";
405 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
406 clock-names = "fck";
407 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
408 #dma-cells = <1>;
409 dma-channels = <13>;
410 };
412 audma1: dma-controller@ec720000 {
413 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
414 reg = <0 0xec720000 0 0x10000>;
415 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
424 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
425 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
426 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
427 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
428 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "error",
430 "ch0", "ch1", "ch2", "ch3",
431 "ch4", "ch5", "ch6", "ch7",
432 "ch8", "ch9", "ch10", "ch11",
433 "ch12";
434 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
435 clock-names = "fck";
436 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
437 #dma-cells = <1>;
438 dma-channels = <13>;
439 };
441 usb_dmac0: dma-controller@e65a0000 {
442 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
443 reg = <0 0xe65a0000 0 0x100>;
444 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
445 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "ch0", "ch1";
447 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
448 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
449 #dma-cells = <1>;
450 dma-channels = <2>;
451 };
453 usb_dmac1: dma-controller@e65b0000 {
454 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
455 reg = <0 0xe65b0000 0 0x100>;
456 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
457 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "ch0", "ch1";
459 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
460 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
461 #dma-cells = <1>;
462 dma-channels = <2>;
463 };
465 i2c0: i2c@e6508000 {
466 #address-cells = <1>;
467 #size-cells = <0>;
468 compatible = "renesas,i2c-r8a7790";
469 reg = <0 0xe6508000 0 0x40>;
470 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
472 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
473 i2c-scl-internal-delay-ns = <110>;
474 status = "disabled";
475 };
477 i2c1: i2c@e6518000 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "renesas,i2c-r8a7790";
481 reg = <0 0xe6518000 0 0x40>;
482 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
484 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
485 i2c-scl-internal-delay-ns = <6>;
486 status = "disabled";
487 };
489 i2c2: i2c@e6530000 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "renesas,i2c-r8a7790";
493 reg = <0 0xe6530000 0 0x40>;
494 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
496 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
497 i2c-scl-internal-delay-ns = <6>;
498 status = "disabled";
499 };
501 i2c3: i2c@e6540000 {
502 #address-cells = <1>;
503 #size-cells = <0>;
504 compatible = "renesas,i2c-r8a7790";
505 reg = <0 0xe6540000 0 0x40>;
506 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
508 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
509 i2c-scl-internal-delay-ns = <110>;
510 status = "disabled";
511 };
513 iic0: i2c@e6500000 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
517 reg = <0 0xe6500000 0 0x425>;
518 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
520 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
521 dma-names = "tx", "rx";
522 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
523 status = "disabled";
524 };
526 iic1: i2c@e6510000 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
530 reg = <0 0xe6510000 0 0x425>;
531 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
533 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
534 dma-names = "tx", "rx";
535 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
536 status = "disabled";
537 };
539 iic2: i2c@e6520000 {
540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
543 reg = <0 0xe6520000 0 0x425>;
544 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
546 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
547 dma-names = "tx", "rx";
548 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
549 status = "disabled";
550 };
552 iic3: i2c@e60b0000 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
556 reg = <0 0xe60b0000 0 0x425>;
557 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
559 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
560 dma-names = "tx", "rx";
561 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
562 status = "disabled";
563 };
565 mmcif0: mmc@ee200000 {
566 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
567 reg = <0 0xee200000 0 0x80>;
568 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
570 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
571 dma-names = "tx", "rx";
572 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
573 reg-io-width = <4>;
574 status = "disabled";
575 max-frequency = <97500000>;
576 };
578 mmcif1: mmc@ee220000 {
579 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
580 reg = <0 0xee220000 0 0x80>;
581 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
583 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
584 dma-names = "tx", "rx";
585 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
586 reg-io-width = <4>;
587 status = "disabled";
588 max-frequency = <97500000>;
589 };
591 pfc: pfc@e6060000 {
592 compatible = "renesas,pfc-r8a7790";
593 reg = <0 0xe6060000 0 0x250>;
594 };
596 sdhi0: sd@ee100000 {
597 compatible = "renesas,sdhi-r8a7790";
598 reg = <0 0xee100000 0 0x328>;
599 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
601 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
602 dma-names = "tx", "rx";
603 max-frequency = <195000000>;
604 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
605 status = "disabled";
606 };
608 sdhi1: sd@ee120000 {
609 compatible = "renesas,sdhi-r8a7790";
610 reg = <0 0xee120000 0 0x328>;
611 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
613 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
614 dma-names = "tx", "rx";
615 max-frequency = <195000000>;
616 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
617 status = "disabled";
618 };
620 sdhi2: sd@ee140000 {
621 compatible = "renesas,sdhi-r8a7790";
622 reg = <0 0xee140000 0 0x100>;
623 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
625 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
626 dma-names = "tx", "rx";
627 max-frequency = <97500000>;
628 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
629 status = "disabled";
630 };
632 sdhi3: sd@ee160000 {
633 compatible = "renesas,sdhi-r8a7790";
634 reg = <0 0xee160000 0 0x100>;
635 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
637 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
638 dma-names = "tx", "rx";
639 max-frequency = <97500000>;
640 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
641 status = "disabled";
642 };
644 scifa0: serial@e6c40000 {
645 compatible = "renesas,scifa-r8a7790",
646 "renesas,rcar-gen2-scifa", "renesas,scifa";
647 reg = <0 0xe6c40000 0 64>;
648 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
650 clock-names = "fck";
651 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
652 dma-names = "tx", "rx";
653 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
654 status = "disabled";
655 };
657 scifa1: serial@e6c50000 {
658 compatible = "renesas,scifa-r8a7790",
659 "renesas,rcar-gen2-scifa", "renesas,scifa";
660 reg = <0 0xe6c50000 0 64>;
661 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
663 clock-names = "fck";
664 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
665 dma-names = "tx", "rx";
666 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
667 status = "disabled";
668 };
670 scifa2: serial@e6c60000 {
671 compatible = "renesas,scifa-r8a7790",
672 "renesas,rcar-gen2-scifa", "renesas,scifa";
673 reg = <0 0xe6c60000 0 64>;
674 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
676 clock-names = "fck";
677 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
678 dma-names = "tx", "rx";
679 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
680 status = "disabled";
681 };
683 scifb0: serial@e6c20000 {
684 compatible = "renesas,scifb-r8a7790",
685 "renesas,rcar-gen2-scifb", "renesas,scifb";
686 reg = <0 0xe6c20000 0 64>;
687 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
689 clock-names = "fck";
690 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
691 dma-names = "tx", "rx";
692 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
693 status = "disabled";
694 };
696 scifb1: serial@e6c30000 {
697 compatible = "renesas,scifb-r8a7790",
698 "renesas,rcar-gen2-scifb", "renesas,scifb";
699 reg = <0 0xe6c30000 0 64>;
700 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
702 clock-names = "fck";
703 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
704 dma-names = "tx", "rx";
705 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
706 status = "disabled";
707 };
709 scifb2: serial@e6ce0000 {
710 compatible = "renesas,scifb-r8a7790",
711 "renesas,rcar-gen2-scifb", "renesas,scifb";
712 reg = <0 0xe6ce0000 0 64>;
713 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
715 clock-names = "fck";
716 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
717 dma-names = "tx", "rx";
718 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
719 status = "disabled";
720 };
722 scif0: serial@e6e60000 {
723 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
724 "renesas,scif";
725 reg = <0 0xe6e60000 0 64>;
726 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
728 <&scif_clk>;
729 clock-names = "fck", "brg_int", "scif_clk";
730 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
731 dma-names = "tx", "rx";
732 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
733 status = "disabled";
734 };
736 scif1: serial@e6e68000 {
737 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
738 "renesas,scif";
739 reg = <0 0xe6e68000 0 64>;
740 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
742 <&scif_clk>;
743 clock-names = "fck", "brg_int", "scif_clk";
744 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
745 dma-names = "tx", "rx";
746 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
747 status = "disabled";
748 };
750 scif2: serial@e6e56000 {
751 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
752 "renesas,scif";
753 reg = <0 0xe6e56000 0 64>;
754 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
756 <&scif_clk>;
757 clock-names = "fck", "brg_int", "scif_clk";
758 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
759 dma-names = "tx", "rx";
760 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
761 status = "disabled";
762 };
764 hscif0: serial@e62c0000 {
765 compatible = "renesas,hscif-r8a7790",
766 "renesas,rcar-gen2-hscif", "renesas,hscif";
767 reg = <0 0xe62c0000 0 96>;
768 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
770 <&scif_clk>;
771 clock-names = "fck", "brg_int", "scif_clk";
772 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
773 dma-names = "tx", "rx";
774 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
775 status = "disabled";
776 };
778 hscif1: serial@e62c8000 {
779 compatible = "renesas,hscif-r8a7790",
780 "renesas,rcar-gen2-hscif", "renesas,hscif";
781 reg = <0 0xe62c8000 0 96>;
782 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
784 <&scif_clk>;
785 clock-names = "fck", "brg_int", "scif_clk";
786 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
787 dma-names = "tx", "rx";
788 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
789 status = "disabled";
790 };
792 ether: ethernet@ee700000 {
793 compatible = "renesas,ether-r8a7790";
794 reg = <0 0xee700000 0 0x400>;
795 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
797 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
798 phy-mode = "rmii";
799 #address-cells = <1>;
800 #size-cells = <0>;
801 status = "disabled";
802 };
804 avb: ethernet@e6800000 {
805 compatible = "renesas,etheravb-r8a7790",
806 "renesas,etheravb-rcar-gen2";
807 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
808 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
810 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
811 #address-cells = <1>;
812 #size-cells = <0>;
813 status = "disabled";
814 };
816 sata0: sata@ee300000 {
817 compatible = "renesas,sata-r8a7790";
818 reg = <0 0xee300000 0 0x2000>;
819 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
821 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
822 status = "disabled";
823 };
825 sata1: sata@ee500000 {
826 compatible = "renesas,sata-r8a7790";
827 reg = <0 0xee500000 0 0x2000>;
828 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
830 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
831 status = "disabled";
832 };
834 hsusb: usb@e6590000 {
835 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
836 reg = <0 0xe6590000 0 0x100>;
837 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
839 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
840 <&usb_dmac1 0>, <&usb_dmac1 1>;
841 dma-names = "ch0", "ch1", "ch2", "ch3";
842 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
843 renesas,buswait = <4>;
844 phys = <&usb0 1>;
845 phy-names = "usb";
846 status = "disabled";
847 };
849 usbphy: usb-phy@e6590100 {
850 compatible = "renesas,usb-phy-r8a7790";
851 reg = <0 0xe6590100 0 0x100>;
852 #address-cells = <1>;
853 #size-cells = <0>;
854 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
855 clock-names = "usbhs";
856 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
857 status = "disabled";
859 usb0: usb-channel@0 {
860 reg = <0>;
861 #phy-cells = <1>;
862 };
863 usb2: usb-channel@2 {
864 reg = <2>;
865 #phy-cells = <1>;
866 };
867 };
869 vin0: video@e6ef0000 {
870 compatible = "renesas,vin-r8a7790";
871 reg = <0 0xe6ef0000 0 0x1000>;
872 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
874 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
875 status = "disabled";
876 };
878 vin1: video@e6ef1000 {
879 compatible = "renesas,vin-r8a7790";
880 reg = <0 0xe6ef1000 0 0x1000>;
881 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
883 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
884 status = "disabled";
885 };
887 vin2: video@e6ef2000 {
888 compatible = "renesas,vin-r8a7790";
889 reg = <0 0xe6ef2000 0 0x1000>;
890 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
892 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
893 status = "disabled";
894 };
896 vin3: video@e6ef3000 {
897 compatible = "renesas,vin-r8a7790";
898 reg = <0 0xe6ef3000 0 0x1000>;
899 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
901 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
902 status = "disabled";
903 };
905 vsp1@fe920000 {
906 compatible = "renesas,vsp1";
907 reg = <0 0xfe920000 0 0x8000>;
908 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
910 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
912 renesas,has-sru;
913 renesas,#rpf = <5>;
914 renesas,#uds = <1>;
915 renesas,#wpf = <4>;
916 };
918 vsp1@fe928000 {
919 compatible = "renesas,vsp1";
920 reg = <0 0xfe928000 0 0x8000>;
921 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
923 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
925 renesas,has-lut;
926 renesas,has-sru;
927 renesas,#rpf = <5>;
928 renesas,#uds = <3>;
929 renesas,#wpf = <4>;
930 };
932 vsp1@fe930000 {
933 compatible = "renesas,vsp1";
934 reg = <0 0xfe930000 0 0x8000>;
935 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
937 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
939 renesas,has-lif;
940 renesas,has-lut;
941 renesas,#rpf = <4>;
942 renesas,#uds = <1>;
943 renesas,#wpf = <4>;
944 };
946 vsp1@fe938000 {
947 compatible = "renesas,vsp1";
948 reg = <0 0xfe938000 0 0x8000>;
949 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
951 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
953 renesas,has-lif;
954 renesas,has-lut;
955 renesas,#rpf = <4>;
956 renesas,#uds = <1>;
957 renesas,#wpf = <4>;
958 };
960 du: display@feb00000 {
961 compatible = "renesas,du-r8a7790";
962 reg = <0 0xfeb00000 0 0x70000>,
963 <0 0xfeb90000 0 0x1c>,
964 <0 0xfeb94000 0 0x1c>;
965 reg-names = "du", "lvds.0", "lvds.1";
966 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
970 <&mstp7_clks R8A7790_CLK_DU1>,
971 <&mstp7_clks R8A7790_CLK_DU2>,
972 <&mstp7_clks R8A7790_CLK_LVDS0>,
973 <&mstp7_clks R8A7790_CLK_LVDS1>;
974 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
975 status = "disabled";
977 ports {
978 #address-cells = <1>;
979 #size-cells = <0>;
981 port@0 {
982 reg = <0>;
983 du_out_rgb: endpoint {
984 };
985 };
986 port@1 {
987 reg = <1>;
988 du_out_lvds0: endpoint {
989 };
990 };
991 port@2 {
992 reg = <2>;
993 du_out_lvds1: endpoint {
994 };
995 };
996 };
997 };
999 can0: can@e6e80000 {
1000 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1001 reg = <0 0xe6e80000 0 0x1000>;
1002 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1004 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1005 clock-names = "clkp1", "clkp2", "can_clk";
1006 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1007 status = "disabled";
1008 };
1010 can1: can@e6e88000 {
1011 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1012 reg = <0 0xe6e88000 0 0x1000>;
1013 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1015 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1016 clock-names = "clkp1", "clkp2", "can_clk";
1017 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1018 status = "disabled";
1019 };
1021 jpu: jpeg-codec@fe980000 {
1022 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
1023 reg = <0 0xfe980000 0 0x10300>;
1024 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1026 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1027 };
1029 clocks {
1030 #address-cells = <2>;
1031 #size-cells = <2>;
1032 ranges;
1034 /* External root clock */
1035 extal_clk: extal {
1036 compatible = "fixed-clock";
1037 #clock-cells = <0>;
1038 /* This value must be overriden by the board. */
1039 clock-frequency = <0>;
1040 };
1042 /* External PCIe clock - can be overridden by the board */
1043 pcie_bus_clk: pcie_bus {
1044 compatible = "fixed-clock";
1045 #clock-cells = <0>;
1046 clock-frequency = <0>;
1047 };
1049 /*
1050 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1051 * default. Boards that provide audio clocks should override them.
1052 */
1053 audio_clk_a: audio_clk_a {
1054 compatible = "fixed-clock";
1055 #clock-cells = <0>;
1056 clock-frequency = <0>;
1057 };
1058 audio_clk_b: audio_clk_b {
1059 compatible = "fixed-clock";
1060 #clock-cells = <0>;
1061 clock-frequency = <0>;
1062 };
1063 audio_clk_c: audio_clk_c {
1064 compatible = "fixed-clock";
1065 #clock-cells = <0>;
1066 clock-frequency = <0>;
1067 };
1069 /* External SCIF clock */
1070 scif_clk: scif {
1071 compatible = "fixed-clock";
1072 #clock-cells = <0>;
1073 /* This value must be overridden by the board. */
1074 clock-frequency = <0>;
1075 };
1077 /* External USB clock - can be overridden by the board */
1078 usb_extal_clk: usb_extal {
1079 compatible = "fixed-clock";
1080 #clock-cells = <0>;
1081 clock-frequency = <48000000>;
1082 };
1084 /* External CAN clock */
1085 can_clk: can_clk {
1086 compatible = "fixed-clock";
1087 #clock-cells = <0>;
1088 /* This value must be overridden by the board. */
1089 clock-frequency = <0>;
1090 };
1092 /* Special CPG clocks */
1093 cpg_clocks: cpg_clocks@e6150000 {
1094 compatible = "renesas,r8a7790-cpg-clocks",
1095 "renesas,rcar-gen2-cpg-clocks";
1096 reg = <0 0xe6150000 0 0x1000>;
1097 clocks = <&extal_clk &usb_extal_clk>;
1098 #clock-cells = <1>;
1099 clock-output-names = "main", "pll0", "pll1", "pll3",
1100 "lb", "qspi", "sdh", "sd0", "sd1",
1101 "z", "rcan", "adsp";
1102 #power-domain-cells = <0>;
1103 };
1105 /* Variable factor clocks */
1106 sd2_clk: sd2@e6150078 {
1107 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1108 reg = <0 0xe6150078 0 4>;
1109 clocks = <&pll1_div2_clk>;
1110 #clock-cells = <0>;
1111 };
1112 sd3_clk: sd3@e615026c {
1113 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1114 reg = <0 0xe615026c 0 4>;
1115 clocks = <&pll1_div2_clk>;
1116 #clock-cells = <0>;
1117 };
1118 mmc0_clk: mmc0@e6150240 {
1119 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1120 reg = <0 0xe6150240 0 4>;
1121 clocks = <&pll1_div2_clk>;
1122 #clock-cells = <0>;
1123 };
1124 mmc1_clk: mmc1@e6150244 {
1125 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1126 reg = <0 0xe6150244 0 4>;
1127 clocks = <&pll1_div2_clk>;
1128 #clock-cells = <0>;
1129 };
1130 ssp_clk: ssp@e6150248 {
1131 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1132 reg = <0 0xe6150248 0 4>;
1133 clocks = <&pll1_div2_clk>;
1134 #clock-cells = <0>;
1135 };
1136 ssprs_clk: ssprs@e615024c {
1137 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1138 reg = <0 0xe615024c 0 4>;
1139 clocks = <&pll1_div2_clk>;
1140 #clock-cells = <0>;
1141 };
1143 /* Fixed factor clocks */
1144 pll1_div2_clk: pll1_div2 {
1145 compatible = "fixed-factor-clock";
1146 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1147 #clock-cells = <0>;
1148 clock-div = <2>;
1149 clock-mult = <1>;
1150 };
1151 z2_clk: z2 {
1152 compatible = "fixed-factor-clock";
1153 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1154 #clock-cells = <0>;
1155 clock-div = <2>;
1156 clock-mult = <1>;
1157 };
1158 zg_clk: zg {
1159 compatible = "fixed-factor-clock";
1160 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1161 #clock-cells = <0>;
1162 clock-div = <3>;
1163 clock-mult = <1>;
1164 };
1165 zx_clk: zx {
1166 compatible = "fixed-factor-clock";
1167 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1168 #clock-cells = <0>;
1169 clock-div = <3>;
1170 clock-mult = <1>;
1171 };
1172 zs_clk: zs {
1173 compatible = "fixed-factor-clock";
1174 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1175 #clock-cells = <0>;
1176 clock-div = <6>;
1177 clock-mult = <1>;
1178 };
1179 hp_clk: hp {
1180 compatible = "fixed-factor-clock";
1181 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1182 #clock-cells = <0>;
1183 clock-div = <12>;
1184 clock-mult = <1>;
1185 };
1186 i_clk: i {
1187 compatible = "fixed-factor-clock";
1188 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1189 #clock-cells = <0>;
1190 clock-div = <2>;
1191 clock-mult = <1>;
1192 };
1193 b_clk: b {
1194 compatible = "fixed-factor-clock";
1195 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1196 #clock-cells = <0>;
1197 clock-div = <12>;
1198 clock-mult = <1>;
1199 };
1200 p_clk: p {
1201 compatible = "fixed-factor-clock";
1202 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1203 #clock-cells = <0>;
1204 clock-div = <24>;
1205 clock-mult = <1>;
1206 };
1207 cl_clk: cl {
1208 compatible = "fixed-factor-clock";
1209 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1210 #clock-cells = <0>;
1211 clock-div = <48>;
1212 clock-mult = <1>;
1213 };
1214 m2_clk: m2 {
1215 compatible = "fixed-factor-clock";
1216 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1217 #clock-cells = <0>;
1218 clock-div = <8>;
1219 clock-mult = <1>;
1220 };
1221 imp_clk: imp {
1222 compatible = "fixed-factor-clock";
1223 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1224 #clock-cells = <0>;
1225 clock-div = <4>;
1226 clock-mult = <1>;
1227 };
1228 rclk_clk: rclk {
1229 compatible = "fixed-factor-clock";
1230 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1231 #clock-cells = <0>;
1232 clock-div = <(48 * 1024)>;
1233 clock-mult = <1>;
1234 };
1235 oscclk_clk: oscclk {
1236 compatible = "fixed-factor-clock";
1237 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1238 #clock-cells = <0>;
1239 clock-div = <(12 * 1024)>;
1240 clock-mult = <1>;
1241 };
1242 zb3_clk: zb3 {
1243 compatible = "fixed-factor-clock";
1244 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1245 #clock-cells = <0>;
1246 clock-div = <4>;
1247 clock-mult = <1>;
1248 };
1249 zb3d2_clk: zb3d2 {
1250 compatible = "fixed-factor-clock";
1251 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1252 #clock-cells = <0>;
1253 clock-div = <8>;
1254 clock-mult = <1>;
1255 };
1256 ddr_clk: ddr {
1257 compatible = "fixed-factor-clock";
1258 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1259 #clock-cells = <0>;
1260 clock-div = <8>;
1261 clock-mult = <1>;
1262 };
1263 mp_clk: mp {
1264 compatible = "fixed-factor-clock";
1265 clocks = <&pll1_div2_clk>;
1266 #clock-cells = <0>;
1267 clock-div = <15>;
1268 clock-mult = <1>;
1269 };
1270 cp_clk: cp {
1271 compatible = "fixed-factor-clock";
1272 clocks = <&extal_clk>;
1273 #clock-cells = <0>;
1274 clock-div = <2>;
1275 clock-mult = <1>;
1276 };
1278 /* Gate clocks */
1279 mstp0_clks: mstp0_clks@e6150130 {
1280 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1281 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1282 clocks = <&mp_clk>;
1283 #clock-cells = <1>;
1284 clock-indices = <R8A7790_CLK_MSIOF0>;
1285 clock-output-names = "msiof0";
1286 };
1287 mstp1_clks: mstp1_clks@e6150134 {
1288 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1289 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1290 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1291 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1292 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1293 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1294 #clock-cells = <1>;
1295 clock-indices = <
1296 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1297 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1298 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1299 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1300 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1301 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1302 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1303 >;
1304 clock-output-names =
1305 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1306 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1307 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1308 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1309 };
1310 mstp2_clks: mstp2_clks@e6150138 {
1311 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1312 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1313 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1314 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1315 <&zs_clk>;
1316 #clock-cells = <1>;
1317 clock-indices = <
1318 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1319 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1320 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1321 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1322 >;
1323 clock-output-names =
1324 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1325 "scifb1", "msiof1", "msiof3", "scifb2",
1326 "sys-dmac1", "sys-dmac0";
1327 };
1328 mstp3_clks: mstp3_clks@e615013c {
1329 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1330 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1331 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1332 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1333 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1334 <&hp_clk>, <&hp_clk>;
1335 #clock-cells = <1>;
1336 clock-indices = <
1337 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1338 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1339 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1340 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1341 >;
1342 clock-output-names =
1343 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1344 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1345 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1346 "usbdmac0", "usbdmac1";
1347 };
1348 mstp4_clks: mstp4_clks@e6150140 {
1349 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1350 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1351 clocks = <&cp_clk>;
1352 #clock-cells = <1>;
1353 clock-indices = <R8A7790_CLK_IRQC>;
1354 clock-output-names = "irqc";
1355 };
1356 mstp5_clks: mstp5_clks@e6150144 {
1357 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1358 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1359 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1360 <&extal_clk>, <&p_clk>;
1361 #clock-cells = <1>;
1362 clock-indices = <
1363 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1364 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1365 R8A7790_CLK_PWM
1366 >;
1367 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1368 "thermal", "pwm";
1369 };
1370 mstp7_clks: mstp7_clks@e615014c {
1371 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1372 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1373 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1374 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1375 <&zx_clk>;
1376 #clock-cells = <1>;
1377 clock-indices = <
1378 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1379 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1380 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1381 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1382 >;
1383 clock-output-names =
1384 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1385 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1386 };
1387 mstp8_clks: mstp8_clks@e6150990 {
1388 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1389 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1390 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1391 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1392 <&zs_clk>;
1393 #clock-cells = <1>;
1394 clock-indices = <
1395 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1396 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1397 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1398 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1399 >;
1400 clock-output-names =
1401 "mlb", "vin3", "vin2", "vin1", "vin0",
1402 "etheravb", "ether", "sata1", "sata0";
1403 };
1404 mstp9_clks: mstp9_clks@e6150994 {
1405 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1406 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1407 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1408 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1409 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1410 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1411 #clock-cells = <1>;
1412 clock-indices = <
1413 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1414 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1415 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1416 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1417 >;
1418 clock-output-names =
1419 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1420 "rcan1", "rcan0", "qspi_mod", "iic3",
1421 "i2c3", "i2c2", "i2c1", "i2c0";
1422 };
1423 mstp10_clks: mstp10_clks@e6150998 {
1424 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1425 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1426 clocks = <&p_clk>,
1427 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1428 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1429 <&p_clk>,
1430 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1431 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1432 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1433 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1434 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1435 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1436 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1438 #clock-cells = <1>;
1439 clock-indices = <
1440 R8A7790_CLK_SSI_ALL
1441 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1442 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1443 R8A7790_CLK_SCU_ALL
1444 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1445 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1446 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1447 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1448 >;
1449 clock-output-names =
1450 "ssi-all",
1451 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1452 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1453 "scu-all",
1454 "scu-dvc1", "scu-dvc0",
1455 "scu-ctu1-mix1", "scu-ctu0-mix0",
1456 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1457 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1458 };
1459 };
1461 sysc: system-controller@e6180000 {
1462 compatible = "renesas,r8a7790-sysc";
1463 reg = <0 0xe6180000 0 0x0200>;
1464 #power-domain-cells = <1>;
1465 };
1467 qspi: spi@e6b10000 {
1468 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1469 reg = <0 0xe6b10000 0 0x2c>;
1470 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1472 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1473 dma-names = "tx", "rx";
1474 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1475 num-cs = <1>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 status = "disabled";
1479 };
1481 msiof0: spi@e6e20000 {
1482 compatible = "renesas,msiof-r8a7790";
1483 reg = <0 0xe6e20000 0 0x0064>;
1484 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1486 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1487 dma-names = "tx", "rx";
1488 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 status = "disabled";
1492 };
1494 msiof1: spi@e6e10000 {
1495 compatible = "renesas,msiof-r8a7790";
1496 reg = <0 0xe6e10000 0 0x0064>;
1497 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1499 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1500 dma-names = "tx", "rx";
1501 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504 status = "disabled";
1505 };
1507 msiof2: spi@e6e00000 {
1508 compatible = "renesas,msiof-r8a7790";
1509 reg = <0 0xe6e00000 0 0x0064>;
1510 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1512 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1513 dma-names = "tx", "rx";
1514 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1517 status = "disabled";
1518 };
1520 msiof3: spi@e6c90000 {
1521 compatible = "renesas,msiof-r8a7790";
1522 reg = <0 0xe6c90000 0 0x0064>;
1523 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1524 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1525 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1526 dma-names = "tx", "rx";
1527 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1533 xhci: usb@ee000000 {
1534 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1535 reg = <0 0xee000000 0 0xc00>;
1536 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1538 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1539 phys = <&usb2 1>;
1540 phy-names = "usb";
1541 status = "disabled";
1542 };
1544 pci0: pci@ee090000 {
1545 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1546 device_type = "pci";
1547 reg = <0 0xee090000 0 0xc00>,
1548 <0 0xee080000 0 0x1100>;
1549 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1550 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1551 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1552 status = "disabled";
1554 bus-range = <0 0>;
1555 #address-cells = <3>;
1556 #size-cells = <2>;
1557 #interrupt-cells = <1>;
1558 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1559 interrupt-map-mask = <0xff00 0 0 0x7>;
1560 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1561 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1562 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1564 usb@0,1 {
1565 reg = <0x800 0 0 0 0>;
1566 device_type = "pci";
1567 phys = <&usb0 0>;
1568 phy-names = "usb";
1569 };
1571 usb@0,2 {
1572 reg = <0x1000 0 0 0 0>;
1573 device_type = "pci";
1574 phys = <&usb0 0>;
1575 phy-names = "usb";
1576 };
1577 };
1579 pci1: pci@ee0b0000 {
1580 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1581 device_type = "pci";
1582 reg = <0 0xee0b0000 0 0xc00>,
1583 <0 0xee0a0000 0 0x1100>;
1584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1586 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1587 status = "disabled";
1589 bus-range = <1 1>;
1590 #address-cells = <3>;
1591 #size-cells = <2>;
1592 #interrupt-cells = <1>;
1593 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1594 interrupt-map-mask = <0xff00 0 0 0x7>;
1595 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1596 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1597 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1598 };
1600 pci2: pci@ee0d0000 {
1601 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1602 device_type = "pci";
1603 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1604 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1605 reg = <0 0xee0d0000 0 0xc00>,
1606 <0 0xee0c0000 0 0x1100>;
1607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1608 status = "disabled";
1610 bus-range = <2 2>;
1611 #address-cells = <3>;
1612 #size-cells = <2>;
1613 #interrupt-cells = <1>;
1614 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1615 interrupt-map-mask = <0xff00 0 0 0x7>;
1616 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1617 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1618 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1620 usb@0,1 {
1621 reg = <0x800 0 0 0 0>;
1622 device_type = "pci";
1623 phys = <&usb2 0>;
1624 phy-names = "usb";
1625 };
1627 usb@0,2 {
1628 reg = <0x1000 0 0 0 0>;
1629 device_type = "pci";
1630 phys = <&usb2 0>;
1631 phy-names = "usb";
1632 };
1633 };
1635 pciec: pcie@fe000000 {
1636 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1637 reg = <0 0xfe000000 0 0x80000>;
1638 #address-cells = <3>;
1639 #size-cells = <2>;
1640 bus-range = <0x00 0xff>;
1641 device_type = "pci";
1642 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1643 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1644 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1645 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1646 /* Map all possible DDR as inbound ranges */
1647 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1648 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1649 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1652 #interrupt-cells = <1>;
1653 interrupt-map-mask = <0 0 0 0>;
1654 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1656 clock-names = "pcie", "pcie_bus";
1657 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1658 status = "disabled";
1659 };
1661 rcar_sound: sound@ec500000 {
1662 /*
1663 * #sound-dai-cells is required
1664 *
1665 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1666 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1667 */
1668 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1669 reg = <0 0xec500000 0 0x1000>, /* SCU */
1670 <0 0xec5a0000 0 0x100>, /* ADG */
1671 <0 0xec540000 0 0x1000>, /* SSIU */
1672 <0 0xec541000 0 0x280>, /* SSI */
1673 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1674 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1676 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1677 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1678 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1679 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1680 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1681 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1682 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1683 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1684 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1685 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1686 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1687 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1688 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1689 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1690 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1691 clock-names = "ssi-all",
1692 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1693 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1694 "src.9", "src.8", "src.7", "src.6", "src.5",
1695 "src.4", "src.3", "src.2", "src.1", "src.0",
1696 "ctu.0", "ctu.1",
1697 "mix.0", "mix.1",
1698 "dvc.0", "dvc.1",
1699 "clk_a", "clk_b", "clk_c", "clk_i";
1700 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1702 status = "disabled";
1704 rcar_sound,dvc {
1705 dvc0: dvc@0 {
1706 dmas = <&audma0 0xbc>;
1707 dma-names = "tx";
1708 };
1709 dvc1: dvc@1 {
1710 dmas = <&audma0 0xbe>;
1711 dma-names = "tx";
1712 };
1713 };
1715 rcar_sound,mix {
1716 mix0: mix@0 { };
1717 mix1: mix@1 { };
1718 };
1720 rcar_sound,ctu {
1721 ctu00: ctu@0 { };
1722 ctu01: ctu@1 { };
1723 ctu02: ctu@2 { };
1724 ctu03: ctu@3 { };
1725 ctu10: ctu@4 { };
1726 ctu11: ctu@5 { };
1727 ctu12: ctu@6 { };
1728 ctu13: ctu@7 { };
1729 };
1731 rcar_sound,src {
1732 src0: src@0 {
1733 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1734 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1735 dma-names = "rx", "tx";
1736 };
1737 src1: src@1 {
1738 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1740 dma-names = "rx", "tx";
1741 };
1742 src2: src@2 {
1743 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1744 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1745 dma-names = "rx", "tx";
1746 };
1747 src3: src@3 {
1748 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1749 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1750 dma-names = "rx", "tx";
1751 };
1752 src4: src@4 {
1753 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1754 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1755 dma-names = "rx", "tx";
1756 };
1757 src5: src@5 {
1758 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1760 dma-names = "rx", "tx";
1761 };
1762 src6: src@6 {
1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1764 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1765 dma-names = "rx", "tx";
1766 };
1767 src7: src@7 {
1768 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1769 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1770 dma-names = "rx", "tx";
1771 };
1772 src8: src@8 {
1773 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1774 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1775 dma-names = "rx", "tx";
1776 };
1777 src9: src@9 {
1778 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1779 dmas = <&audma0 0x97>, <&audma1 0xba>;
1780 dma-names = "rx", "tx";
1781 };
1782 };
1784 rcar_sound,ssi {
1785 ssi0: ssi@0 {
1786 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1788 dma-names = "rx", "tx", "rxu", "txu";
1789 };
1790 ssi1: ssi@1 {
1791 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1793 dma-names = "rx", "tx", "rxu", "txu";
1794 };
1795 ssi2: ssi@2 {
1796 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1798 dma-names = "rx", "tx", "rxu", "txu";
1799 };
1800 ssi3: ssi@3 {
1801 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1803 dma-names = "rx", "tx", "rxu", "txu";
1804 };
1805 ssi4: ssi@4 {
1806 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1808 dma-names = "rx", "tx", "rxu", "txu";
1809 };
1810 ssi5: ssi@5 {
1811 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1813 dma-names = "rx", "tx", "rxu", "txu";
1814 };
1815 ssi6: ssi@6 {
1816 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1818 dma-names = "rx", "tx", "rxu", "txu";
1819 };
1820 ssi7: ssi@7 {
1821 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1823 dma-names = "rx", "tx", "rxu", "txu";
1824 };
1825 ssi8: ssi@8 {
1826 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1828 dma-names = "rx", "tx", "rxu", "txu";
1829 };
1830 ssi9: ssi@9 {
1831 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1832 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1833 dma-names = "rx", "tx", "rxu", "txu";
1834 };
1835 };
1836 };
1838 ipmmu_sy0: mmu@e6280000 {
1839 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1840 reg = <0 0xe6280000 0 0x1000>;
1841 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1843 #iommu-cells = <1>;
1844 status = "disabled";
1845 };
1847 ipmmu_sy1: mmu@e6290000 {
1848 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1849 reg = <0 0xe6290000 0 0x1000>;
1850 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1851 #iommu-cells = <1>;
1852 status = "disabled";
1853 };
1855 ipmmu_ds: mmu@e6740000 {
1856 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1857 reg = <0 0xe6740000 0 0x1000>;
1858 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1860 #iommu-cells = <1>;
1861 status = "disabled";
1862 };
1864 ipmmu_mp: mmu@ec680000 {
1865 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1866 reg = <0 0xec680000 0 0x1000>;
1867 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1868 #iommu-cells = <1>;
1869 status = "disabled";
1870 };
1872 ipmmu_mx: mmu@fe951000 {
1873 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1874 reg = <0 0xfe951000 0 0x1000>;
1875 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1877 #iommu-cells = <1>;
1878 status = "disabled";
1879 };
1881 ipmmu_rt: mmu@ffc80000 {
1882 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1883 reg = <0 0xffc80000 0 0x1000>;
1884 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1885 #iommu-cells = <1>;
1886 status = "disabled";
1887 };
1888 };