arch/arm/boot/dts/rk3228.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3228";
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@f00 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0xf00>;
  68                         resets = <&cru SRST_CORE0>;
  69                         operating-points = <
  70                                 /* KHz    uV */
  71                                  816000 1000000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77
  78                 cpu1: cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                         resets = <&cru SRST_CORE1>;
  83                 };
  84
  85                 cpu2: cpu@f02 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0xf02>;
  89                         resets = <&cru SRST_CORE2>;
  90                 };
  91
  92                 cpu3: cpu@f03 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a7";
  95                         reg = <0xf03>;
  96                         resets = <&cru SRST_CORE3>;
  97                 };
  98         };
  99
 100         amba {
 101                 compatible = "simple-bus";
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 ranges;
 105
 106                 pdma: pdma@110f0000 {
 107                         compatible = "arm,pl330", "arm,primecell";
 108                         reg = <0x110f0000 0x4000>;
 109                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 110                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 111                         #dma-cells = <1>;
 112                         clocks = <&cru ACLK_DMAC>;
 113                         clock-names = "apb_pclk";
 114                 };
 115         };
 116
 117         arm-pmu {
 118                 compatible = "arm,cortex-a7-pmu";
 119                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 123                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv7-timer";
 128                 arm,cpu-registers-not-fw-configured;
 129                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 131                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 132                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 133                 clock-frequency = <24000000>;
 134         };
 135
 136         xin24m: oscillator {
 137                 compatible = "fixed-clock";
 138                 clock-frequency = <24000000>;
 139                 clock-output-names = "xin24m";
 140                 #clock-cells = <0>;
 141         };
 142
 143         grf: syscon@11000000 {
 144                 compatible = "syscon";
 145                 reg = <0x11000000 0x1000>;
 146         };
 147
 148         uart0: serial@11010000 {
 149                 compatible = "snps,dw-apb-uart";
 150                 reg = <0x11010000 0x100>;
 151                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 152                 clock-frequency = <24000000>;
 153                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 154                 clock-names = "baudclk", "apb_pclk";
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 157                 reg-shift = <2>;
 158                 reg-io-width = <4>;
 159                 status = "disabled";
 160         };
 161
 162         uart1: serial@11020000 {
 163                 compatible = "snps,dw-apb-uart";
 164                 reg = <0x11020000 0x100>;
 165                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 166                 clock-frequency = <24000000>;
 167                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 168                 clock-names = "baudclk", "apb_pclk";
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&uart1_xfer>;
 171                 reg-shift = <2>;
 172                 reg-io-width = <4>;
 173                 status = "disabled";
 174         };
 175
 176         uart2: serial@11030000 {
 177                 compatible = "snps,dw-apb-uart";
 178                 reg = <0x11030000 0x100>;
 179                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 180                 clock-frequency = <24000000>;
 181                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 182                 clock-names = "baudclk", "apb_pclk";
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&uart2_xfer>;
 185                 reg-shift = <2>;
 186                 reg-io-width = <4>;
 187                 status = "disabled";
 188         };
 189
 190         i2c0: i2c@11050000 {
 191                 compatible = "rockchip,rk3228-i2c";
 192                 reg = <0x11050000 0x1000>;
 193                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 clock-names = "i2c";
 197                 clocks = <&cru PCLK_I2C0>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&i2c0_xfer>;
 200                 status = "disabled";
 201         };
 202
 203         i2c1: i2c@11060000 {
 204                 compatible = "rockchip,rk3228-i2c";
 205                 reg = <0x11060000 0x1000>;
 206                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 207                 #address-cells = <1>;
 208                 #size-cells = <0>;
 209                 clock-names = "i2c";
 210                 clocks = <&cru PCLK_I2C1>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&i2c1_xfer>;
 213                 status = "disabled";
 214         };
 215
 216         i2c2: i2c@11070000 {
 217                 compatible = "rockchip,rk3228-i2c";
 218                 reg = <0x11070000 0x1000>;
 219                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 220                 #address-cells = <1>;
 221                 #size-cells = <0>;
 222                 clock-names = "i2c";
 223                 clocks = <&cru PCLK_I2C2>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&i2c2_xfer>;
 226                 status = "disabled";
 227         };
 228
 229         i2c3: i2c@11080000 {
 230                 compatible = "rockchip,rk3228-i2c";
 231                 reg = <0x11080000 0x1000>;
 232                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 clock-names = "i2c";
 236                 clocks = <&cru PCLK_I2C3>;
 237                 pinctrl-names = "default";
 238                 pinctrl-0 = <&i2c3_xfer>;
 239                 status = "disabled";
 240         };
 241
 242         pwm0: pwm@110b0000 {
 243                 compatible = "rockchip,rk3288-pwm";
 244                 reg = <0x110b0000 0x10>;
 245                 #pwm-cells = <3>;
 246                 clocks = <&cru PCLK_PWM>;
 247                 clock-names = "pwm";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&pwm0_pin>;
 250                 status = "disabled";
 251         };
 252
 253         pwm1: pwm@110b0010 {
 254                 compatible = "rockchip,rk3288-pwm";
 255                 reg = <0x110b0010 0x10>;
 256                 #pwm-cells = <3>;
 257                 clocks = <&cru PCLK_PWM>;
 258                 clock-names = "pwm";
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&pwm1_pin>;
 261                 status = "disabled";
 262         };
 263
 264         pwm2: pwm@110b0020 {
 265                 compatible = "rockchip,rk3288-pwm";
 266                 reg = <0x110b0020 0x10>;
 267                 #pwm-cells = <3>;
 268                 clocks = <&cru PCLK_PWM>;
 269                 clock-names = "pwm";
 270                 pinctrl-names = "default";
 271                 pinctrl-0 = <&pwm2_pin>;
 272                 status = "disabled";
 273         };
 274
 275         pwm3: pwm@110b0030 {
 276                 compatible = "rockchip,rk3288-pwm";
 277                 reg = <0x110b0030 0x10>;
 278                 #pwm-cells = <2>;
 279                 clocks = <&cru PCLK_PWM>;
 280                 clock-names = "pwm";
 281                 pinctrl-names = "default";
 282                 pinctrl-0 = <&pwm3_pin>;
 283                 status = "disabled";
 284         };
 285
 286         timer: timer@110c0000 {
 287                 compatible = "rockchip,rk3288-timer";
 288                 reg = <0x110c0000 0x20>;
 289                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 290                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 291                 clock-names = "timer", "pclk";
 292         };
 293
 294         cru: clock-controller@110e0000 {
 295                 compatible = "rockchip,rk3228-cru";
 296                 reg = <0x110e0000 0x1000>;
 297                 rockchip,grf = <&grf>;
 298                 #clock-cells = <1>;
 299                 #reset-cells = <1>;
 300                 assigned-clocks = <&cru PLL_GPLL>;
 301                 assigned-clock-rates = <594000000>;
 302         };
 303
 304         thermal-zones {
 305                 cpu_thermal: cpu-thermal {
 306                         polling-delay-passive = <100>; /* milliseconds */
 307                         polling-delay = <5000>; /* milliseconds */
 308
 309                         thermal-sensors = <&tsadc 0>;
 310
 311                         trips {
 312                                 cpu_alert0: cpu_alert0 {
 313                                         temperature = <70000>; /* millicelsius */
 314                                         hysteresis = <2000>; /* millicelsius */
 315                                         type = "passive";
 316                                 };
 317                                 cpu_alert1: cpu_alert1 {
 318                                         temperature = <75000>; /* millicelsius */
 319                                         hysteresis = <2000>; /* millicelsius */
 320                                         type = "passive";
 321                                 };
 322                                 cpu_crit: cpu_crit {
 323                                         temperature = <90000>; /* millicelsius */
 324                                         hysteresis = <2000>; /* millicelsius */
 325                                         type = "critical";
 326                                 };
 327                         };
 328
 329                         cooling-maps {
 330                                 map0 {
 331                                         trip = <&cpu_alert0>;
 332                                         cooling-device =
 333                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 334                                 };
 335                                 map1 {
 336                                         trip = <&cpu_alert1>;
 337                                         cooling-device =
 338                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 339                                 };
 340                         };
 341                 };
 342         };
 343
 344         tsadc: tsadc@11150000 {
 345                 compatible = "rockchip,rk3228-tsadc";
 346                 reg = <0x11150000 0x100>;
 347                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 349                 clock-names = "tsadc", "apb_pclk";
 350                 resets = <&cru SRST_TSADC>;
 351                 reset-names = "tsadc-apb";
 352                 pinctrl-names = "init", "default", "sleep";
 353                 pinctrl-0 = <&otp_gpio>;
 354                 pinctrl-1 = <&otp_out>;
 355                 pinctrl-2 = <&otp_gpio>;
 356                 #thermal-sensor-cells = <0>;
 357                 rockchip,hw-tshut-temp = <95000>;
 358                 status = "disabled";
 359         };
 360
 361         emmc: dwmmc@30020000 {
 362                 compatible = "rockchip,rk3288-dw-mshc";
 363                 reg = <0x30020000 0x4000>;
 364                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 365                 clock-frequency = <37500000>;
 366                 clock-freq-min-max = <400000 37500000>;
 367                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 368                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 369                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 370                 bus-width = <8>;
 371                 default-sample-phase = <158>;
 372                 num-slots = <1>;
 373                 fifo-depth = <0x100>;
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 376                 status = "disabled";
 377         };
 378
 379         gic: interrupt-controller@32010000 {
 380                 compatible = "arm,gic-400";
 381                 interrupt-controller;
 382                 #interrupt-cells = <3>;
 383                 #address-cells = <0>;
 384
 385                 reg = <0x32011000 0x1000>,
 386                       <0x32012000 0x1000>,
 387                       <0x32014000 0x2000>,
 388                       <0x32016000 0x2000>;
 389                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 390         };
 391
 392         pinctrl: pinctrl {
 393                 compatible = "rockchip,rk3228-pinctrl";
 394                 rockchip,grf = <&grf>;
 395                 #address-cells = <1>;
 396                 #size-cells = <1>;
 397                 ranges;
 398
 399                 gpio0: gpio0@11110000 {
 400                         compatible = "rockchip,gpio-bank";
 401                         reg = <0x11110000 0x100>;
 402                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 403                         clocks = <&cru PCLK_GPIO0>;
 404
 405                         gpio-controller;
 406                         #gpio-cells = <2>;
 407
 408                         interrupt-controller;
 409                         #interrupt-cells = <2>;
 410                 };
 411
 412                 gpio1: gpio1@11120000 {
 413                         compatible = "rockchip,gpio-bank";
 414                         reg = <0x11120000 0x100>;
 415                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 416                         clocks = <&cru PCLK_GPIO1>;
 417
 418                         gpio-controller;
 419                         #gpio-cells = <2>;
 420
 421                         interrupt-controller;
 422                         #interrupt-cells = <2>;
 423                 };
 424
 425                 gpio2: gpio2@11130000 {
 426                         compatible = "rockchip,gpio-bank";
 427                         reg = <0x11130000 0x100>;
 428                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&cru PCLK_GPIO2>;
 430
 431                         gpio-controller;
 432                         #gpio-cells = <2>;
 433
 434                         interrupt-controller;
 435                         #interrupt-cells = <2>;
 436                 };
 437
 438                 gpio3: gpio3@11140000 {
 439                         compatible = "rockchip,gpio-bank";
 440                         reg = <0x11140000 0x100>;
 441                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&cru PCLK_GPIO3>;
 443
 444                         gpio-controller;
 445                         #gpio-cells = <2>;
 446
 447                         interrupt-controller;
 448                         #interrupt-cells = <2>;
 449                 };
 450
 451                 pcfg_pull_up: pcfg-pull-up {
 452                         bias-pull-up;
 453                 };
 454
 455                 pcfg_pull_down: pcfg-pull-down {
 456                         bias-pull-down;
 457                 };
 458
 459                 pcfg_pull_none: pcfg-pull-none {
 460                         bias-disable;
 461                 };
 462
 463                 emmc {
 464                         emmc_clk: emmc-clk {
 465                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 466                         };
 467
 468                         emmc_cmd: emmc-cmd {
 469                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 470                         };
 471
 472                         emmc_bus8: emmc-bus8 {
 473                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 474                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 475                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 476                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 477                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 478                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 479                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 480                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 481                         };
 482                 };
 483
 484                 i2c0 {
 485                         i2c0_xfer: i2c0-xfer {
 486                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 487                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 488                         };
 489                 };
 490
 491                 i2c1 {
 492                         i2c1_xfer: i2c1-xfer {
 493                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 494                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 495                         };
 496                 };
 497
 498                 i2c2 {
 499                         i2c2_xfer: i2c2-xfer {
 500                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 501                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 502                         };
 503                 };
 504
 505                 i2c3 {
 506                         i2c3_xfer: i2c3-xfer {
 507                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 508                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 509                         };
 510                 };
 511
 512                 pwm0 {
 513                         pwm0_pin: pwm0-pin {
 514                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
 515                         };
 516                 };
 517
 518                 pwm1 {
 519                         pwm1_pin: pwm1-pin {
 520                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
 521                         };
 522                 };
 523
 524                 pwm2 {
 525                         pwm2_pin: pwm2-pin {
 526                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
 527                         };
 528                 };
 529
 530                 pwm3 {
 531                         pwm3_pin: pwm3-pin {
 532                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
 533                         };
 534                 };
 535
 536                 tsadc {
 537                         otp_gpio: otp-gpio {
 538                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
 539                         };
 540
 541                         otp_out: otp-out {
 542                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
 543                         };
 544                 };
 545
 546                 uart0 {
 547                         uart0_xfer: uart0-xfer {
 548                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
 549                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
 550                         };
 551
 552                         uart0_cts: uart0-cts {
 553                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
 554                         };
 555
 556                         uart0_rts: uart0-rts {
 557                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
 558                         };
 559                 };
 560
 561                 uart1 {
 562                         uart1_xfer: uart1-xfer {
 563                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
 564                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
 565                         };
 566
 567                         uart1_cts: uart1-cts {
 568                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
 569                         };
 570
 571                         uart1_rts: uart1-rts {
 572                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
 573                         };
 574                 };
 575
 576                 uart2 {
 577                         uart2_xfer: uart2-xfer {
 578                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
 579                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 580                         };
 581
 582                         uart2_cts: uart2-cts {
 583                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
 584                         };
 585
 586                         uart2_rts: uart2-rts {
 587                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 588                         };
 589                 };
 590         };
 591 };