| blob | 7e05e09e61c7e49fa78a287220047e70f0b2fa99 |
1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
51 / {
52 interrupt-parent = <&gic>;
54 chosen {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
59 simplefb_lcd: framebuffer@0 {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0";
63 clocks = <&pll6 0>;
64 status = "disabled";
65 };
66 };
68 timer {
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 clock-frequency = <24000000>;
75 arm,cpu-registers-not-fw-configured;
76 };
78 cpus {
79 enable-method = "allwinner,sun8i-a23";
80 #address-cells = <1>;
81 #size-cells = <0>;
83 cpu@0 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <0>;
87 };
89 cpu@1 {
90 compatible = "arm,cortex-a7";
91 device_type = "cpu";
92 reg = <1>;
93 };
94 };
96 clocks {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
101 osc24M: osc24M_clk {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 clock-frequency = <24000000>;
105 clock-output-names = "osc24M";
106 };
108 osc32k: osc32k_clk {
109 #clock-cells = <0>;
110 compatible = "fixed-clock";
111 clock-frequency = <32768>;
112 clock-output-names = "osc32k";
113 };
115 pll1: clk@01c20000 {
116 #clock-cells = <0>;
117 compatible = "allwinner,sun8i-a23-pll1-clk";
118 reg = <0x01c20000 0x4>;
119 clocks = <&osc24M>;
120 clock-output-names = "pll1";
121 };
123 /* dummy clock until actually implemented */
124 pll5: pll5_clk {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 clock-output-names = "pll5";
129 };
131 pll6: clk@01c20028 {
132 #clock-cells = <1>;
133 compatible = "allwinner,sun6i-a31-pll6-clk";
134 reg = <0x01c20028 0x4>;
135 clocks = <&osc24M>;
136 clock-output-names = "pll6", "pll6x2";
137 };
139 cpu: cpu_clk@01c20050 {
140 #clock-cells = <0>;
141 compatible = "allwinner,sun4i-a10-cpu-clk";
142 reg = <0x01c20050 0x4>;
144 /*
145 * PLL1 is listed twice here.
146 * While it looks suspicious, it's actually documented
147 * that way both in the datasheet and in the code from
148 * Allwinner.
149 */
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
151 clock-output-names = "cpu";
152 };
154 axi: axi_clk@01c20050 {
155 #clock-cells = <0>;
156 compatible = "allwinner,sun8i-a23-axi-clk";
157 reg = <0x01c20050 0x4>;
158 clocks = <&cpu>;
159 clock-output-names = "axi";
160 };
162 ahb1: ahb1_clk@01c20054 {
163 #clock-cells = <0>;
164 compatible = "allwinner,sun6i-a31-ahb1-clk";
165 reg = <0x01c20054 0x4>;
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
167 clock-output-names = "ahb1";
168 };
170 apb1: apb1_clk@01c20054 {
171 #clock-cells = <0>;
172 compatible = "allwinner,sun4i-a10-apb0-clk";
173 reg = <0x01c20054 0x4>;
174 clocks = <&ahb1>;
175 clock-output-names = "apb1";
176 };
178 apb1_gates: clk@01c20068 {
179 #clock-cells = <1>;
180 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
181 reg = <0x01c20068 0x4>;
182 clocks = <&apb1>;
183 clock-indices = <0>, <5>,
184 <12>, <13>;
185 clock-output-names = "apb1_codec", "apb1_pio",
186 "apb1_daudio0", "apb1_daudio1";
187 };
189 apb2: clk@01c20058 {
190 #clock-cells = <0>;
191 compatible = "allwinner,sun4i-a10-apb1-clk";
192 reg = <0x01c20058 0x4>;
193 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
194 clock-output-names = "apb2";
195 };
197 apb2_gates: clk@01c2006c {
198 #clock-cells = <1>;
199 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
200 reg = <0x01c2006c 0x4>;
201 clocks = <&apb2>;
202 clock-indices = <0>, <1>,
203 <2>, <16>,
204 <17>, <18>,
205 <19>, <20>;
206 clock-output-names = "apb2_i2c0", "apb2_i2c1",
207 "apb2_i2c2", "apb2_uart0",
208 "apb2_uart1", "apb2_uart2",
209 "apb2_uart3", "apb2_uart4";
210 };
212 mmc0_clk: clk@01c20088 {
213 #clock-cells = <1>;
214 compatible = "allwinner,sun4i-a10-mmc-clk";
215 reg = <0x01c20088 0x4>;
216 clocks = <&osc24M>, <&pll6 0>;
217 clock-output-names = "mmc0",
218 "mmc0_output",
219 "mmc0_sample";
220 };
222 mmc1_clk: clk@01c2008c {
223 #clock-cells = <1>;
224 compatible = "allwinner,sun4i-a10-mmc-clk";
225 reg = <0x01c2008c 0x4>;
226 clocks = <&osc24M>, <&pll6 0>;
227 clock-output-names = "mmc1",
228 "mmc1_output",
229 "mmc1_sample";
230 };
232 mmc2_clk: clk@01c20090 {
233 #clock-cells = <1>;
234 compatible = "allwinner,sun4i-a10-mmc-clk";
235 reg = <0x01c20090 0x4>;
236 clocks = <&osc24M>, <&pll6 0>;
237 clock-output-names = "mmc2",
238 "mmc2_output",
239 "mmc2_sample";
240 };
242 usb_clk: clk@01c200cc {
243 #clock-cells = <1>;
244 #reset-cells = <1>;
245 compatible = "allwinner,sun8i-a23-usb-clk";
246 reg = <0x01c200cc 0x4>;
247 clocks = <&osc24M>;
248 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
249 "usb_hsic_12M", "usb_ohci0";
250 };
251 };
253 soc@01c00000 {
254 compatible = "simple-bus";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges;
259 dma: dma-controller@01c02000 {
260 compatible = "allwinner,sun8i-a23-dma";
261 reg = <0x01c02000 0x1000>;
262 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&ahb1_gates 6>;
264 resets = <&ahb1_rst 6>;
265 #dma-cells = <1>;
266 };
268 mmc0: mmc@01c0f000 {
269 compatible = "allwinner,sun5i-a13-mmc";
270 reg = <0x01c0f000 0x1000>;
271 clocks = <&ahb1_gates 8>,
272 <&mmc0_clk 0>,
273 <&mmc0_clk 1>,
274 <&mmc0_clk 2>;
275 clock-names = "ahb",
276 "mmc",
277 "output",
278 "sample";
279 resets = <&ahb1_rst 8>;
280 reset-names = "ahb";
281 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
282 status = "disabled";
283 #address-cells = <1>;
284 #size-cells = <0>;
285 };
287 mmc1: mmc@01c10000 {
288 compatible = "allwinner,sun5i-a13-mmc";
289 reg = <0x01c10000 0x1000>;
290 clocks = <&ahb1_gates 9>,
291 <&mmc1_clk 0>,
292 <&mmc1_clk 1>,
293 <&mmc1_clk 2>;
294 clock-names = "ahb",
295 "mmc",
296 "output",
297 "sample";
298 resets = <&ahb1_rst 9>;
299 reset-names = "ahb";
300 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
301 status = "disabled";
302 #address-cells = <1>;
303 #size-cells = <0>;
304 };
306 mmc2: mmc@01c11000 {
307 compatible = "allwinner,sun5i-a13-mmc";
308 reg = <0x01c11000 0x1000>;
309 clocks = <&ahb1_gates 10>,
310 <&mmc2_clk 0>,
311 <&mmc2_clk 1>,
312 <&mmc2_clk 2>;
313 clock-names = "ahb",
314 "mmc",
315 "output",
316 "sample";
317 resets = <&ahb1_rst 10>;
318 reset-names = "ahb";
319 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
320 status = "disabled";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
325 ehci0: usb@01c1a000 {
326 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
327 reg = <0x01c1a000 0x100>;
328 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&ahb1_gates 26>;
330 resets = <&ahb1_rst 26>;
331 phys = <&usbphy 1>;
332 phy-names = "usb";
333 status = "disabled";
334 };
336 ohci0: usb@01c1a400 {
337 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
338 reg = <0x01c1a400 0x100>;
339 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
341 resets = <&ahb1_rst 29>;
342 phys = <&usbphy 1>;
343 phy-names = "usb";
344 status = "disabled";
345 };
347 pio: pinctrl@01c20800 {
348 /* compatible gets set in SoC specific dtsi file */
349 reg = <0x01c20800 0x400>;
350 /* interrupts get set in SoC specific dtsi file */
351 clocks = <&apb1_gates 5>;
352 gpio-controller;
353 interrupt-controller;
354 #interrupt-cells = <3>;
355 #gpio-cells = <3>;
357 uart0_pins_a: uart0@0 {
358 allwinner,pins = "PF2", "PF4";
359 allwinner,function = "uart0";
360 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
361 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
362 };
364 mmc0_pins_a: mmc0@0 {
365 allwinner,pins = "PF0", "PF1", "PF2",
366 "PF3", "PF4", "PF5";
367 allwinner,function = "mmc0";
368 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
369 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
370 };
372 mmc1_pins_a: mmc1@0 {
373 allwinner,pins = "PG0", "PG1", "PG2",
374 "PG3", "PG4", "PG5";
375 allwinner,function = "mmc1";
376 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
377 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
378 };
380 mmc2_8bit_pins: mmc2_8bit {
381 allwinner,pins = "PC5", "PC6", "PC8",
382 "PC9", "PC10", "PC11",
383 "PC12", "PC13", "PC14",
384 "PC15", "PC16";
385 allwinner,function = "mmc2";
386 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
387 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
388 };
390 pwm0_pins: pwm0 {
391 allwinner,pins = "PH0";
392 allwinner,function = "pwm0";
393 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
394 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
395 };
397 i2c0_pins_a: i2c0@0 {
398 allwinner,pins = "PH2", "PH3";
399 allwinner,function = "i2c0";
400 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
401 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
402 };
404 i2c1_pins_a: i2c1@0 {
405 allwinner,pins = "PH4", "PH5";
406 allwinner,function = "i2c1";
407 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
408 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
409 };
411 i2c2_pins_a: i2c2@0 {
412 allwinner,pins = "PE12", "PE13";
413 allwinner,function = "i2c2";
414 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
415 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
416 };
417 };
419 ahb1_rst: reset@01c202c0 {
420 #reset-cells = <1>;
421 compatible = "allwinner,sun6i-a31-clock-reset";
422 reg = <0x01c202c0 0xc>;
423 };
425 apb1_rst: reset@01c202d0 {
426 #reset-cells = <1>;
427 compatible = "allwinner,sun6i-a31-clock-reset";
428 reg = <0x01c202d0 0x4>;
429 };
431 apb2_rst: reset@01c202d8 {
432 #reset-cells = <1>;
433 compatible = "allwinner,sun6i-a31-clock-reset";
434 reg = <0x01c202d8 0x4>;
435 };
437 timer@01c20c00 {
438 compatible = "allwinner,sun4i-a10-timer";
439 reg = <0x01c20c00 0xa0>;
440 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&osc24M>;
443 };
445 wdt0: watchdog@01c20ca0 {
446 compatible = "allwinner,sun6i-a31-wdt";
447 reg = <0x01c20ca0 0x20>;
448 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
449 };
451 pwm: pwm@01c21400 {
452 compatible = "allwinner,sun7i-a20-pwm";
453 reg = <0x01c21400 0xc>;
454 clocks = <&osc24M>;
455 #pwm-cells = <3>;
456 status = "disabled";
457 };
459 lradc: lradc@01c22800 {
460 compatible = "allwinner,sun4i-a10-lradc-keys";
461 reg = <0x01c22800 0x100>;
462 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
463 status = "disabled";
464 };
466 uart0: serial@01c28000 {
467 compatible = "snps,dw-apb-uart";
468 reg = <0x01c28000 0x400>;
469 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
470 reg-shift = <2>;
471 reg-io-width = <4>;
472 clocks = <&apb2_gates 16>;
473 resets = <&apb2_rst 16>;
474 dmas = <&dma 6>, <&dma 6>;
475 dma-names = "rx", "tx";
476 status = "disabled";
477 };
479 uart1: serial@01c28400 {
480 compatible = "snps,dw-apb-uart";
481 reg = <0x01c28400 0x400>;
482 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
483 reg-shift = <2>;
484 reg-io-width = <4>;
485 clocks = <&apb2_gates 17>;
486 resets = <&apb2_rst 17>;
487 dmas = <&dma 7>, <&dma 7>;
488 dma-names = "rx", "tx";
489 status = "disabled";
490 };
492 uart2: serial@01c28800 {
493 compatible = "snps,dw-apb-uart";
494 reg = <0x01c28800 0x400>;
495 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
496 reg-shift = <2>;
497 reg-io-width = <4>;
498 clocks = <&apb2_gates 18>;
499 resets = <&apb2_rst 18>;
500 dmas = <&dma 8>, <&dma 8>;
501 dma-names = "rx", "tx";
502 status = "disabled";
503 };
505 uart3: serial@01c28c00 {
506 compatible = "snps,dw-apb-uart";
507 reg = <0x01c28c00 0x400>;
508 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
509 reg-shift = <2>;
510 reg-io-width = <4>;
511 clocks = <&apb2_gates 19>;
512 resets = <&apb2_rst 19>;
513 dmas = <&dma 9>, <&dma 9>;
514 dma-names = "rx", "tx";
515 status = "disabled";
516 };
518 uart4: serial@01c29000 {
519 compatible = "snps,dw-apb-uart";
520 reg = <0x01c29000 0x400>;
521 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
522 reg-shift = <2>;
523 reg-io-width = <4>;
524 clocks = <&apb2_gates 20>;
525 resets = <&apb2_rst 20>;
526 dmas = <&dma 10>, <&dma 10>;
527 dma-names = "rx", "tx";
528 status = "disabled";
529 };
531 i2c0: i2c@01c2ac00 {
532 compatible = "allwinner,sun6i-a31-i2c";
533 reg = <0x01c2ac00 0x400>;
534 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&apb2_gates 0>;
536 resets = <&apb2_rst 0>;
537 status = "disabled";
538 #address-cells = <1>;
539 #size-cells = <0>;
540 };
542 i2c1: i2c@01c2b000 {
543 compatible = "allwinner,sun6i-a31-i2c";
544 reg = <0x01c2b000 0x400>;
545 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&apb2_gates 1>;
547 resets = <&apb2_rst 1>;
548 status = "disabled";
549 #address-cells = <1>;
550 #size-cells = <0>;
551 };
553 i2c2: i2c@01c2b400 {
554 compatible = "allwinner,sun6i-a31-i2c";
555 reg = <0x01c2b400 0x400>;
556 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&apb2_gates 2>;
558 resets = <&apb2_rst 2>;
559 status = "disabled";
560 #address-cells = <1>;
561 #size-cells = <0>;
562 };
564 gic: interrupt-controller@01c81000 {
565 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
566 reg = <0x01c81000 0x1000>,
567 <0x01c82000 0x1000>,
568 <0x01c84000 0x2000>,
569 <0x01c86000 0x2000>;
570 interrupt-controller;
571 #interrupt-cells = <3>;
572 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
573 };
575 rtc: rtc@01f00000 {
576 compatible = "allwinner,sun6i-a31-rtc";
577 reg = <0x01f00000 0x54>;
578 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
580 };
582 nmi_intc: interrupt-controller@01f00c0c {
583 compatible = "allwinner,sun6i-a31-sc-nmi";
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 reg = <0x01f00c0c 0x38>;
587 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
588 };
590 prcm@01f01400 {
591 compatible = "allwinner,sun8i-a23-prcm";
592 reg = <0x01f01400 0x200>;
594 ar100: ar100_clk {
595 compatible = "fixed-factor-clock";
596 #clock-cells = <0>;
597 clock-div = <1>;
598 clock-mult = <1>;
599 clocks = <&osc24M>;
600 clock-output-names = "ar100";
601 };
603 ahb0: ahb0_clk {
604 compatible = "fixed-factor-clock";
605 #clock-cells = <0>;
606 clock-div = <1>;
607 clock-mult = <1>;
608 clocks = <&ar100>;
609 clock-output-names = "ahb0";
610 };
612 apb0: apb0_clk {
613 compatible = "allwinner,sun8i-a23-apb0-clk";
614 #clock-cells = <0>;
615 clocks = <&ahb0>;
616 clock-output-names = "apb0";
617 };
619 apb0_gates: apb0_gates_clk {
620 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
621 #clock-cells = <1>;
622 clocks = <&apb0>;
623 clock-output-names = "apb0_pio", "apb0_timer",
624 "apb0_rsb", "apb0_uart",
625 "apb0_i2c";
626 };
628 apb0_rst: apb0_rst {
629 compatible = "allwinner,sun6i-a31-clock-reset";
630 #reset-cells = <1>;
631 };
632 };
634 cpucfg@01f01c00 {
635 compatible = "allwinner,sun8i-a23-cpuconfig";
636 reg = <0x01f01c00 0x300>;
637 };
639 r_uart: serial@01f02800 {
640 compatible = "snps,dw-apb-uart";
641 reg = <0x01f02800 0x400>;
642 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
643 reg-shift = <2>;
644 reg-io-width = <4>;
645 clocks = <&apb0_gates 4>;
646 resets = <&apb0_rst 4>;
647 status = "disabled";
648 };
650 r_pio: pinctrl@01f02c00 {
651 compatible = "allwinner,sun8i-a23-r-pinctrl";
652 reg = <0x01f02c00 0x400>;
653 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&apb0_gates 0>;
655 resets = <&apb0_rst 0>;
656 gpio-controller;
657 interrupt-controller;
658 #interrupt-cells = <3>;
659 #address-cells = <1>;
660 #size-cells = <0>;
661 #gpio-cells = <3>;
663 r_rsb_pins: r_rsb {
664 allwinner,pins = "PL0", "PL1";
665 allwinner,function = "s_rsb";
666 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
667 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
668 };
670 r_uart_pins_a: r_uart@0 {
671 allwinner,pins = "PL2", "PL3";
672 allwinner,function = "s_uart";
673 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
674 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
675 };
676 };
678 r_rsb: rsb@01f03400 {
679 compatible = "allwinner,sun8i-a23-rsb";
680 reg = <0x01f03400 0x400>;
681 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&apb0_gates 3>;
683 clock-frequency = <3000000>;
684 resets = <&apb0_rst 3>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&r_rsb_pins>;
687 status = "disabled";
688 #address-cells = <1>;
689 #size-cells = <0>;
690 };
691 };
692 };