| blob | 8e0066ad9628e745fa167ff7047fb474c29d6dcb |
1 #include "tegra20.dtsi"
3 / {
4 model = "Toradex Colibri T20 512MB";
5 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
7 aliases {
8 rtc0 = "/i2c@7000d000/tps6586x@34";
9 rtc1 = "/rtc@7000e000";
10 };
12 memory {
13 reg = <0x00000000 0x20000000>;
14 };
16 host1x@50000000 {
17 hdmi@54280000 {
18 vdd-supply = <&hdmi_vdd_reg>;
19 pll-supply = <&hdmi_pll_reg>;
21 nvidia,ddc-i2c-bus = <&i2c_ddc>;
22 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 GPIO_ACTIVE_HIGH>;
24 };
25 };
27 pinmux@70000014 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
31 state_default: pinmux {
32 audio_refclk {
33 nvidia,pins = "cdev1";
34 nvidia,function = "plla_out";
35 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
36 nvidia,tristate = <TEGRA_PIN_DISABLE>;
37 };
38 crt {
39 nvidia,pins = "crtp";
40 nvidia,function = "crt";
41 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
42 nvidia,tristate = <TEGRA_PIN_ENABLE>;
43 };
44 dap3 {
45 nvidia,pins = "dap3";
46 nvidia,function = "dap3";
47 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
48 nvidia,tristate = <TEGRA_PIN_DISABLE>;
49 };
50 displaya {
51 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
52 "ld4", "ld5", "ld6", "ld7", "ld8",
53 "ld9", "ld10", "ld11", "ld12", "ld13",
54 "ld14", "ld15", "ld16", "ld17",
55 "lhs", "lpw0", "lpw2", "lsc0",
56 "lsc1", "lsck", "lsda", "lspi", "lvs";
57 nvidia,function = "displaya";
58 nvidia,tristate = <TEGRA_PIN_ENABLE>;
59 };
60 gpio_dte {
61 nvidia,pins = "dte";
62 nvidia,function = "rsvd1";
63 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
64 nvidia,tristate = <TEGRA_PIN_DISABLE>;
65 };
66 gpio_gmi {
67 nvidia,pins = "ata", "atc", "atd", "ate",
68 "dap1", "dap2", "dap4", "gpu", "irrx",
69 "irtx", "spia", "spib", "spic";
70 nvidia,function = "gmi";
71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
73 };
74 gpio_pta {
75 nvidia,pins = "pta";
76 nvidia,function = "rsvd4";
77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 };
80 gpio_uac {
81 nvidia,pins = "uac";
82 nvidia,function = "rsvd2";
83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 };
86 hdint {
87 nvidia,pins = "hdint";
88 nvidia,function = "hdmi";
89 nvidia,tristate = <TEGRA_PIN_ENABLE>;
90 };
91 i2c1 {
92 nvidia,pins = "rm";
93 nvidia,function = "i2c1";
94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_ENABLE>;
96 };
97 i2c3 {
98 nvidia,pins = "dtf";
99 nvidia,function = "i2c3";
100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
102 };
103 i2cddc {
104 nvidia,pins = "ddc";
105 nvidia,function = "i2c2";
106 nvidia,pull = <TEGRA_PIN_PULL_UP>;
107 nvidia,tristate = <TEGRA_PIN_ENABLE>;
108 };
109 i2cp {
110 nvidia,pins = "i2cp";
111 nvidia,function = "i2cp";
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 };
115 irda {
116 nvidia,pins = "uad";
117 nvidia,function = "irda";
118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
120 };
121 nand {
122 nvidia,pins = "kbca", "kbcc", "kbcd",
123 "kbce", "kbcf";
124 nvidia,function = "nand";
125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 };
128 owc {
129 nvidia,pins = "owc";
130 nvidia,function = "owr";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_ENABLE>;
133 };
134 pmc {
135 nvidia,pins = "pmc";
136 nvidia,function = "pwr_on";
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 };
139 pwm {
140 nvidia,pins = "sdb", "sdc", "sdd";
141 nvidia,function = "pwm";
142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
143 };
144 sdio4 {
145 nvidia,pins = "atb", "gma", "gme";
146 nvidia,function = "sdio4";
147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148 nvidia,tristate = <TEGRA_PIN_ENABLE>;
149 };
150 spi1 {
151 nvidia,pins = "spid", "spie", "spif";
152 nvidia,function = "spi1";
153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <TEGRA_PIN_ENABLE>;
155 };
156 spi4 {
157 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
158 nvidia,function = "spi4";
159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_ENABLE>;
161 };
162 uarta {
163 nvidia,pins = "sdio1";
164 nvidia,function = "uarta";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_ENABLE>;
167 };
168 uartd {
169 nvidia,pins = "gmc";
170 nvidia,function = "uartd";
171 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
172 nvidia,tristate = <TEGRA_PIN_ENABLE>;
173 };
174 ulpi {
175 nvidia,pins = "uaa", "uab", "uda";
176 nvidia,function = "ulpi";
177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
179 };
180 ulpi_refclk {
181 nvidia,pins = "cdev2";
182 nvidia,function = "pllp_out4";
183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
185 };
186 usb_gpio {
187 nvidia,pins = "spig", "spih";
188 nvidia,function = "spi2_alt";
189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
191 };
192 vi {
193 nvidia,pins = "dta", "dtb", "dtc", "dtd";
194 nvidia,function = "vi";
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
197 };
198 vi_sc {
199 nvidia,pins = "csus";
200 nvidia,function = "vi_sensor_clk";
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
203 };
204 };
205 };
207 ac97: ac97@70002000 {
208 status = "okay";
209 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
210 GPIO_ACTIVE_HIGH>;
211 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
212 GPIO_ACTIVE_HIGH>;
213 };
215 i2c@7000c000 {
216 clock-frequency = <400000>;
217 };
219 i2c_ddc: i2c@7000c400 {
220 clock-frequency = <100000>;
221 };
223 i2c@7000c500 {
224 clock-frequency = <400000>;
225 };
227 i2c@7000d000 {
228 status = "okay";
229 clock-frequency = <400000>;
231 pmic: tps6586x@34 {
232 compatible = "ti,tps6586x";
233 reg = <0x34>;
234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
236 ti,system-power-controller;
238 #gpio-cells = <2>;
239 gpio-controller;
241 sys-supply = <&vdd_3v3_reg>;
242 vin-sm0-supply = <&sys_reg>;
243 vin-sm1-supply = <&sys_reg>;
244 vin-sm2-supply = <&sys_reg>;
245 vinldo01-supply = <&sm2_reg>;
246 vinldo23-supply = <&vdd_3v3_reg>;
247 vinldo4-supply = <&vdd_3v3_reg>;
248 vinldo678-supply = <&vdd_3v3_reg>;
249 vinldo9-supply = <&vdd_3v3_reg>;
251 regulators {
252 #address-cells = <1>;
253 #size-cells = <0>;
255 sys_reg: regulator@0 {
256 reg = <0>;
257 regulator-compatible = "sys";
258 regulator-name = "vdd_sys";
259 regulator-always-on;
260 };
262 regulator@1 {
263 reg = <1>;
264 regulator-compatible = "sm0";
265 regulator-name = "vdd_sm0,vdd_core";
266 regulator-min-microvolt = <1200000>;
267 regulator-max-microvolt = <1200000>;
268 regulator-always-on;
269 };
271 regulator@2 {
272 reg = <2>;
273 regulator-compatible = "sm1";
274 regulator-name = "vdd_sm1,vdd_cpu";
275 regulator-min-microvolt = <1000000>;
276 regulator-max-microvolt = <1000000>;
277 regulator-always-on;
278 };
280 sm2_reg: regulator@3 {
281 reg = <3>;
282 regulator-compatible = "sm2";
283 regulator-name = "vdd_sm2,vin_ldo*";
284 regulator-min-microvolt = <1800000>;
285 regulator-max-microvolt = <1800000>;
286 regulator-always-on;
287 };
289 /* LDO0 is not connected to anything */
291 regulator@5 {
292 reg = <5>;
293 regulator-compatible = "ldo1";
294 regulator-name = "vdd_ldo1,avdd_pll*";
295 regulator-min-microvolt = <1100000>;
296 regulator-max-microvolt = <1100000>;
297 regulator-always-on;
298 };
300 regulator@6 {
301 reg = <6>;
302 regulator-compatible = "ldo2";
303 regulator-name = "vdd_ldo2,vdd_rtc";
304 regulator-min-microvolt = <1200000>;
305 regulator-max-microvolt = <1200000>;
306 };
308 /* LDO3 is not connected to anything */
310 regulator@8 {
311 reg = <8>;
312 regulator-compatible = "ldo4";
313 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
314 regulator-min-microvolt = <1800000>;
315 regulator-max-microvolt = <1800000>;
316 regulator-always-on;
317 };
319 ldo5_reg: regulator@9 {
320 reg = <9>;
321 regulator-compatible = "ldo5";
322 regulator-name = "vdd_ldo5,vdd_fuse";
323 regulator-min-microvolt = <3300000>;
324 regulator-max-microvolt = <3300000>;
325 regulator-always-on;
326 };
328 regulator@10 {
329 reg = <10>;
330 regulator-compatible = "ldo6";
331 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
332 regulator-min-microvolt = <2850000>;
333 regulator-max-microvolt = <2850000>;
334 };
336 hdmi_vdd_reg: regulator@11 {
337 reg = <11>;
338 regulator-compatible = "ldo7";
339 regulator-name = "vdd_ldo7,avdd_hdmi";
340 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>;
342 };
344 hdmi_pll_reg: regulator@12 {
345 reg = <12>;
346 regulator-compatible = "ldo8";
347 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
348 regulator-min-microvolt = <1800000>;
349 regulator-max-microvolt = <1800000>;
350 };
352 regulator@13 {
353 reg = <13>;
354 regulator-compatible = "ldo9";
355 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
356 regulator-min-microvolt = <2850000>;
357 regulator-max-microvolt = <2850000>;
358 regulator-always-on;
359 };
361 regulator@14 {
362 reg = <14>;
363 regulator-compatible = "ldo_rtc";
364 regulator-name = "vdd_rtc_out,vdd_cell";
365 regulator-min-microvolt = <3300000>;
366 regulator-max-microvolt = <3300000>;
367 regulator-always-on;
368 };
369 };
370 };
372 temperature-sensor@4c {
373 compatible = "national,lm95245";
374 reg = <0x4c>;
375 };
376 };
378 pmc@7000e400 {
379 nvidia,suspend-mode = <1>;
380 nvidia,cpu-pwr-good-time = <5000>;
381 nvidia,cpu-pwr-off-time = <5000>;
382 nvidia,core-pwr-good-time = <3845 3845>;
383 nvidia,core-pwr-off-time = <3875>;
384 nvidia,sys-clock-req-active-high;
385 };
387 memory-controller@7000f400 {
388 emc-table@83250 {
389 reg = <83250>;
390 compatible = "nvidia,tegra20-emc-table";
391 clock-frequency = <83250>;
392 nvidia,emc-registers = <0x00000005 0x00000011
393 0x00000004 0x00000002 0x00000004 0x00000004
394 0x00000001 0x0000000a 0x00000002 0x00000002
395 0x00000001 0x00000001 0x00000003 0x00000004
396 0x00000003 0x00000009 0x0000000c 0x0000025f
397 0x00000000 0x00000003 0x00000003 0x00000002
398 0x00000002 0x00000001 0x00000008 0x000000c8
399 0x00000003 0x00000005 0x00000003 0x0000000c
400 0x00000002 0x00000000 0x00000000 0x00000002
401 0x00000000 0x00000000 0x00000083 0x00520006
402 0x00000010 0x00000008 0x00000000 0x00000000
403 0x00000000 0x00000000 0x00000000 0x00000000>;
404 };
405 emc-table@133200 {
406 reg = <133200>;
407 compatible = "nvidia,tegra20-emc-table";
408 clock-frequency = <133200>;
409 nvidia,emc-registers = <0x00000008 0x00000019
410 0x00000006 0x00000002 0x00000004 0x00000004
411 0x00000001 0x0000000a 0x00000002 0x00000002
412 0x00000002 0x00000001 0x00000003 0x00000004
413 0x00000003 0x00000009 0x0000000c 0x0000039f
414 0x00000000 0x00000003 0x00000003 0x00000002
415 0x00000002 0x00000001 0x00000008 0x000000c8
416 0x00000003 0x00000007 0x00000003 0x0000000c
417 0x00000002 0x00000000 0x00000000 0x00000002
418 0x00000000 0x00000000 0x00000083 0x00510006
419 0x00000010 0x00000008 0x00000000 0x00000000
420 0x00000000 0x00000000 0x00000000 0x00000000>;
421 };
422 emc-table@166500 {
423 reg = <166500>;
424 compatible = "nvidia,tegra20-emc-table";
425 clock-frequency = <166500>;
426 nvidia,emc-registers = <0x0000000a 0x00000021
427 0x00000008 0x00000003 0x00000004 0x00000004
428 0x00000002 0x0000000a 0x00000003 0x00000003
429 0x00000002 0x00000001 0x00000003 0x00000004
430 0x00000003 0x00000009 0x0000000c 0x000004df
431 0x00000000 0x00000003 0x00000003 0x00000003
432 0x00000003 0x00000001 0x00000009 0x000000c8
433 0x00000003 0x00000009 0x00000004 0x0000000c
434 0x00000002 0x00000000 0x00000000 0x00000002
435 0x00000000 0x00000000 0x00000083 0x004f0006
436 0x00000010 0x00000008 0x00000000 0x00000000
437 0x00000000 0x00000000 0x00000000 0x00000000>;
438 };
439 emc-table@333000 {
440 reg = <333000>;
441 compatible = "nvidia,tegra20-emc-table";
442 clock-frequency = <333000>;
443 nvidia,emc-registers = <0x00000014 0x00000041
444 0x0000000f 0x00000005 0x00000004 0x00000005
445 0x00000003 0x0000000a 0x00000005 0x00000005
446 0x00000004 0x00000001 0x00000003 0x00000004
447 0x00000003 0x00000009 0x0000000c 0x000009ff
448 0x00000000 0x00000003 0x00000003 0x00000005
449 0x00000005 0x00000001 0x0000000e 0x000000c8
450 0x00000003 0x00000011 0x00000006 0x0000000c
451 0x00000002 0x00000000 0x00000000 0x00000002
452 0x00000000 0x00000000 0x00000083 0x00380006
453 0x00000010 0x00000008 0x00000000 0x00000000
454 0x00000000 0x00000000 0x00000000 0x00000000>;
455 };
456 };
458 usb@c5004000 {
459 status = "okay";
460 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
461 GPIO_ACTIVE_LOW>;
462 };
464 usb-phy@c5004000 {
465 status = "okay";
466 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
467 GPIO_ACTIVE_LOW>;
468 };
470 sdhci@c8000600 {
471 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
472 };
474 clocks {
475 compatible = "simple-bus";
476 #address-cells = <1>;
477 #size-cells = <0>;
479 clk32k_in: clock@0 {
480 compatible = "fixed-clock";
481 reg=<0>;
482 #clock-cells = <0>;
483 clock-frequency = <32768>;
484 };
485 };
487 regulators {
488 compatible = "simple-bus";
489 #address-cells = <1>;
490 #size-cells = <0>;
492 vdd_3v3_reg: regulator@100 {
493 compatible = "regulator-fixed";
494 reg = <100>;
495 regulator-name = "vdd_3v3";
496 regulator-min-microvolt = <3300000>;
497 regulator-max-microvolt = <3300000>;
498 regulator-always-on;
499 };
501 regulator@101 {
502 compatible = "regulator-fixed";
503 reg = <101>;
504 regulator-name = "internal_usb";
505 regulator-min-microvolt = <5000000>;
506 regulator-max-microvolt = <5000000>;
507 enable-active-high;
508 regulator-boot-on;
509 regulator-always-on;
510 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
511 };
512 };
514 sound {
515 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
516 "nvidia,tegra-audio-wm9712";
517 nvidia,model = "Colibri T20 AC97 Audio";
519 nvidia,audio-routing =
520 "Headphone", "HPOUTL",
521 "Headphone", "HPOUTR",
522 "LineIn", "LINEINL",
523 "LineIn", "LINEINR",
524 "Mic", "MIC1";
526 nvidia,ac97-controller = <&ac97>;
528 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
529 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
530 <&tegra_car TEGRA20_CLK_CDEV1>;
531 clock-names = "pll_a", "pll_a_out0", "mclk";
532 };
533 };