drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58 #include "mlx4_stats.h"
  59
  60 #define DRV_NAME        "mlx4_en"
  61 #define DRV_VERSION     "2.2-1"
  62 #define DRV_RELDATE     "Feb 2014"
  63
  64 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  65
  66 /*
  67  * Device constants
  68  */
  69
  70
  71 #define MLX4_EN_PAGE_SHIFT      12
  72 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  73 #define DEF_RX_RINGS            16
  74 #define MAX_RX_RINGS            128
  75 #define MIN_RX_RINGS            4
  76 #define TXBB_SIZE               64
  77 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  78 #define STAMP_STRIDE            64
  79 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  80 #define STAMP_SHIFT             31
  81 #define STAMP_VAL               0x7fffffff
  82 #define STATS_DELAY             (HZ / 4)
  83 #define SERVICE_TASK_DELAY      (HZ / 4)
  84 #define MAX_NUM_OF_FS_RULES     256
  85
  86 #define MLX4_EN_FILTER_HASH_SHIFT 4
  87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  88
  89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  90 #define MAX_DESC_SIZE           512
  91 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  92
  93 /*
  94  * OS related constants and tunables
  95  */
  96
  97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
  98 #define MLX4_EN_PRIV_FLAGS_PHV       2
  99
 100 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 101
 102 /* Use the maximum between 16384 and a single page */
 103 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 104
 105 #define MLX4_EN_ALLOC_PREFER_ORDER      PAGE_ALLOC_COSTLY_ORDER
 106
 107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
 108  * and 4K allocations) */
 109 enum {
 110         FRAG_SZ0 = 1536 - NET_IP_ALIGN,
 111         FRAG_SZ1 = 4096,
 112         FRAG_SZ2 = 4096,
 113         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 114 };
 115 #define MLX4_EN_MAX_RX_FRAGS    4
 116
 117 /* Maximum ring sizes */
 118 #define MLX4_EN_MAX_TX_SIZE     8192
 119 #define MLX4_EN_MAX_RX_SIZE     8192
 120
 121 /* Minimum ring size for our page-allocation scheme to work */
 122 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 123 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 124
 125 #define MLX4_EN_SMALL_PKT_SIZE          64
 126 #define MLX4_EN_MIN_TX_RING_P_UP        1
 127 #define MLX4_EN_MAX_TX_RING_P_UP        32
 128 #define MLX4_EN_NUM_UP                  8
 129 #define MLX4_EN_DEF_TX_RING_SIZE        512
 130 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 131 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 132                                          MLX4_EN_NUM_UP)
 133
 134 #define MLX4_EN_DEFAULT_TX_WORK         256
 135
 136 /* Target number of packets to coalesce with interrupt moderation */
 137 #define MLX4_EN_RX_COAL_TARGET  44
 138 #define MLX4_EN_RX_COAL_TIME    0x10
 139
 140 #define MLX4_EN_TX_COAL_PKTS    16
 141 #define MLX4_EN_TX_COAL_TIME    0x10
 142
 143 #define MLX4_EN_RX_RATE_LOW             400000
 144 #define MLX4_EN_RX_COAL_TIME_LOW        0
 145 #define MLX4_EN_RX_RATE_HIGH            450000
 146 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 147 #define MLX4_EN_RX_SIZE_THRESH          1024
 148 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 149 #define MLX4_EN_SAMPLE_INTERVAL         0
 150 #define MLX4_EN_AVG_PKT_SMALL           256
 151
 152 #define MLX4_EN_AUTO_CONF       0xffff
 153
 154 #define MLX4_EN_DEF_RX_PAUSE    1
 155 #define MLX4_EN_DEF_TX_PAUSE    1
 156
 157 /* Interval between successive polls in the Tx routine when polling is used
 158    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 159 #define MLX4_EN_TX_POLL_MODER   16
 160 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 161
 162 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 163 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 164 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 165
 166 #define MLX4_EN_MIN_MTU         46
 167 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
 168  * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
 169  */
 170 #define MLX4_EN_EFF_MTU(mtu)    ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
 171 #define ETH_BCAST               0xffffffffffffULL
 172
 173 #define MLX4_EN_LOOPBACK_RETRIES        5
 174 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 175
 176 #ifdef MLX4_EN_PERF_STAT
 177 /* Number of samples to 'average' */
 178 #define AVG_SIZE                        128
 179 #define AVG_FACTOR                      1024
 180
 181 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 182 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 183 #define AVG_PERF_COUNTER(cnt, sample) \
 184         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 185 #define GET_PERF_COUNTER(cnt)           (cnt)
 186 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 187
 188 #else
 189
 190 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 191 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 192 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 193 #define GET_PERF_COUNTER(cnt)           (0)
 194 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 195 #endif /* MLX4_EN_PERF_STAT */
 196
 197 /* Constants for TX flow */
 198 enum {
 199         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 200         MAX_BF = 256,
 201         MIN_PKT_LEN = 17,
 202 };
 203
 204 /*
 205  * Configurables
 206  */
 207
 208 enum cq_type {
 209         RX = 0,
 210         TX = 1,
 211 };
 212
 213
 214 /*
 215  * Useful macros
 216  */
 217 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 218 #define XNOR(x, y)              (!(x) == !(y))
 219
 220
 221 struct mlx4_en_tx_info {
 222         struct sk_buff *skb;
 223         dma_addr_t      map0_dma;
 224         u32             map0_byte_count;
 225         u32             nr_txbb;
 226         u32             nr_bytes;
 227         u8              linear;
 228         u8              data_offset;
 229         u8              inl;
 230         u8              ts_requested;
 231         u8              nr_maps;
 232 } ____cacheline_aligned_in_smp;
 233
 234
 235 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 236 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 237 #define MLX4_EN_MEMTYPE_PAD     0x100
 238 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 239
 240
 241 struct mlx4_en_tx_desc {
 242         struct mlx4_wqe_ctrl_seg ctrl;
 243         union {
 244                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 245                 struct mlx4_wqe_lso_seg lso;
 246                 struct mlx4_wqe_inline_seg inl;
 247         };
 248 };
 249
 250 #define MLX4_EN_USE_SRQ         0x01000000
 251
 252 #define MLX4_EN_CX3_LOW_ID      0x1000
 253 #define MLX4_EN_CX3_HIGH_ID     0x1005
 254
 255 struct mlx4_en_rx_alloc {
 256         struct page     *page;
 257         dma_addr_t      dma;
 258         u32             page_offset;
 259         u32             page_size;
 260 };
 261
 262 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
 263 struct mlx4_en_page_cache {
 264         u32 index;
 265         struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE];
 266 };
 267
 268 struct mlx4_en_tx_ring {
 269         /* cache line used and dirtied in tx completion
 270          * (mlx4_en_free_tx_buf())
 271          */
 272         u32                     last_nr_txbb;
 273         u32                     cons;
 274         unsigned long           wake_queue;
 275
 276         /* cache line used and dirtied in mlx4_en_xmit() */
 277         u32                     prod ____cacheline_aligned_in_smp;
 278         unsigned long           bytes;
 279         unsigned long           packets;
 280         unsigned long           tx_csum;
 281         unsigned long           tso_packets;
 282         unsigned long           xmit_more;
 283         unsigned int            tx_dropped;
 284         struct mlx4_bf          bf;
 285         unsigned long           queue_stopped;
 286
 287         /* Following part should be mostly read */
 288         cpumask_t               affinity_mask;
 289         struct mlx4_qp          qp;
 290         struct mlx4_hwq_resources wqres;
 291         u32                     size; /* number of TXBBs */
 292         u32                     size_mask;
 293         u16                     stride;
 294         u32                     full_size;
 295         u16                     cqn;    /* index of port CQ associated with this ring */
 296         u32                     buf_size;
 297         __be32                  doorbell_qpn;
 298         __be32                  mr_key;
 299         void                    *buf;
 300         struct mlx4_en_tx_info  *tx_info;
 301         u8                      *bounce_buf;
 302         struct mlx4_qp_context  context;
 303         int                     qpn;
 304         enum mlx4_qp_state      qp_state;
 305         u8                      queue_index;
 306         bool                    bf_enabled;
 307         bool                    bf_alloced;
 308         struct netdev_queue     *tx_queue;
 309         int                     hwtstamp_tx_type;
 310 } ____cacheline_aligned_in_smp;
 311
 312 struct mlx4_en_rx_desc {
 313         /* actual number of entries depends on rx ring stride */
 314         struct mlx4_wqe_data_seg data[0];
 315 };
 316
 317 struct mlx4_en_rx_ring {
 318         struct mlx4_hwq_resources wqres;
 319         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 320         u32 size ;      /* number of Rx descs*/
 321         u32 actual_size;
 322         u32 size_mask;
 323         u16 stride;
 324         u16 log_stride;
 325         u16 cqn;        /* index of port CQ associated with this ring */
 326         u32 prod;
 327         u32 cons;
 328         u32 buf_size;
 329         u8  fcs_del;
 330         void *buf;
 331         void *rx_info;
 332         struct bpf_prog *xdp_prog;
 333         struct mlx4_en_page_cache page_cache;
 334         unsigned long bytes;
 335         unsigned long packets;
 336         unsigned long csum_ok;
 337         unsigned long csum_none;
 338         unsigned long csum_complete;
 339         unsigned long dropped;
 340         int hwtstamp_rx_filter;
 341         cpumask_var_t affinity_mask;
 342 };
 343
 344 struct mlx4_en_cq {
 345         struct mlx4_cq          mcq;
 346         struct mlx4_hwq_resources wqres;
 347         int                     ring;
 348         struct net_device      *dev;
 349         struct napi_struct      napi;
 350         int size;
 351         int buf_size;
 352         int vector;
 353         enum cq_type is_tx;
 354         u16 moder_time;
 355         u16 moder_cnt;
 356         struct mlx4_cqe *buf;
 357 #define MLX4_EN_OPCODE_ERROR    0x1e
 358
 359         struct irq_desc *irq_desc;
 360 };
 361
 362 struct mlx4_en_port_profile {
 363         u32 flags;
 364         u32 tx_ring_num;
 365         u32 rx_ring_num;
 366         u32 tx_ring_size;
 367         u32 rx_ring_size;
 368         u8 rx_pause;
 369         u8 rx_ppp;
 370         u8 tx_pause;
 371         u8 tx_ppp;
 372         int rss_rings;
 373         int inline_thold;
 374 };
 375
 376 struct mlx4_en_profile {
 377         int udp_rss;
 378         u8 rss_mask;
 379         u32 active_ports;
 380         u32 small_pkt_int;
 381         u8 no_reset;
 382         u8 num_tx_rings_p_up;
 383         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 384 };
 385
 386 struct mlx4_en_dev {
 387         struct mlx4_dev         *dev;
 388         struct pci_dev          *pdev;
 389         struct mutex            state_lock;
 390         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 391         struct net_device       *upper[MLX4_MAX_PORTS + 1];
 392         u32                     port_cnt;
 393         bool                    device_up;
 394         struct mlx4_en_profile  profile;
 395         u32                     LSO_support;
 396         struct workqueue_struct *workqueue;
 397         struct device           *dma_device;
 398         void __iomem            *uar_map;
 399         struct mlx4_uar         priv_uar;
 400         struct mlx4_mr          mr;
 401         u32                     priv_pdn;
 402         spinlock_t              uar_lock;
 403         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 404         rwlock_t                clock_lock;
 405         u32                     nominal_c_mult;
 406         struct cyclecounter     cycles;
 407         struct timecounter      clock;
 408         unsigned long           last_overflow_check;
 409         unsigned long           overflow_period;
 410         struct ptp_clock        *ptp_clock;
 411         struct ptp_clock_info   ptp_clock_info;
 412         struct notifier_block   nb;
 413 };
 414
 415
 416 struct mlx4_en_rss_map {
 417         int base_qpn;
 418         struct mlx4_qp qps[MAX_RX_RINGS];
 419         enum mlx4_qp_state state[MAX_RX_RINGS];
 420         struct mlx4_qp indir_qp;
 421         enum mlx4_qp_state indir_state;
 422 };
 423
 424 enum mlx4_en_port_flag {
 425         MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
 426         MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
 427 };
 428
 429 struct mlx4_en_port_state {
 430         int link_state;
 431         int link_speed;
 432         int transceiver;
 433         u32 flags;
 434 };
 435
 436 enum mlx4_en_mclist_act {
 437         MCLIST_NONE,
 438         MCLIST_REM,
 439         MCLIST_ADD,
 440 };
 441
 442 struct mlx4_en_mc_list {
 443         struct list_head        list;
 444         enum mlx4_en_mclist_act action;
 445         u8                      addr[ETH_ALEN];
 446         u64                     reg_id;
 447         u64                     tunnel_reg_id;
 448 };
 449
 450 struct mlx4_en_frag_info {
 451         u16 frag_size;
 452         u16 frag_prefix_size;
 453         u32 frag_stride;
 454         enum dma_data_direction dma_dir;
 455         int order;
 456 };
 457
 458 #ifdef CONFIG_MLX4_EN_DCB
 459 /* Minimal TC BW - setting to 0 will block traffic */
 460 #define MLX4_EN_BW_MIN 1
 461 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 462
 463 #define MLX4_EN_TC_ETS 7
 464
 465 enum dcb_pfc_type {
 466         pfc_disabled = 0,
 467         pfc_enabled_full,
 468         pfc_enabled_tx,
 469         pfc_enabled_rx
 470 };
 471
 472 struct tc_configuration {
 473         enum dcb_pfc_type  dcb_pfc;
 474 };
 475
 476 struct mlx4_en_cee_config {
 477         bool    pfc_state;
 478         struct  tc_configuration tc_config[MLX4_EN_NUM_UP];
 479 };
 480
 481 struct mlx4_en_cee_params {
 482         u8 dcbx_cap;
 483         struct mlx4_en_cee_config dcb_cfg;
 484 };
 485
 486 #endif
 487
 488 struct ethtool_flow_id {
 489         struct list_head list;
 490         struct ethtool_rx_flow_spec flow_spec;
 491         u64 id;
 492 };
 493
 494 enum {
 495         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 496         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 497         /* whether we need to enable hardware loopback by putting dmac
 498          * in Tx WQE
 499          */
 500         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 501         /* whether we need to drop packets that hardware loopback-ed */
 502         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 503         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4),
 504         MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP        = (1 << 5),
 505 #ifdef CONFIG_MLX4_EN_DCB
 506         MLX4_EN_FLAG_DCB_ENABLED        = (1 << 6),
 507 #endif
 508 };
 509
 510 #define PORT_BEACON_MAX_LIMIT (65535)
 511 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 512 #define MLX4_EN_MAC_HASH_IDX 5
 513
 514 struct mlx4_en_stats_bitmap {
 515         DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
 516         struct mutex mutex; /* for mutual access to stats bitmap */
 517 };
 518
 519 struct mlx4_en_priv {
 520         struct mlx4_en_dev *mdev;
 521         struct mlx4_en_port_profile *prof;
 522         struct net_device *dev;
 523         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 524         struct mlx4_en_port_state port_state;
 525         spinlock_t stats_lock;
 526         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 527         /* To allow rules removal while port is going down */
 528         struct list_head ethtool_list;
 529
 530         unsigned long last_moder_packets[MAX_RX_RINGS];
 531         unsigned long last_moder_tx_packets;
 532         unsigned long last_moder_bytes[MAX_RX_RINGS];
 533         unsigned long last_moder_jiffies;
 534         int last_moder_time[MAX_RX_RINGS];
 535         u16 rx_usecs;
 536         u16 rx_frames;
 537         u16 tx_usecs;
 538         u16 tx_frames;
 539         u32 pkt_rate_low;
 540         u16 rx_usecs_low;
 541         u32 pkt_rate_high;
 542         u16 rx_usecs_high;
 543         u16 sample_interval;
 544         u16 adaptive_rx_coal;
 545         u32 msg_enable;
 546         u32 loopback_ok;
 547         u32 validate_loopback;
 548
 549         struct mlx4_hwq_resources res;
 550         int link_state;
 551         int last_link_state;
 552         bool port_up;
 553         int port;
 554         int registered;
 555         int allocated;
 556         int stride;
 557         unsigned char current_mac[ETH_ALEN + 2];
 558         int mac_index;
 559         unsigned max_mtu;
 560         int base_qpn;
 561         int cqe_factor;
 562         int cqe_size;
 563
 564         struct mlx4_en_rss_map rss_map;
 565         __be32 ctrl_flags;
 566         u32 flags;
 567         u8 num_tx_rings_p_up;
 568         u32 tx_work_limit;
 569         u32 tx_ring_num;
 570         u32 rx_ring_num;
 571         u32 rx_skb_size;
 572         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 573         u16 num_frags;
 574         u16 log_rx_info;
 575         int xdp_ring_num;
 576
 577         struct mlx4_en_tx_ring **tx_ring;
 578         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 579         struct mlx4_en_cq **tx_cq;
 580         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 581         struct mlx4_qp drop_qp;
 582         struct work_struct rx_mode_task;
 583         struct work_struct watchdog_task;
 584         struct work_struct linkstate_task;
 585         struct delayed_work stats_task;
 586         struct delayed_work service_task;
 587         struct work_struct vxlan_add_task;
 588         struct work_struct vxlan_del_task;
 589         struct mlx4_en_perf_stats pstats;
 590         struct mlx4_en_pkt_stats pkstats;
 591         struct mlx4_en_counter_stats pf_stats;
 592         struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
 593         struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
 594         struct mlx4_en_flow_stats_rx rx_flowstats;
 595         struct mlx4_en_flow_stats_tx tx_flowstats;
 596         struct mlx4_en_port_stats port_stats;
 597         struct mlx4_en_stats_bitmap stats_bitmap;
 598         struct list_head mc_list;
 599         struct list_head curr_list;
 600         u64 broadcast_id;
 601         struct mlx4_en_stat_out_mbox hw_stats;
 602         int vids[128];
 603         bool wol;
 604         struct device *ddev;
 605         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 606         struct hwtstamp_config hwtstamp_config;
 607         u32 counter_index;
 608
 609 #ifdef CONFIG_MLX4_EN_DCB
 610 #define MLX4_EN_DCB_ENABLED     0x3
 611         struct ieee_ets ets;
 612         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 613         enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
 614         struct mlx4_en_cee_params cee_params;
 615 #endif
 616 #ifdef CONFIG_RFS_ACCEL
 617         spinlock_t filters_lock;
 618         int last_filter_id;
 619         struct list_head filters;
 620         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 621 #endif
 622         u64 tunnel_reg_id;
 623         __be16 vxlan_port;
 624
 625         u32 pflags;
 626         u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
 627         u8 rss_hash_fn;
 628 };
 629
 630 enum mlx4_en_wol {
 631         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 632         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 633 };
 634
 635 struct mlx4_mac_entry {
 636         struct hlist_node hlist;
 637         unsigned char mac[ETH_ALEN + 2];
 638         u64 reg_id;
 639         struct rcu_head rcu;
 640 };
 641
 642 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
 643 {
 644         return buf + idx * cqe_sz;
 645 }
 646
 647 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 648
 649 void mlx4_en_init_ptys2ethtool_map(void);
 650 void mlx4_en_update_loopback_state(struct net_device *dev,
 651                                    netdev_features_t features);
 652
 653 void mlx4_en_destroy_netdev(struct net_device *dev);
 654 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 655                         struct mlx4_en_port_profile *prof);
 656
 657 int mlx4_en_start_port(struct net_device *dev);
 658 void mlx4_en_stop_port(struct net_device *dev, int detach);
 659
 660 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
 661                               struct mlx4_en_stats_bitmap *stats_bitmap,
 662                               u8 rx_ppp, u8 rx_pause,
 663                               u8 tx_ppp, u8 tx_pause);
 664
 665 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 666 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 667
 668 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 669                       int entries, int ring, enum cq_type mode, int node);
 670 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 671 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 672                         int cq_idx);
 673 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 674 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 675 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 676
 677 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 678 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 679                          void *accel_priv, select_queue_fallback_t fallback);
 680 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 681
 682 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 683                            struct mlx4_en_tx_ring **pring,
 684                            u32 size, u16 stride,
 685                            int node, int queue_index);
 686 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 687                              struct mlx4_en_tx_ring **pring);
 688 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 689                              struct mlx4_en_tx_ring *ring,
 690                              int cq, int user_prio);
 691 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 692                                 struct mlx4_en_tx_ring *ring);
 693 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 694 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
 695 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 696                            struct mlx4_en_rx_ring **pring,
 697                            u32 size, u16 stride, int node);
 698 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 699                              struct mlx4_en_rx_ring **pring,
 700                              u32 size, u16 stride);
 701 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 702 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 703                                 struct mlx4_en_rx_ring *ring);
 704 int mlx4_en_process_rx_cq(struct net_device *dev,
 705                           struct mlx4_en_cq *cq,
 706                           int budget);
 707 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 708 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 709 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 710                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 711                 struct mlx4_qp_context *context);
 712 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 713 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
 714                             int loopback);
 715 void mlx4_en_calc_rx_buf(struct net_device *dev);
 716 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 717 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 718 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 719 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 720 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 721 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 722
 723 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 724 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 725
 726 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 727 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 728
 729 #ifdef CONFIG_MLX4_EN_DCB
 730 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 731 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 732 #endif
 733
 734 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 735
 736 #ifdef CONFIG_RFS_ACCEL
 737 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 738 #endif
 739
 740 #define MLX4_EN_NUM_SELF_TEST   5
 741 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 742 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 743
 744 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
 745         ((dev->features & feature) ^ (new_features & feature))
 746
 747 int mlx4_en_reset_config(struct net_device *dev,
 748                          struct hwtstamp_config ts_config,
 749                          netdev_features_t new_features);
 750 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
 751                                      struct mlx4_en_stats_bitmap *stats_bitmap,
 752                                      u8 rx_ppp, u8 rx_pause,
 753                                      u8 tx_ppp, u8 tx_pause);
 754 int mlx4_en_netdev_event(struct notifier_block *this,
 755                          unsigned long event, void *ptr);
 756
 757 /*
 758  * Functions for time stamping
 759  */
 760 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 761 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 762                             struct skb_shared_hwtstamps *hwts,
 763                             u64 timestamp);
 764 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 765 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 766
 767 /* Globals
 768  */
 769 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 770
 771
 772
 773 /*
 774  * printk / logging functions
 775  */
 776
 777 __printf(3, 4)
 778 void en_print(const char *level, const struct mlx4_en_priv *priv,
 779               const char *format, ...);
 780
 781 #define en_dbg(mlevel, priv, format, ...)                               \
 782 do {                                                                    \
 783         if (NETIF_MSG_##mlevel & (priv)->msg_enable)                    \
 784                 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);      \
 785 } while (0)
 786 #define en_warn(priv, format, ...)                                      \
 787         en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
 788 #define en_err(priv, format, ...)                                       \
 789         en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
 790 #define en_info(priv, format, ...)                                      \
 791         en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
 792
 793 #define mlx4_err(mdev, format, ...)                                     \
 794         pr_err(DRV_NAME " %s: " format,                                 \
 795                dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 796 #define mlx4_info(mdev, format, ...)                                    \
 797         pr_info(DRV_NAME " %s: " format,                                \
 798                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 799 #define mlx4_warn(mdev, format, ...)                                    \
 800         pr_warn(DRV_NAME " %s: " format,                                \
 801                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 802
 803 #endif