?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dm: Call proper helper to determine dax support
[linux/fpc-iii.git] / drivers / media / i2c / ov6650.c
blobaf482620f94a69b334121a8fed6c538a20775774
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
4 *
5 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
6 *
7 * Based on OmniVision OV96xx Camera Driver
8 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
9 *
10 * Based on ov772x camera driver:
11 * Copyright (C) 2008 Renesas Solutions Corp.
12 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
13 *
14 * Based on ov7670 and soc_camera_platform driver,
15 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
16 * Copyright (C) 2008 Magnus Damm
17 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
18 *
19 * Hardware specific bits initially based on former work by Matt Callow
20 * drivers/media/video/omap/sensor_ov6650.c
21 * Copyright (C) 2006 Matt Callow
22 */
23
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
28 #include <linux/v4l2-mediabus.h>
29 #include <linux/module.h>
30
31 #include <media/v4l2-clk.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-device.h>
34
35 /* Register definitions */
36 #define REG_GAIN 0x00 /* range 00 - 3F */
37 #define REG_BLUE 0x01
38 #define REG_RED 0x02
39 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
40 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
41
42 #define REG_BRT 0x06
43
44 #define REG_PIDH 0x0a
45 #define REG_PIDL 0x0b
46
47 #define REG_AECH 0x10
48 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
49 /* [7:6] Input system clock (MHz)*/
50 /* 00=8, 01=12, 10=16, 11=24 */
51 /* [5:0]: Internal Clock Pre-Scaler */
52 #define REG_COMA 0x12 /* [7] Reset */
53 #define REG_COMB 0x13
54 #define REG_COMC 0x14
55 #define REG_COMD 0x15
56 #define REG_COML 0x16
57 #define REG_HSTRT 0x17
58 #define REG_HSTOP 0x18
59 #define REG_VSTRT 0x19
60 #define REG_VSTOP 0x1a
61 #define REG_PSHFT 0x1b
62 #define REG_MIDH 0x1c
63 #define REG_MIDL 0x1d
64 #define REG_HSYNS 0x1e
65 #define REG_HSYNE 0x1f
66 #define REG_COME 0x20
67 #define REG_YOFF 0x21
68 #define REG_UOFF 0x22
69 #define REG_VOFF 0x23
70 #define REG_AEW 0x24
71 #define REG_AEB 0x25
72 #define REG_COMF 0x26
73 #define REG_COMG 0x27
74 #define REG_COMH 0x28
75 #define REG_COMI 0x29
76
77 #define REG_FRARL 0x2b
78 #define REG_COMJ 0x2c
79 #define REG_COMK 0x2d
80 #define REG_AVGY 0x2e
81 #define REG_REF0 0x2f
82 #define REG_REF1 0x30
83 #define REG_REF2 0x31
84 #define REG_FRAJH 0x32
85 #define REG_FRAJL 0x33
86 #define REG_FACT 0x34
87 #define REG_L1AEC 0x35
88 #define REG_AVGU 0x36
89 #define REG_AVGV 0x37
90
91 #define REG_SPCB 0x60
92 #define REG_SPCC 0x61
93 #define REG_GAM1 0x62
94 #define REG_GAM2 0x63
95 #define REG_GAM3 0x64
96 #define REG_SPCD 0x65
97
98 #define REG_SPCE 0x68
99 #define REG_ADCL 0x69
100
101 #define REG_RMCO 0x6c
102 #define REG_GMCO 0x6d
103 #define REG_BMCO 0x6e
104
105
106 /* Register bits, values, etc. */
107 #define OV6650_PIDH 0x66 /* high byte of product ID number */
108 #define OV6650_PIDL 0x50 /* low byte of product ID number */
109 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
110 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
111
112 #define DEF_GAIN 0x00
113 #define DEF_BLUE 0x80
114 #define DEF_RED 0x80
115
116 #define SAT_SHIFT 4
117 #define SAT_MASK (0xf << SAT_SHIFT)
118 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
119
120 #define HUE_EN BIT(5)
121 #define HUE_MASK 0x1f
122 #define DEF_HUE 0x10
123 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
124
125 #define DEF_AECH 0x4D
126
127 #define CLKRC_6MHz 0x00
128 #define CLKRC_12MHz 0x40
129 #define CLKRC_16MHz 0x80
130 #define CLKRC_24MHz 0xc0
131 #define CLKRC_DIV_MASK 0x3f
132 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
133 #define DEF_CLKRC 0x00
134
135 #define COMA_RESET BIT(7)
136 #define COMA_QCIF BIT(5)
137 #define COMA_RAW_RGB BIT(4)
138 #define COMA_RGB BIT(3)
139 #define COMA_BW BIT(2)
140 #define COMA_WORD_SWAP BIT(1)
141 #define COMA_BYTE_SWAP BIT(0)
142 #define DEF_COMA 0x00
143
144 #define COMB_FLIP_V BIT(7)
145 #define COMB_FLIP_H BIT(5)
146 #define COMB_BAND_FILTER BIT(4)
147 #define COMB_AWB BIT(2)
148 #define COMB_AGC BIT(1)
149 #define COMB_AEC BIT(0)
150 #define DEF_COMB 0x5f
151
152 #define COML_ONE_CHANNEL BIT(7)
153
154 #define DEF_HSTRT 0x24
155 #define DEF_HSTOP 0xd4
156 #define DEF_VSTRT 0x04
157 #define DEF_VSTOP 0x94
158
159 #define COMF_HREF_LOW BIT(4)
160
161 #define COMJ_PCLK_RISING BIT(4)
162 #define COMJ_VSYNC_HIGH BIT(0)
163
164 /* supported resolutions */
165 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
166 #define W_CIF (W_QCIF << 1)
167 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
168 #define H_CIF (H_QCIF << 1)
169
170 #define FRAME_RATE_MAX 30
171
172
173 struct ov6650_reg {
174 u8 reg;
175 u8 val;
176 };
177
178 struct ov6650 {
179 struct v4l2_subdev subdev;
180 struct v4l2_ctrl_handler hdl;
181 struct {
182 /* exposure/autoexposure cluster */
183 struct v4l2_ctrl *autoexposure;
184 struct v4l2_ctrl *exposure;
185 };
186 struct {
187 /* gain/autogain cluster */
188 struct v4l2_ctrl *autogain;
189 struct v4l2_ctrl *gain;
190 };
191 struct {
192 /* blue/red/autowhitebalance cluster */
193 struct v4l2_ctrl *autowb;
194 struct v4l2_ctrl *blue;
195 struct v4l2_ctrl *red;
196 };
197 struct v4l2_clk *clk;
198 bool half_scale; /* scale down output by 2 */
199 struct v4l2_rect rect; /* sensor cropping window */
200 unsigned long pclk_limit; /* from host */
201 unsigned long pclk_max; /* from resolution and format */
202 struct v4l2_fract tpf; /* as requested with s_frame_interval */
203 u32 code;
204 };
205
206
207 static u32 ov6650_codes[] = {
208 MEDIA_BUS_FMT_YUYV8_2X8,
209 MEDIA_BUS_FMT_UYVY8_2X8,
210 MEDIA_BUS_FMT_YVYU8_2X8,
211 MEDIA_BUS_FMT_VYUY8_2X8,
212 MEDIA_BUS_FMT_SBGGR8_1X8,
213 MEDIA_BUS_FMT_Y8_1X8,
214 };
215
216 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
217 .width = W_CIF,
218 .height = H_CIF,
219 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
220 .colorspace = V4L2_COLORSPACE_SRGB,
221 .field = V4L2_FIELD_NONE,
222 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
223 .quantization = V4L2_QUANTIZATION_DEFAULT,
224 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
225 };
226
227 /* read a register */
228 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
229 {
230 int ret;
231 u8 data = reg;
232 struct i2c_msg msg = {
233 .addr = client->addr,
234 .flags = 0,
235 .len = 1,
236 .buf = &data,
237 };
238
239 ret = i2c_transfer(client->adapter, &msg, 1);
240 if (ret < 0)
241 goto err;
242
243 msg.flags = I2C_M_RD;
244 ret = i2c_transfer(client->adapter, &msg, 1);
245 if (ret < 0)
246 goto err;
247
248 *val = data;
249 return 0;
250
251 err:
252 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
253 return ret;
254 }
255
256 /* write a register */
257 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
258 {
259 int ret;
260 unsigned char data[2] = { reg, val };
261 struct i2c_msg msg = {
262 .addr = client->addr,
263 .flags = 0,
264 .len = 2,
265 .buf = data,
266 };
267
268 ret = i2c_transfer(client->adapter, &msg, 1);
269 udelay(100);
270
271 if (ret < 0) {
272 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
273 return ret;
274 }
275 return 0;
276 }
277
278
279 /* Read a register, alter its bits, write it back */
280 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
281 {
282 u8 val;
283 int ret;
284
285 ret = ov6650_reg_read(client, reg, &val);
286 if (ret) {
287 dev_err(&client->dev,
288 "[Read]-Modify-Write of register 0x%02x failed!\n",
289 reg);
290 return ret;
291 }
292
293 val &= ~mask;
294 val |= set;
295
296 ret = ov6650_reg_write(client, reg, val);
297 if (ret)
298 dev_err(&client->dev,
299 "Read-Modify-[Write] of register 0x%02x failed!\n",
300 reg);
301
302 return ret;
303 }
304
305 static struct ov6650 *to_ov6650(const struct i2c_client *client)
306 {
307 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
308 }
309
310 /* Start/Stop streaming from the device */
311 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
312 {
313 return 0;
314 }
315
316 /* Get status of additional camera capabilities */
317 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
318 {
319 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
320 struct v4l2_subdev *sd = &priv->subdev;
321 struct i2c_client *client = v4l2_get_subdevdata(sd);
322 uint8_t reg, reg2;
323 int ret;
324
325 switch (ctrl->id) {
326 case V4L2_CID_AUTOGAIN:
327 ret = ov6650_reg_read(client, REG_GAIN, &reg);
328 if (!ret)
329 priv->gain->val = reg;
330 return ret;
331 case V4L2_CID_AUTO_WHITE_BALANCE:
332 ret = ov6650_reg_read(client, REG_BLUE, &reg);
333 if (!ret)
334 ret = ov6650_reg_read(client, REG_RED, &reg2);
335 if (!ret) {
336 priv->blue->val = reg;
337 priv->red->val = reg2;
338 }
339 return ret;
340 case V4L2_CID_EXPOSURE_AUTO:
341 ret = ov6650_reg_read(client, REG_AECH, &reg);
342 if (!ret)
343 priv->exposure->val = reg;
344 return ret;
345 }
346 return -EINVAL;
347 }
348
349 /* Set status of additional camera capabilities */
350 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
351 {
352 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
353 struct v4l2_subdev *sd = &priv->subdev;
354 struct i2c_client *client = v4l2_get_subdevdata(sd);
355 int ret;
356
357 switch (ctrl->id) {
358 case V4L2_CID_AUTOGAIN:
359 ret = ov6650_reg_rmw(client, REG_COMB,
360 ctrl->val ? COMB_AGC : 0, COMB_AGC);
361 if (!ret && !ctrl->val)
362 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
363 return ret;
364 case V4L2_CID_AUTO_WHITE_BALANCE:
365 ret = ov6650_reg_rmw(client, REG_COMB,
366 ctrl->val ? COMB_AWB : 0, COMB_AWB);
367 if (!ret && !ctrl->val) {
368 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
369 if (!ret)
370 ret = ov6650_reg_write(client, REG_RED,
371 priv->red->val);
372 }
373 return ret;
374 case V4L2_CID_SATURATION:
375 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
376 SAT_MASK);
377 case V4L2_CID_HUE:
378 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
379 HUE_MASK);
380 case V4L2_CID_BRIGHTNESS:
381 return ov6650_reg_write(client, REG_BRT, ctrl->val);
382 case V4L2_CID_EXPOSURE_AUTO:
383 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
384 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
385 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
386 ret = ov6650_reg_write(client, REG_AECH,
387 priv->exposure->val);
388 return ret;
389 case V4L2_CID_GAMMA:
390 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
391 case V4L2_CID_VFLIP:
392 return ov6650_reg_rmw(client, REG_COMB,
393 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
394 case V4L2_CID_HFLIP:
395 return ov6650_reg_rmw(client, REG_COMB,
396 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
397 }
398
399 return -EINVAL;
400 }
401
402 #ifdef CONFIG_VIDEO_ADV_DEBUG
403 static int ov6650_get_register(struct v4l2_subdev *sd,
404 struct v4l2_dbg_register *reg)
405 {
406 struct i2c_client *client = v4l2_get_subdevdata(sd);
407 int ret;
408 u8 val;
409
410 if (reg->reg & ~0xff)
411 return -EINVAL;
412
413 reg->size = 1;
414
415 ret = ov6650_reg_read(client, reg->reg, &val);
416 if (!ret)
417 reg->val = (__u64)val;
418
419 return ret;
420 }
421
422 static int ov6650_set_register(struct v4l2_subdev *sd,
423 const struct v4l2_dbg_register *reg)
424 {
425 struct i2c_client *client = v4l2_get_subdevdata(sd);
426
427 if (reg->reg & ~0xff || reg->val & ~0xff)
428 return -EINVAL;
429
430 return ov6650_reg_write(client, reg->reg, reg->val);
431 }
432 #endif
433
434 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
435 {
436 struct i2c_client *client = v4l2_get_subdevdata(sd);
437 struct ov6650 *priv = to_ov6650(client);
438 int ret = 0;
439
440 if (on)
441 ret = v4l2_clk_enable(priv->clk);
442 else
443 v4l2_clk_disable(priv->clk);
444
445 return ret;
446 }
447
448 static int ov6650_get_selection(struct v4l2_subdev *sd,
449 struct v4l2_subdev_pad_config *cfg,
450 struct v4l2_subdev_selection *sel)
451 {
452 struct i2c_client *client = v4l2_get_subdevdata(sd);
453 struct ov6650 *priv = to_ov6650(client);
454
455 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
456 return -EINVAL;
457
458 switch (sel->target) {
459 case V4L2_SEL_TGT_CROP_BOUNDS:
460 sel->r.left = DEF_HSTRT << 1;
461 sel->r.top = DEF_VSTRT << 1;
462 sel->r.width = W_CIF;
463 sel->r.height = H_CIF;
464 return 0;
465 case V4L2_SEL_TGT_CROP:
466 sel->r = priv->rect;
467 return 0;
468 default:
469 return -EINVAL;
470 }
471 }
472
473 static int ov6650_set_selection(struct v4l2_subdev *sd,
474 struct v4l2_subdev_pad_config *cfg,
475 struct v4l2_subdev_selection *sel)
476 {
477 struct i2c_client *client = v4l2_get_subdevdata(sd);
478 struct ov6650 *priv = to_ov6650(client);
479 int ret;
480
481 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
482 sel->target != V4L2_SEL_TGT_CROP)
483 return -EINVAL;
484
485 v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1,
486 &sel->r.height, 2, H_CIF, 1, 0);
487 v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1,
488 (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1,
489 &sel->r.top, DEF_VSTRT << 1,
490 (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height,
491 1, 0);
492
493 ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
494 if (!ret) {
495 priv->rect.width += priv->rect.left - sel->r.left;
496 priv->rect.left = sel->r.left;
497 ret = ov6650_reg_write(client, REG_HSTOP,
498 (sel->r.left + sel->r.width) >> 1);
499 }
500 if (!ret) {
501 priv->rect.width = sel->r.width;
502 ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
503 }
504 if (!ret) {
505 priv->rect.height += priv->rect.top - sel->r.top;
506 priv->rect.top = sel->r.top;
507 ret = ov6650_reg_write(client, REG_VSTOP,
508 (sel->r.top + sel->r.height) >> 1);
509 }
510 if (!ret)
511 priv->rect.height = sel->r.height;
512
513 return ret;
514 }
515
516 static int ov6650_get_fmt(struct v4l2_subdev *sd,
517 struct v4l2_subdev_pad_config *cfg,
518 struct v4l2_subdev_format *format)
519 {
520 struct v4l2_mbus_framefmt *mf = &format->format;
521 struct i2c_client *client = v4l2_get_subdevdata(sd);
522 struct ov6650 *priv = to_ov6650(client);
523
524 if (format->pad)
525 return -EINVAL;
526
527 /* initialize response with default media bus frame format */
528 *mf = ov6650_def_fmt;
529
530 /* update media bus format code and frame size */
531 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
532 mf->width = cfg->try_fmt.width;
533 mf->height = cfg->try_fmt.height;
534 mf->code = cfg->try_fmt.code;
535
536 } else {
537 mf->width = priv->rect.width >> priv->half_scale;
538 mf->height = priv->rect.height >> priv->half_scale;
539 mf->code = priv->code;
540 }
541 return 0;
542 }
543
544 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
545 {
546 return width > rect->width >> 1 || height > rect->height >> 1;
547 }
548
549 static u8 to_clkrc(struct v4l2_fract *timeperframe,
550 unsigned long pclk_limit, unsigned long pclk_max)
551 {
552 unsigned long pclk;
553
554 if (timeperframe->numerator && timeperframe->denominator)
555 pclk = pclk_max * timeperframe->denominator /
556 (FRAME_RATE_MAX * timeperframe->numerator);
557 else
558 pclk = pclk_max;
559
560 if (pclk_limit && pclk_limit < pclk)
561 pclk = pclk_limit;
562
563 return (pclk_max - 1) / pclk;
564 }
565
566 /* set the format we will capture in */
567 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
568 {
569 struct i2c_client *client = v4l2_get_subdevdata(sd);
570 struct ov6650 *priv = to_ov6650(client);
571 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
572 struct v4l2_subdev_selection sel = {
573 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
574 .target = V4L2_SEL_TGT_CROP,
575 .r.left = priv->rect.left + (priv->rect.width >> 1) -
576 (mf->width >> (1 - half_scale)),
577 .r.top = priv->rect.top + (priv->rect.height >> 1) -
578 (mf->height >> (1 - half_scale)),
579 .r.width = mf->width << half_scale,
580 .r.height = mf->height << half_scale,
581 };
582 u32 code = mf->code;
583 unsigned long mclk, pclk;
584 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
585 int ret;
586
587 /* select color matrix configuration for given color encoding */
588 switch (code) {
589 case MEDIA_BUS_FMT_Y8_1X8:
590 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
591 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
592 coma_set |= COMA_BW;
593 break;
594 case MEDIA_BUS_FMT_YUYV8_2X8:
595 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
596 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
597 coma_set |= COMA_WORD_SWAP;
598 break;
599 case MEDIA_BUS_FMT_YVYU8_2X8:
600 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
601 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
602 COMA_BYTE_SWAP;
603 break;
604 case MEDIA_BUS_FMT_UYVY8_2X8:
605 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
606 if (half_scale) {
607 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
608 coma_set |= COMA_BYTE_SWAP;
609 } else {
610 coma_mask |= COMA_RGB | COMA_BW;
611 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
612 }
613 break;
614 case MEDIA_BUS_FMT_VYUY8_2X8:
615 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
616 if (half_scale) {
617 coma_mask |= COMA_RGB | COMA_BW;
618 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
619 } else {
620 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
621 coma_set |= COMA_BYTE_SWAP;
622 }
623 break;
624 case MEDIA_BUS_FMT_SBGGR8_1X8:
625 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
626 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
627 coma_set |= COMA_RAW_RGB | COMA_RGB;
628 break;
629 default:
630 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
631 return -EINVAL;
632 }
633
634 if (code == MEDIA_BUS_FMT_Y8_1X8 ||
635 code == MEDIA_BUS_FMT_SBGGR8_1X8) {
636 coml_mask = COML_ONE_CHANNEL;
637 coml_set = 0;
638 priv->pclk_max = 4000000;
639 } else {
640 coml_mask = 0;
641 coml_set = COML_ONE_CHANNEL;
642 priv->pclk_max = 8000000;
643 }
644
645 if (half_scale) {
646 dev_dbg(&client->dev, "max resolution: QCIF\n");
647 coma_set |= COMA_QCIF;
648 priv->pclk_max /= 2;
649 } else {
650 dev_dbg(&client->dev, "max resolution: CIF\n");
651 coma_mask |= COMA_QCIF;
652 }
653
654 clkrc = CLKRC_12MHz;
655 mclk = 12000000;
656 priv->pclk_limit = 1334000;
657 dev_dbg(&client->dev, "using 12MHz input clock\n");
658
659 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
660
661 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
662 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
663 mclk / pclk, 10 * mclk % pclk / pclk);
664
665 ret = ov6650_set_selection(sd, NULL, &sel);
666 if (!ret)
667 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
668 if (!ret)
669 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
670 if (!ret) {
671 priv->half_scale = half_scale;
672
673 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
674 }
675 if (!ret)
676 priv->code = code;
677
678 return ret;
679 }
680
681 static int ov6650_set_fmt(struct v4l2_subdev *sd,
682 struct v4l2_subdev_pad_config *cfg,
683 struct v4l2_subdev_format *format)
684 {
685 struct v4l2_mbus_framefmt *mf = &format->format;
686 struct i2c_client *client = v4l2_get_subdevdata(sd);
687 struct ov6650 *priv = to_ov6650(client);
688
689 if (format->pad)
690 return -EINVAL;
691
692 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
693 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
694 &mf->height, 2, H_CIF, 1, 0);
695
696 switch (mf->code) {
697 case MEDIA_BUS_FMT_Y10_1X10:
698 mf->code = MEDIA_BUS_FMT_Y8_1X8;
699 /* fall through */
700 case MEDIA_BUS_FMT_Y8_1X8:
701 case MEDIA_BUS_FMT_YVYU8_2X8:
702 case MEDIA_BUS_FMT_YUYV8_2X8:
703 case MEDIA_BUS_FMT_VYUY8_2X8:
704 case MEDIA_BUS_FMT_UYVY8_2X8:
705 break;
706 default:
707 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
708 /* fall through */
709 case MEDIA_BUS_FMT_SBGGR8_1X8:
710 break;
711 }
712
713 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
714 /* store media bus format code and frame size in pad config */
715 cfg->try_fmt.width = mf->width;
716 cfg->try_fmt.height = mf->height;
717 cfg->try_fmt.code = mf->code;
718
719 /* return default mbus frame format updated with pad config */
720 *mf = ov6650_def_fmt;
721 mf->width = cfg->try_fmt.width;
722 mf->height = cfg->try_fmt.height;
723 mf->code = cfg->try_fmt.code;
724
725 } else {
726 /* apply new media bus format code and frame size */
727 int ret = ov6650_s_fmt(sd, mf);
728
729 if (ret)
730 return ret;
731
732 /* return default format updated with active size and code */
733 *mf = ov6650_def_fmt;
734 mf->width = priv->rect.width >> priv->half_scale;
735 mf->height = priv->rect.height >> priv->half_scale;
736 mf->code = priv->code;
737 }
738 return 0;
739 }
740
741 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
742 struct v4l2_subdev_pad_config *cfg,
743 struct v4l2_subdev_mbus_code_enum *code)
744 {
745 if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
746 return -EINVAL;
747
748 code->code = ov6650_codes[code->index];
749 return 0;
750 }
751
752 static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
753 struct v4l2_subdev_frame_interval *ival)
754 {
755 struct i2c_client *client = v4l2_get_subdevdata(sd);
756 struct ov6650 *priv = to_ov6650(client);
757
758 ival->interval.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
759 priv->pclk_limit, priv->pclk_max));
760 ival->interval.denominator = FRAME_RATE_MAX;
761
762 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
763 ival->interval.numerator, ival->interval.denominator);
764
765 return 0;
766 }
767
768 static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
769 struct v4l2_subdev_frame_interval *ival)
770 {
771 struct i2c_client *client = v4l2_get_subdevdata(sd);
772 struct ov6650 *priv = to_ov6650(client);
773 struct v4l2_fract *tpf = &ival->interval;
774 int div, ret;
775 u8 clkrc;
776
777 if (tpf->numerator == 0 || tpf->denominator == 0)
778 div = 1; /* Reset to full rate */
779 else
780 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
781
782 if (div == 0)
783 div = 1;
784 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
785 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
786
787 tpf->numerator = div;
788 tpf->denominator = FRAME_RATE_MAX;
789
790 clkrc = to_clkrc(tpf, priv->pclk_limit, priv->pclk_max);
791
792 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
793 if (!ret) {
794 priv->tpf.numerator = GET_CLKRC_DIV(clkrc);
795 priv->tpf.denominator = FRAME_RATE_MAX;
796
797 *tpf = priv->tpf;
798 }
799
800 return ret;
801 }
802
803 /* Soft reset the camera. This has nothing to do with the RESET pin! */
804 static int ov6650_reset(struct i2c_client *client)
805 {
806 int ret;
807
808 dev_dbg(&client->dev, "reset\n");
809
810 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
811 if (ret)
812 dev_err(&client->dev,
813 "An error occurred while entering soft reset!\n");
814
815 return ret;
816 }
817
818 /* program default register values */
819 static int ov6650_prog_dflt(struct i2c_client *client)
820 {
821 int ret;
822
823 dev_dbg(&client->dev, "initializing\n");
824
825 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
826 if (!ret)
827 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
828
829 return ret;
830 }
831
832 static int ov6650_video_probe(struct v4l2_subdev *sd)
833 {
834 struct i2c_client *client = v4l2_get_subdevdata(sd);
835 struct ov6650 *priv = to_ov6650(client);
836 u8 pidh, pidl, midh, midl;
837 int ret;
838
839 priv->clk = v4l2_clk_get(&client->dev, NULL);
840 if (IS_ERR(priv->clk)) {
841 ret = PTR_ERR(priv->clk);
842 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
843 return ret;
844 }
845
846 ret = ov6650_s_power(sd, 1);
847 if (ret < 0)
848 goto eclkput;
849
850 msleep(20);
851
852 /*
853 * check and show product ID and manufacturer ID
854 */
855 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
856 if (!ret)
857 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
858 if (!ret)
859 ret = ov6650_reg_read(client, REG_MIDH, &midh);
860 if (!ret)
861 ret = ov6650_reg_read(client, REG_MIDL, &midl);
862
863 if (ret)
864 goto done;
865
866 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
867 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
868 pidh, pidl);
869 ret = -ENODEV;
870 goto done;
871 }
872
873 dev_info(&client->dev,
874 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
875 pidh, pidl, midh, midl);
876
877 ret = ov6650_reset(client);
878 if (!ret)
879 ret = ov6650_prog_dflt(client);
880 if (!ret) {
881 struct v4l2_mbus_framefmt mf = ov6650_def_fmt;
882
883 ret = ov6650_s_fmt(sd, &mf);
884 }
885 if (!ret)
886 ret = v4l2_ctrl_handler_setup(&priv->hdl);
887
888 done:
889 ov6650_s_power(sd, 0);
890 if (!ret)
891 return 0;
892 eclkput:
893 v4l2_clk_put(priv->clk);
894
895 return ret;
896 }
897
898 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
899 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
900 .s_ctrl = ov6550_s_ctrl,
901 };
902
903 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
904 #ifdef CONFIG_VIDEO_ADV_DEBUG
905 .g_register = ov6650_get_register,
906 .s_register = ov6650_set_register,
907 #endif
908 .s_power = ov6650_s_power,
909 };
910
911 /* Request bus settings on camera side */
912 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
913 struct v4l2_mbus_config *cfg)
914 {
915
916 cfg->flags = V4L2_MBUS_MASTER |
917 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
918 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
919 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
920 V4L2_MBUS_DATA_ACTIVE_HIGH;
921 cfg->type = V4L2_MBUS_PARALLEL;
922
923 return 0;
924 }
925
926 /* Alter bus settings on camera side */
927 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
928 const struct v4l2_mbus_config *cfg)
929 {
930 struct i2c_client *client = v4l2_get_subdevdata(sd);
931 int ret;
932
933 if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
934 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
935 else
936 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
937 if (ret)
938 return ret;
939
940 if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
941 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
942 else
943 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
944 if (ret)
945 return ret;
946
947 if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
948 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
949 else
950 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
951
952 return ret;
953 }
954
955 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
956 .s_stream = ov6650_s_stream,
957 .g_frame_interval = ov6650_g_frame_interval,
958 .s_frame_interval = ov6650_s_frame_interval,
959 .g_mbus_config = ov6650_g_mbus_config,
960 .s_mbus_config = ov6650_s_mbus_config,
961 };
962
963 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
964 .enum_mbus_code = ov6650_enum_mbus_code,
965 .get_selection = ov6650_get_selection,
966 .set_selection = ov6650_set_selection,
967 .get_fmt = ov6650_get_fmt,
968 .set_fmt = ov6650_set_fmt,
969 };
970
971 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
972 .core = &ov6650_core_ops,
973 .video = &ov6650_video_ops,
974 .pad = &ov6650_pad_ops,
975 };
976
977 static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
978 .registered = ov6650_video_probe,
979 };
980
981 /*
982 * i2c_driver function
983 */
984 static int ov6650_probe(struct i2c_client *client,
985 const struct i2c_device_id *did)
986 {
987 struct ov6650 *priv;
988 int ret;
989
990 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
991 if (!priv)
992 return -ENOMEM;
993
994 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
995 v4l2_ctrl_handler_init(&priv->hdl, 13);
996 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
997 V4L2_CID_VFLIP, 0, 1, 1, 0);
998 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
999 V4L2_CID_HFLIP, 0, 1, 1, 0);
1000 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1001 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1002 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1003 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
1004 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1005 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1006 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1007 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1008 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1009 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1010 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1011 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1012 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1013 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1014 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1015 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1016 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1017 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1018 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1019 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1020 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1021 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1022 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1023
1024 priv->subdev.ctrl_handler = &priv->hdl;
1025 if (priv->hdl.error) {
1026 ret = priv->hdl.error;
1027 goto ectlhdlfree;
1028 }
1029
1030 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1031 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1032 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1033 V4L2_EXPOSURE_MANUAL, true);
1034
1035 priv->rect.left = DEF_HSTRT << 1;
1036 priv->rect.top = DEF_VSTRT << 1;
1037 priv->rect.width = W_CIF;
1038 priv->rect.height = H_CIF;
1039
1040 /* Hardware default frame interval */
1041 priv->tpf.numerator = GET_CLKRC_DIV(DEF_CLKRC);
1042 priv->tpf.denominator = FRAME_RATE_MAX;
1043
1044 priv->subdev.internal_ops = &ov6650_internal_ops;
1045
1046 ret = v4l2_async_register_subdev(&priv->subdev);
1047 if (!ret)
1048 return 0;
1049 ectlhdlfree:
1050 v4l2_ctrl_handler_free(&priv->hdl);
1051
1052 return ret;
1053 }
1054
1055 static int ov6650_remove(struct i2c_client *client)
1056 {
1057 struct ov6650 *priv = to_ov6650(client);
1058
1059 v4l2_clk_put(priv->clk);
1060 v4l2_async_unregister_subdev(&priv->subdev);
1061 v4l2_ctrl_handler_free(&priv->hdl);
1062 return 0;
1063 }
1064
1065 static const struct i2c_device_id ov6650_id[] = {
1066 { "ov6650", 0 },
1067 { }
1068 };
1069 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1070
1071 static struct i2c_driver ov6650_i2c_driver = {
1072 .driver = {
1073 .name = "ov6650",
1074 },
1075 .probe = ov6650_probe,
1076 .remove = ov6650_remove,
1077 .id_table = ov6650_id,
1078 };
1079
1080 module_i2c_driver(ov6650_i2c_driver);
1081
1082 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1083 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1084 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support