drivers/spi/spi-mt65xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: Leilk Liu <leilk.liu@mediatek.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/err.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/ioport.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/platform_data/spi-mt65xx.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #define SPI_CFG0_REG                      0x0000
  23 #define SPI_CFG1_REG                      0x0004
  24 #define SPI_TX_SRC_REG                    0x0008
  25 #define SPI_RX_DST_REG                    0x000c
  26 #define SPI_TX_DATA_REG                   0x0010
  27 #define SPI_RX_DATA_REG                   0x0014
  28 #define SPI_CMD_REG                       0x0018
  29 #define SPI_STATUS0_REG                   0x001c
  30 #define SPI_PAD_SEL_REG                   0x0024
  31 #define SPI_CFG2_REG                      0x0028
  32 #define SPI_TX_SRC_REG_64                 0x002c
  33 #define SPI_RX_DST_REG_64                 0x0030
  34
  35 #define SPI_CFG0_SCK_HIGH_OFFSET          0
  36 #define SPI_CFG0_SCK_LOW_OFFSET           8
  37 #define SPI_CFG0_CS_HOLD_OFFSET           16
  38 #define SPI_CFG0_CS_SETUP_OFFSET          24
  39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET    0
  40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET   16
  41
  42 #define SPI_CFG1_CS_IDLE_OFFSET           0
  43 #define SPI_CFG1_PACKET_LOOP_OFFSET       8
  44 #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
  45 #define SPI_CFG1_GET_TICK_DLY_OFFSET      30
  46
  47 #define SPI_CFG1_CS_IDLE_MASK             0xff
  48 #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
  49 #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
  50 #define SPI_CFG2_SCK_HIGH_OFFSET          0
  51 #define SPI_CFG2_SCK_LOW_OFFSET           16
  52
  53 #define SPI_CMD_ACT                  BIT(0)
  54 #define SPI_CMD_RESUME               BIT(1)
  55 #define SPI_CMD_RST                  BIT(2)
  56 #define SPI_CMD_PAUSE_EN             BIT(4)
  57 #define SPI_CMD_DEASSERT             BIT(5)
  58 #define SPI_CMD_SAMPLE_SEL           BIT(6)
  59 #define SPI_CMD_CS_POL               BIT(7)
  60 #define SPI_CMD_CPHA                 BIT(8)
  61 #define SPI_CMD_CPOL                 BIT(9)
  62 #define SPI_CMD_RX_DMA               BIT(10)
  63 #define SPI_CMD_TX_DMA               BIT(11)
  64 #define SPI_CMD_TXMSBF               BIT(12)
  65 #define SPI_CMD_RXMSBF               BIT(13)
  66 #define SPI_CMD_RX_ENDIAN            BIT(14)
  67 #define SPI_CMD_TX_ENDIAN            BIT(15)
  68 #define SPI_CMD_FINISH_IE            BIT(16)
  69 #define SPI_CMD_PAUSE_IE             BIT(17)
  70
  71 #define MT8173_SPI_MAX_PAD_SEL 3
  72
  73 #define MTK_SPI_PAUSE_INT_STATUS 0x2
  74
  75 #define MTK_SPI_IDLE 0
  76 #define MTK_SPI_PAUSED 1
  77
  78 #define MTK_SPI_MAX_FIFO_SIZE 32U
  79 #define MTK_SPI_PACKET_SIZE 1024
  80 #define MTK_SPI_32BITS_MASK  (0xffffffff)
  81
  82 #define DMA_ADDR_EXT_BITS (36)
  83 #define DMA_ADDR_DEF_BITS (32)
  84
  85 struct mtk_spi_compatible {
  86         bool need_pad_sel;
  87         /* Must explicitly send dummy Tx bytes to do Rx only transfer */
  88         bool must_tx;
  89         /* some IC design adjust cfg register to enhance time accuracy */
  90         bool enhance_timing;
  91         /* some IC support DMA addr extension */
  92         bool dma_ext;
  93 };
  94
  95 struct mtk_spi {
  96         void __iomem *base;
  97         u32 state;
  98         int pad_num;
  99         u32 *pad_sel;
 100         struct clk *parent_clk, *sel_clk, *spi_clk;
 101         struct spi_transfer *cur_transfer;
 102         u32 xfer_len;
 103         u32 num_xfered;
 104         struct scatterlist *tx_sgl, *rx_sgl;
 105         u32 tx_sgl_len, rx_sgl_len;
 106         const struct mtk_spi_compatible *dev_comp;
 107 };
 108
 109 static const struct mtk_spi_compatible mtk_common_compat;
 110
 111 static const struct mtk_spi_compatible mt2712_compat = {
 112         .must_tx = true,
 113 };
 114
 115 static const struct mtk_spi_compatible mt6765_compat = {
 116         .need_pad_sel = true,
 117         .must_tx = true,
 118         .enhance_timing = true,
 119         .dma_ext = true,
 120 };
 121
 122 static const struct mtk_spi_compatible mt7622_compat = {
 123         .must_tx = true,
 124         .enhance_timing = true,
 125 };
 126
 127 static const struct mtk_spi_compatible mt8173_compat = {
 128         .need_pad_sel = true,
 129         .must_tx = true,
 130 };
 131
 132 static const struct mtk_spi_compatible mt8183_compat = {
 133         .need_pad_sel = true,
 134         .must_tx = true,
 135         .enhance_timing = true,
 136 };
 137
 138 /*
 139  * A piece of default chip info unless the platform
 140  * supplies it.
 141  */
 142 static const struct mtk_chip_config mtk_default_chip_info = {
 143         .cs_pol = 0,
 144         .sample_sel = 0,
 145 };
 146
 147 static const struct of_device_id mtk_spi_of_match[] = {
 148         { .compatible = "mediatek,mt2701-spi",
 149                 .data = (void *)&mtk_common_compat,
 150         },
 151         { .compatible = "mediatek,mt2712-spi",
 152                 .data = (void *)&mt2712_compat,
 153         },
 154         { .compatible = "mediatek,mt6589-spi",
 155                 .data = (void *)&mtk_common_compat,
 156         },
 157         { .compatible = "mediatek,mt6765-spi",
 158                 .data = (void *)&mt6765_compat,
 159         },
 160         { .compatible = "mediatek,mt7622-spi",
 161                 .data = (void *)&mt7622_compat,
 162         },
 163         { .compatible = "mediatek,mt7629-spi",
 164                 .data = (void *)&mt7622_compat,
 165         },
 166         { .compatible = "mediatek,mt8135-spi",
 167                 .data = (void *)&mtk_common_compat,
 168         },
 169         { .compatible = "mediatek,mt8173-spi",
 170                 .data = (void *)&mt8173_compat,
 171         },
 172         { .compatible = "mediatek,mt8183-spi",
 173                 .data = (void *)&mt8183_compat,
 174         },
 175         {}
 176 };
 177 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
 178
 179 static void mtk_spi_reset(struct mtk_spi *mdata)
 180 {
 181         u32 reg_val;
 182
 183         /* set the software reset bit in SPI_CMD_REG. */
 184         reg_val = readl(mdata->base + SPI_CMD_REG);
 185         reg_val |= SPI_CMD_RST;
 186         writel(reg_val, mdata->base + SPI_CMD_REG);
 187
 188         reg_val = readl(mdata->base + SPI_CMD_REG);
 189         reg_val &= ~SPI_CMD_RST;
 190         writel(reg_val, mdata->base + SPI_CMD_REG);
 191 }
 192
 193 static int mtk_spi_prepare_message(struct spi_master *master,
 194                                    struct spi_message *msg)
 195 {
 196         u16 cpha, cpol;
 197         u32 reg_val;
 198         struct spi_device *spi = msg->spi;
 199         struct mtk_chip_config *chip_config = spi->controller_data;
 200         struct mtk_spi *mdata = spi_master_get_devdata(master);
 201
 202         cpha = spi->mode & SPI_CPHA ? 1 : 0;
 203         cpol = spi->mode & SPI_CPOL ? 1 : 0;
 204
 205         reg_val = readl(mdata->base + SPI_CMD_REG);
 206         if (cpha)
 207                 reg_val |= SPI_CMD_CPHA;
 208         else
 209                 reg_val &= ~SPI_CMD_CPHA;
 210         if (cpol)
 211                 reg_val |= SPI_CMD_CPOL;
 212         else
 213                 reg_val &= ~SPI_CMD_CPOL;
 214
 215         /* set the mlsbx and mlsbtx */
 216         if (spi->mode & SPI_LSB_FIRST) {
 217                 reg_val &= ~SPI_CMD_TXMSBF;
 218                 reg_val &= ~SPI_CMD_RXMSBF;
 219         } else {
 220                 reg_val |= SPI_CMD_TXMSBF;
 221                 reg_val |= SPI_CMD_RXMSBF;
 222         }
 223
 224         /* set the tx/rx endian */
 225 #ifdef __LITTLE_ENDIAN
 226         reg_val &= ~SPI_CMD_TX_ENDIAN;
 227         reg_val &= ~SPI_CMD_RX_ENDIAN;
 228 #else
 229         reg_val |= SPI_CMD_TX_ENDIAN;
 230         reg_val |= SPI_CMD_RX_ENDIAN;
 231 #endif
 232
 233         if (mdata->dev_comp->enhance_timing) {
 234                 if (chip_config->cs_pol)
 235                         reg_val |= SPI_CMD_CS_POL;
 236                 else
 237                         reg_val &= ~SPI_CMD_CS_POL;
 238                 if (chip_config->sample_sel)
 239                         reg_val |= SPI_CMD_SAMPLE_SEL;
 240                 else
 241                         reg_val &= ~SPI_CMD_SAMPLE_SEL;
 242         }
 243
 244         /* set finish and pause interrupt always enable */
 245         reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
 246
 247         /* disable dma mode */
 248         reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
 249
 250         /* disable deassert mode */
 251         reg_val &= ~SPI_CMD_DEASSERT;
 252
 253         writel(reg_val, mdata->base + SPI_CMD_REG);
 254
 255         /* pad select */
 256         if (mdata->dev_comp->need_pad_sel)
 257                 writel(mdata->pad_sel[spi->chip_select],
 258                        mdata->base + SPI_PAD_SEL_REG);
 259
 260         return 0;
 261 }
 262
 263 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
 264 {
 265         u32 reg_val;
 266         struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
 267
 268         reg_val = readl(mdata->base + SPI_CMD_REG);
 269         if (!enable) {
 270                 reg_val |= SPI_CMD_PAUSE_EN;
 271                 writel(reg_val, mdata->base + SPI_CMD_REG);
 272         } else {
 273                 reg_val &= ~SPI_CMD_PAUSE_EN;
 274                 writel(reg_val, mdata->base + SPI_CMD_REG);
 275                 mdata->state = MTK_SPI_IDLE;
 276                 mtk_spi_reset(mdata);
 277         }
 278 }
 279
 280 static void mtk_spi_prepare_transfer(struct spi_master *master,
 281                                      struct spi_transfer *xfer)
 282 {
 283         u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
 284         struct mtk_spi *mdata = spi_master_get_devdata(master);
 285
 286         spi_clk_hz = clk_get_rate(mdata->spi_clk);
 287         if (xfer->speed_hz < spi_clk_hz / 2)
 288                 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
 289         else
 290                 div = 1;
 291
 292         sck_time = (div + 1) / 2;
 293         cs_time = sck_time * 2;
 294
 295         if (mdata->dev_comp->enhance_timing) {
 296                 reg_val = (((sck_time - 1) & 0xffff)
 297                            << SPI_CFG2_SCK_HIGH_OFFSET);
 298                 reg_val |= (((sck_time - 1) & 0xffff)
 299                            << SPI_CFG2_SCK_LOW_OFFSET);
 300                 writel(reg_val, mdata->base + SPI_CFG2_REG);
 301                 reg_val = (((cs_time - 1) & 0xffff)
 302                            << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
 303                 reg_val |= (((cs_time - 1) & 0xffff)
 304                            << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
 305                 writel(reg_val, mdata->base + SPI_CFG0_REG);
 306         } else {
 307                 reg_val = (((sck_time - 1) & 0xff)
 308                            << SPI_CFG0_SCK_HIGH_OFFSET);
 309                 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
 310                 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
 311                 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
 312                 writel(reg_val, mdata->base + SPI_CFG0_REG);
 313         }
 314
 315         reg_val = readl(mdata->base + SPI_CFG1_REG);
 316         reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
 317         reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
 318         writel(reg_val, mdata->base + SPI_CFG1_REG);
 319 }
 320
 321 static void mtk_spi_setup_packet(struct spi_master *master)
 322 {
 323         u32 packet_size, packet_loop, reg_val;
 324         struct mtk_spi *mdata = spi_master_get_devdata(master);
 325
 326         packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
 327         packet_loop = mdata->xfer_len / packet_size;
 328
 329         reg_val = readl(mdata->base + SPI_CFG1_REG);
 330         reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
 331         reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
 332         reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
 333         writel(reg_val, mdata->base + SPI_CFG1_REG);
 334 }
 335
 336 static void mtk_spi_enable_transfer(struct spi_master *master)
 337 {
 338         u32 cmd;
 339         struct mtk_spi *mdata = spi_master_get_devdata(master);
 340
 341         cmd = readl(mdata->base + SPI_CMD_REG);
 342         if (mdata->state == MTK_SPI_IDLE)
 343                 cmd |= SPI_CMD_ACT;
 344         else
 345                 cmd |= SPI_CMD_RESUME;
 346         writel(cmd, mdata->base + SPI_CMD_REG);
 347 }
 348
 349 static int mtk_spi_get_mult_delta(u32 xfer_len)
 350 {
 351         u32 mult_delta;
 352
 353         if (xfer_len > MTK_SPI_PACKET_SIZE)
 354                 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
 355         else
 356                 mult_delta = 0;
 357
 358         return mult_delta;
 359 }
 360
 361 static void mtk_spi_update_mdata_len(struct spi_master *master)
 362 {
 363         int mult_delta;
 364         struct mtk_spi *mdata = spi_master_get_devdata(master);
 365
 366         if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
 367                 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
 368                         mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 369                         mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 370                         mdata->rx_sgl_len = mult_delta;
 371                         mdata->tx_sgl_len -= mdata->xfer_len;
 372                 } else {
 373                         mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 374                         mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 375                         mdata->tx_sgl_len = mult_delta;
 376                         mdata->rx_sgl_len -= mdata->xfer_len;
 377                 }
 378         } else if (mdata->tx_sgl_len) {
 379                 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 380                 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 381                 mdata->tx_sgl_len = mult_delta;
 382         } else if (mdata->rx_sgl_len) {
 383                 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 384                 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 385                 mdata->rx_sgl_len = mult_delta;
 386         }
 387 }
 388
 389 static void mtk_spi_setup_dma_addr(struct spi_master *master,
 390                                    struct spi_transfer *xfer)
 391 {
 392         struct mtk_spi *mdata = spi_master_get_devdata(master);
 393
 394         if (mdata->tx_sgl) {
 395                 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
 396                        mdata->base + SPI_TX_SRC_REG);
 397 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 398                 if (mdata->dev_comp->dma_ext)
 399                         writel((u32)(xfer->tx_dma >> 32),
 400                                mdata->base + SPI_TX_SRC_REG_64);
 401 #endif
 402         }
 403
 404         if (mdata->rx_sgl) {
 405                 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
 406                        mdata->base + SPI_RX_DST_REG);
 407 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 408                 if (mdata->dev_comp->dma_ext)
 409                         writel((u32)(xfer->rx_dma >> 32),
 410                                mdata->base + SPI_RX_DST_REG_64);
 411 #endif
 412         }
 413 }
 414
 415 static int mtk_spi_fifo_transfer(struct spi_master *master,
 416                                  struct spi_device *spi,
 417                                  struct spi_transfer *xfer)
 418 {
 419         int cnt, remainder;
 420         u32 reg_val;
 421         struct mtk_spi *mdata = spi_master_get_devdata(master);
 422
 423         mdata->cur_transfer = xfer;
 424         mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
 425         mdata->num_xfered = 0;
 426         mtk_spi_prepare_transfer(master, xfer);
 427         mtk_spi_setup_packet(master);
 428
 429         cnt = xfer->len / 4;
 430         iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
 431
 432         remainder = xfer->len % 4;
 433         if (remainder > 0) {
 434                 reg_val = 0;
 435                 memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
 436                 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
 437         }
 438
 439         mtk_spi_enable_transfer(master);
 440
 441         return 1;
 442 }
 443
 444 static int mtk_spi_dma_transfer(struct spi_master *master,
 445                                 struct spi_device *spi,
 446                                 struct spi_transfer *xfer)
 447 {
 448         int cmd;
 449         struct mtk_spi *mdata = spi_master_get_devdata(master);
 450
 451         mdata->tx_sgl = NULL;
 452         mdata->rx_sgl = NULL;
 453         mdata->tx_sgl_len = 0;
 454         mdata->rx_sgl_len = 0;
 455         mdata->cur_transfer = xfer;
 456         mdata->num_xfered = 0;
 457
 458         mtk_spi_prepare_transfer(master, xfer);
 459
 460         cmd = readl(mdata->base + SPI_CMD_REG);
 461         if (xfer->tx_buf)
 462                 cmd |= SPI_CMD_TX_DMA;
 463         if (xfer->rx_buf)
 464                 cmd |= SPI_CMD_RX_DMA;
 465         writel(cmd, mdata->base + SPI_CMD_REG);
 466
 467         if (xfer->tx_buf)
 468                 mdata->tx_sgl = xfer->tx_sg.sgl;
 469         if (xfer->rx_buf)
 470                 mdata->rx_sgl = xfer->rx_sg.sgl;
 471
 472         if (mdata->tx_sgl) {
 473                 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
 474                 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 475         }
 476         if (mdata->rx_sgl) {
 477                 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
 478                 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 479         }
 480
 481         mtk_spi_update_mdata_len(master);
 482         mtk_spi_setup_packet(master);
 483         mtk_spi_setup_dma_addr(master, xfer);
 484         mtk_spi_enable_transfer(master);
 485
 486         return 1;
 487 }
 488
 489 static int mtk_spi_transfer_one(struct spi_master *master,
 490                                 struct spi_device *spi,
 491                                 struct spi_transfer *xfer)
 492 {
 493         if (master->can_dma(master, spi, xfer))
 494                 return mtk_spi_dma_transfer(master, spi, xfer);
 495         else
 496                 return mtk_spi_fifo_transfer(master, spi, xfer);
 497 }
 498
 499 static bool mtk_spi_can_dma(struct spi_master *master,
 500                             struct spi_device *spi,
 501                             struct spi_transfer *xfer)
 502 {
 503         /* Buffers for DMA transactions must be 4-byte aligned */
 504         return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
 505                 (unsigned long)xfer->tx_buf % 4 == 0 &&
 506                 (unsigned long)xfer->rx_buf % 4 == 0);
 507 }
 508
 509 static int mtk_spi_setup(struct spi_device *spi)
 510 {
 511         struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
 512
 513         if (!spi->controller_data)
 514                 spi->controller_data = (void *)&mtk_default_chip_info;
 515
 516         if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
 517                 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
 518
 519         return 0;
 520 }
 521
 522 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
 523 {
 524         u32 cmd, reg_val, cnt, remainder, len;
 525         struct spi_master *master = dev_id;
 526         struct mtk_spi *mdata = spi_master_get_devdata(master);
 527         struct spi_transfer *trans = mdata->cur_transfer;
 528
 529         reg_val = readl(mdata->base + SPI_STATUS0_REG);
 530         if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
 531                 mdata->state = MTK_SPI_PAUSED;
 532         else
 533                 mdata->state = MTK_SPI_IDLE;
 534
 535         if (!master->can_dma(master, master->cur_msg->spi, trans)) {
 536                 if (trans->rx_buf) {
 537                         cnt = mdata->xfer_len / 4;
 538                         ioread32_rep(mdata->base + SPI_RX_DATA_REG,
 539                                      trans->rx_buf + mdata->num_xfered, cnt);
 540                         remainder = mdata->xfer_len % 4;
 541                         if (remainder > 0) {
 542                                 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
 543                                 memcpy(trans->rx_buf +
 544                                         mdata->num_xfered +
 545                                         (cnt * 4),
 546                                         &reg_val,
 547                                         remainder);
 548                         }
 549                 }
 550
 551                 mdata->num_xfered += mdata->xfer_len;
 552                 if (mdata->num_xfered == trans->len) {
 553                         spi_finalize_current_transfer(master);
 554                         return IRQ_HANDLED;
 555                 }
 556
 557                 len = trans->len - mdata->num_xfered;
 558                 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
 559                 mtk_spi_setup_packet(master);
 560
 561                 cnt = mdata->xfer_len / 4;
 562                 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
 563                                 trans->tx_buf + mdata->num_xfered, cnt);
 564
 565                 remainder = mdata->xfer_len % 4;
 566                 if (remainder > 0) {
 567                         reg_val = 0;
 568                         memcpy(&reg_val,
 569                                 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
 570                                 remainder);
 571                         writel(reg_val, mdata->base + SPI_TX_DATA_REG);
 572                 }
 573
 574                 mtk_spi_enable_transfer(master);
 575
 576                 return IRQ_HANDLED;
 577         }
 578
 579         if (mdata->tx_sgl)
 580                 trans->tx_dma += mdata->xfer_len;
 581         if (mdata->rx_sgl)
 582                 trans->rx_dma += mdata->xfer_len;
 583
 584         if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
 585                 mdata->tx_sgl = sg_next(mdata->tx_sgl);
 586                 if (mdata->tx_sgl) {
 587                         trans->tx_dma = sg_dma_address(mdata->tx_sgl);
 588                         mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 589                 }
 590         }
 591         if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
 592                 mdata->rx_sgl = sg_next(mdata->rx_sgl);
 593                 if (mdata->rx_sgl) {
 594                         trans->rx_dma = sg_dma_address(mdata->rx_sgl);
 595                         mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 596                 }
 597         }
 598
 599         if (!mdata->tx_sgl && !mdata->rx_sgl) {
 600                 /* spi disable dma */
 601                 cmd = readl(mdata->base + SPI_CMD_REG);
 602                 cmd &= ~SPI_CMD_TX_DMA;
 603                 cmd &= ~SPI_CMD_RX_DMA;
 604                 writel(cmd, mdata->base + SPI_CMD_REG);
 605
 606                 spi_finalize_current_transfer(master);
 607                 return IRQ_HANDLED;
 608         }
 609
 610         mtk_spi_update_mdata_len(master);
 611         mtk_spi_setup_packet(master);
 612         mtk_spi_setup_dma_addr(master, trans);
 613         mtk_spi_enable_transfer(master);
 614
 615         return IRQ_HANDLED;
 616 }
 617
 618 static int mtk_spi_probe(struct platform_device *pdev)
 619 {
 620         struct spi_master *master;
 621         struct mtk_spi *mdata;
 622         const struct of_device_id *of_id;
 623         struct resource *res;
 624         int i, irq, ret, addr_bits;
 625
 626         master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
 627         if (!master) {
 628                 dev_err(&pdev->dev, "failed to alloc spi master\n");
 629                 return -ENOMEM;
 630         }
 631
 632         master->auto_runtime_pm = true;
 633         master->dev.of_node = pdev->dev.of_node;
 634         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
 635
 636         master->set_cs = mtk_spi_set_cs;
 637         master->prepare_message = mtk_spi_prepare_message;
 638         master->transfer_one = mtk_spi_transfer_one;
 639         master->can_dma = mtk_spi_can_dma;
 640         master->setup = mtk_spi_setup;
 641
 642         of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
 643         if (!of_id) {
 644                 dev_err(&pdev->dev, "failed to probe of_node\n");
 645                 ret = -EINVAL;
 646                 goto err_put_master;
 647         }
 648
 649         mdata = spi_master_get_devdata(master);
 650         mdata->dev_comp = of_id->data;
 651         if (mdata->dev_comp->must_tx)
 652                 master->flags = SPI_MASTER_MUST_TX;
 653
 654         if (mdata->dev_comp->need_pad_sel) {
 655                 mdata->pad_num = of_property_count_u32_elems(
 656                         pdev->dev.of_node,
 657                         "mediatek,pad-select");
 658                 if (mdata->pad_num < 0) {
 659                         dev_err(&pdev->dev,
 660                                 "No 'mediatek,pad-select' property\n");
 661                         ret = -EINVAL;
 662                         goto err_put_master;
 663                 }
 664
 665                 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
 666                                                     sizeof(u32), GFP_KERNEL);
 667                 if (!mdata->pad_sel) {
 668                         ret = -ENOMEM;
 669                         goto err_put_master;
 670                 }
 671
 672                 for (i = 0; i < mdata->pad_num; i++) {
 673                         of_property_read_u32_index(pdev->dev.of_node,
 674                                                    "mediatek,pad-select",
 675                                                    i, &mdata->pad_sel[i]);
 676                         if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
 677                                 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
 678                                         i, mdata->pad_sel[i]);
 679                                 ret = -EINVAL;
 680                                 goto err_put_master;
 681                         }
 682                 }
 683         }
 684
 685         platform_set_drvdata(pdev, master);
 686
 687         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 688         if (!res) {
 689                 ret = -ENODEV;
 690                 dev_err(&pdev->dev, "failed to determine base address\n");
 691                 goto err_put_master;
 692         }
 693
 694         mdata->base = devm_ioremap_resource(&pdev->dev, res);
 695         if (IS_ERR(mdata->base)) {
 696                 ret = PTR_ERR(mdata->base);
 697                 goto err_put_master;
 698         }
 699
 700         irq = platform_get_irq(pdev, 0);
 701         if (irq < 0) {
 702                 ret = irq;
 703                 goto err_put_master;
 704         }
 705
 706         if (!pdev->dev.dma_mask)
 707                 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 708
 709         ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
 710                                IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
 711         if (ret) {
 712                 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
 713                 goto err_put_master;
 714         }
 715
 716         mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
 717         if (IS_ERR(mdata->parent_clk)) {
 718                 ret = PTR_ERR(mdata->parent_clk);
 719                 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
 720                 goto err_put_master;
 721         }
 722
 723         mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
 724         if (IS_ERR(mdata->sel_clk)) {
 725                 ret = PTR_ERR(mdata->sel_clk);
 726                 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
 727                 goto err_put_master;
 728         }
 729
 730         mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
 731         if (IS_ERR(mdata->spi_clk)) {
 732                 ret = PTR_ERR(mdata->spi_clk);
 733                 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
 734                 goto err_put_master;
 735         }
 736
 737         ret = clk_prepare_enable(mdata->spi_clk);
 738         if (ret < 0) {
 739                 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
 740                 goto err_put_master;
 741         }
 742
 743         ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
 744         if (ret < 0) {
 745                 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
 746                 clk_disable_unprepare(mdata->spi_clk);
 747                 goto err_put_master;
 748         }
 749
 750         clk_disable_unprepare(mdata->spi_clk);
 751
 752         pm_runtime_enable(&pdev->dev);
 753
 754         ret = devm_spi_register_master(&pdev->dev, master);
 755         if (ret) {
 756                 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
 757                 goto err_disable_runtime_pm;
 758         }
 759
 760         if (mdata->dev_comp->need_pad_sel) {
 761                 if (mdata->pad_num != master->num_chipselect) {
 762                         dev_err(&pdev->dev,
 763                                 "pad_num does not match num_chipselect(%d != %d)\n",
 764                                 mdata->pad_num, master->num_chipselect);
 765                         ret = -EINVAL;
 766                         goto err_disable_runtime_pm;
 767                 }
 768
 769                 if (!master->cs_gpios && master->num_chipselect > 1) {
 770                         dev_err(&pdev->dev,
 771                                 "cs_gpios not specified and num_chipselect > 1\n");
 772                         ret = -EINVAL;
 773                         goto err_disable_runtime_pm;
 774                 }
 775
 776                 if (master->cs_gpios) {
 777                         for (i = 0; i < master->num_chipselect; i++) {
 778                                 ret = devm_gpio_request(&pdev->dev,
 779                                                         master->cs_gpios[i],
 780                                                         dev_name(&pdev->dev));
 781                                 if (ret) {
 782                                         dev_err(&pdev->dev,
 783                                                 "can't get CS GPIO %i\n", i);
 784                                         goto err_disable_runtime_pm;
 785                                 }
 786                         }
 787                 }
 788         }
 789
 790         if (mdata->dev_comp->dma_ext)
 791                 addr_bits = DMA_ADDR_EXT_BITS;
 792         else
 793                 addr_bits = DMA_ADDR_DEF_BITS;
 794         ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
 795         if (ret)
 796                 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
 797                            addr_bits, ret);
 798
 799         return 0;
 800
 801 err_disable_runtime_pm:
 802         pm_runtime_disable(&pdev->dev);
 803 err_put_master:
 804         spi_master_put(master);
 805
 806         return ret;
 807 }
 808
 809 static int mtk_spi_remove(struct platform_device *pdev)
 810 {
 811         struct spi_master *master = platform_get_drvdata(pdev);
 812         struct mtk_spi *mdata = spi_master_get_devdata(master);
 813
 814         pm_runtime_disable(&pdev->dev);
 815
 816         mtk_spi_reset(mdata);
 817
 818         return 0;
 819 }
 820
 821 #ifdef CONFIG_PM_SLEEP
 822 static int mtk_spi_suspend(struct device *dev)
 823 {
 824         int ret;
 825         struct spi_master *master = dev_get_drvdata(dev);
 826         struct mtk_spi *mdata = spi_master_get_devdata(master);
 827
 828         ret = spi_master_suspend(master);
 829         if (ret)
 830                 return ret;
 831
 832         if (!pm_runtime_suspended(dev))
 833                 clk_disable_unprepare(mdata->spi_clk);
 834
 835         return ret;
 836 }
 837
 838 static int mtk_spi_resume(struct device *dev)
 839 {
 840         int ret;
 841         struct spi_master *master = dev_get_drvdata(dev);
 842         struct mtk_spi *mdata = spi_master_get_devdata(master);
 843
 844         if (!pm_runtime_suspended(dev)) {
 845                 ret = clk_prepare_enable(mdata->spi_clk);
 846                 if (ret < 0) {
 847                         dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
 848                         return ret;
 849                 }
 850         }
 851
 852         ret = spi_master_resume(master);
 853         if (ret < 0)
 854                 clk_disable_unprepare(mdata->spi_clk);
 855
 856         return ret;
 857 }
 858 #endif /* CONFIG_PM_SLEEP */
 859
 860 #ifdef CONFIG_PM
 861 static int mtk_spi_runtime_suspend(struct device *dev)
 862 {
 863         struct spi_master *master = dev_get_drvdata(dev);
 864         struct mtk_spi *mdata = spi_master_get_devdata(master);
 865
 866         clk_disable_unprepare(mdata->spi_clk);
 867
 868         return 0;
 869 }
 870
 871 static int mtk_spi_runtime_resume(struct device *dev)
 872 {
 873         struct spi_master *master = dev_get_drvdata(dev);
 874         struct mtk_spi *mdata = spi_master_get_devdata(master);
 875         int ret;
 876
 877         ret = clk_prepare_enable(mdata->spi_clk);
 878         if (ret < 0) {
 879                 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
 880                 return ret;
 881         }
 882
 883         return 0;
 884 }
 885 #endif /* CONFIG_PM */
 886
 887 static const struct dev_pm_ops mtk_spi_pm = {
 888         SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
 889         SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
 890                            mtk_spi_runtime_resume, NULL)
 891 };
 892
 893 static struct platform_driver mtk_spi_driver = {
 894         .driver = {
 895                 .name = "mtk-spi",
 896                 .pm     = &mtk_spi_pm,
 897                 .of_match_table = mtk_spi_of_match,
 898         },
 899         .probe = mtk_spi_probe,
 900         .remove = mtk_spi_remove,
 901 };
 902
 903 module_platform_driver(mtk_spi_driver);
 904
 905 MODULE_DESCRIPTION("MTK SPI Controller driver");
 906 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
 907 MODULE_LICENSE("GPL v2");
 908 MODULE_ALIAS("platform:mtk-spi");