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dm: Call proper helper to determine dax support
[linux/fpc-iii.git] / drivers / spi / spi-pxa2xx.c
blob7f4285e2ae682e4c91d342e67ac388c94657556d
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, Intel Corporation
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/ioport.h>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/pxa2xx_spi.h>
19 #include <linux/spi/spi.h>
20 #include <linux/delay.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/acpi.h>
27 #include <linux/of_device.h>
28
29 #include "spi-pxa2xx.h"
30
31 MODULE_AUTHOR("Stephen Street");
32 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
33 MODULE_LICENSE("GPL");
34 MODULE_ALIAS("platform:pxa2xx-spi");
35
36 #define TIMOUT_DFLT 1000
37
38 /*
39 * for testing SSCR1 changes that require SSP restart, basically
40 * everything except the service and interrupt enables, the pxa270 developer
41 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
42 * list, but the PXA255 dev man says all bits without really meaning the
43 * service and interrupt enables
44 */
45 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
46 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
47 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
48 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
49 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
50 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
51
52 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
53 | QUARK_X1000_SSCR1_EFWR \
54 | QUARK_X1000_SSCR1_RFT \
55 | QUARK_X1000_SSCR1_TFT \
56 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
57
58 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
59 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
60 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
61 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
62 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CAPS_CS_EN_SHIFT 9
69 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
70
71 #define LPSS_PRIV_CLOCK_GATE 0x38
72 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
73 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
74
75 struct lpss_config {
76 /* LPSS offset from drv_data->ioaddr */
77 unsigned offset;
78 /* Register offsets from drv_data->lpss_base or -1 */
79 int reg_general;
80 int reg_ssp;
81 int reg_cs_ctrl;
82 int reg_capabilities;
83 /* FIFO thresholds */
84 u32 rx_threshold;
85 u32 tx_threshold_lo;
86 u32 tx_threshold_hi;
87 /* Chip select control */
88 unsigned cs_sel_shift;
89 unsigned cs_sel_mask;
90 unsigned cs_num;
91 /* Quirks */
92 unsigned cs_clk_stays_gated : 1;
93 };
94
95 /* Keep these sorted with enum pxa_ssp_type */
96 static const struct lpss_config lpss_platforms[] = {
97 { /* LPSS_LPT_SSP */
98 .offset = 0x800,
99 .reg_general = 0x08,
100 .reg_ssp = 0x0c,
101 .reg_cs_ctrl = 0x18,
102 .reg_capabilities = -1,
103 .rx_threshold = 64,
104 .tx_threshold_lo = 160,
105 .tx_threshold_hi = 224,
106 },
107 { /* LPSS_BYT_SSP */
108 .offset = 0x400,
109 .reg_general = 0x08,
110 .reg_ssp = 0x0c,
111 .reg_cs_ctrl = 0x18,
112 .reg_capabilities = -1,
113 .rx_threshold = 64,
114 .tx_threshold_lo = 160,
115 .tx_threshold_hi = 224,
116 },
117 { /* LPSS_BSW_SSP */
118 .offset = 0x400,
119 .reg_general = 0x08,
120 .reg_ssp = 0x0c,
121 .reg_cs_ctrl = 0x18,
122 .reg_capabilities = -1,
123 .rx_threshold = 64,
124 .tx_threshold_lo = 160,
125 .tx_threshold_hi = 224,
126 .cs_sel_shift = 2,
127 .cs_sel_mask = 1 << 2,
128 .cs_num = 2,
129 },
130 { /* LPSS_SPT_SSP */
131 .offset = 0x200,
132 .reg_general = -1,
133 .reg_ssp = 0x20,
134 .reg_cs_ctrl = 0x24,
135 .reg_capabilities = -1,
136 .rx_threshold = 1,
137 .tx_threshold_lo = 32,
138 .tx_threshold_hi = 56,
139 },
140 { /* LPSS_BXT_SSP */
141 .offset = 0x200,
142 .reg_general = -1,
143 .reg_ssp = 0x20,
144 .reg_cs_ctrl = 0x24,
145 .reg_capabilities = 0xfc,
146 .rx_threshold = 1,
147 .tx_threshold_lo = 16,
148 .tx_threshold_hi = 48,
149 .cs_sel_shift = 8,
150 .cs_sel_mask = 3 << 8,
151 .cs_clk_stays_gated = true,
152 },
153 { /* LPSS_CNL_SSP */
154 .offset = 0x200,
155 .reg_general = -1,
156 .reg_ssp = 0x20,
157 .reg_cs_ctrl = 0x24,
158 .reg_capabilities = 0xfc,
159 .rx_threshold = 1,
160 .tx_threshold_lo = 32,
161 .tx_threshold_hi = 56,
162 .cs_sel_shift = 8,
163 .cs_sel_mask = 3 << 8,
164 .cs_clk_stays_gated = true,
165 },
166 };
167
168 static inline const struct lpss_config
169 *lpss_get_config(const struct driver_data *drv_data)
170 {
171 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
172 }
173
174 static bool is_lpss_ssp(const struct driver_data *drv_data)
175 {
176 switch (drv_data->ssp_type) {
177 case LPSS_LPT_SSP:
178 case LPSS_BYT_SSP:
179 case LPSS_BSW_SSP:
180 case LPSS_SPT_SSP:
181 case LPSS_BXT_SSP:
182 case LPSS_CNL_SSP:
183 return true;
184 default:
185 return false;
186 }
187 }
188
189 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
190 {
191 return drv_data->ssp_type == QUARK_X1000_SSP;
192 }
193
194 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
195 {
196 switch (drv_data->ssp_type) {
197 case QUARK_X1000_SSP:
198 return QUARK_X1000_SSCR1_CHANGE_MASK;
199 case CE4100_SSP:
200 return CE4100_SSCR1_CHANGE_MASK;
201 default:
202 return SSCR1_CHANGE_MASK;
203 }
204 }
205
206 static u32
207 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
208 {
209 switch (drv_data->ssp_type) {
210 case QUARK_X1000_SSP:
211 return RX_THRESH_QUARK_X1000_DFLT;
212 case CE4100_SSP:
213 return RX_THRESH_CE4100_DFLT;
214 default:
215 return RX_THRESH_DFLT;
216 }
217 }
218
219 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
220 {
221 u32 mask;
222
223 switch (drv_data->ssp_type) {
224 case QUARK_X1000_SSP:
225 mask = QUARK_X1000_SSSR_TFL_MASK;
226 break;
227 case CE4100_SSP:
228 mask = CE4100_SSSR_TFL_MASK;
229 break;
230 default:
231 mask = SSSR_TFL_MASK;
232 break;
233 }
234
235 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
236 }
237
238 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
239 u32 *sccr1_reg)
240 {
241 u32 mask;
242
243 switch (drv_data->ssp_type) {
244 case QUARK_X1000_SSP:
245 mask = QUARK_X1000_SSCR1_RFT;
246 break;
247 case CE4100_SSP:
248 mask = CE4100_SSCR1_RFT;
249 break;
250 default:
251 mask = SSCR1_RFT;
252 break;
253 }
254 *sccr1_reg &= ~mask;
255 }
256
257 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
258 u32 *sccr1_reg, u32 threshold)
259 {
260 switch (drv_data->ssp_type) {
261 case QUARK_X1000_SSP:
262 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
263 break;
264 case CE4100_SSP:
265 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
266 break;
267 default:
268 *sccr1_reg |= SSCR1_RxTresh(threshold);
269 break;
270 }
271 }
272
273 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
274 u32 clk_div, u8 bits)
275 {
276 switch (drv_data->ssp_type) {
277 case QUARK_X1000_SSP:
278 return clk_div
279 | QUARK_X1000_SSCR0_Motorola
280 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
281 | SSCR0_SSE;
282 default:
283 return clk_div
284 | SSCR0_Motorola
285 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
286 | SSCR0_SSE
287 | (bits > 16 ? SSCR0_EDSS : 0);
288 }
289 }
290
291 /*
292 * Read and write LPSS SSP private registers. Caller must first check that
293 * is_lpss_ssp() returns true before these can be called.
294 */
295 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
296 {
297 WARN_ON(!drv_data->lpss_base);
298 return readl(drv_data->lpss_base + offset);
299 }
300
301 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
302 unsigned offset, u32 value)
303 {
304 WARN_ON(!drv_data->lpss_base);
305 writel(value, drv_data->lpss_base + offset);
306 }
307
308 /*
309 * lpss_ssp_setup - perform LPSS SSP specific setup
310 * @drv_data: pointer to the driver private data
311 *
312 * Perform LPSS SSP specific setup. This function must be called first if
313 * one is going to use LPSS SSP private registers.
314 */
315 static void lpss_ssp_setup(struct driver_data *drv_data)
316 {
317 const struct lpss_config *config;
318 u32 value;
319
320 config = lpss_get_config(drv_data);
321 drv_data->lpss_base = drv_data->ioaddr + config->offset;
322
323 /* Enable software chip select control */
324 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
325 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
326 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
327 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
328
329 /* Enable multiblock DMA transfers */
330 if (drv_data->controller_info->enable_dma) {
331 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
332
333 if (config->reg_general >= 0) {
334 value = __lpss_ssp_read_priv(drv_data,
335 config->reg_general);
336 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
337 __lpss_ssp_write_priv(drv_data,
338 config->reg_general, value);
339 }
340 }
341 }
342
343 static void lpss_ssp_select_cs(struct spi_device *spi,
344 const struct lpss_config *config)
345 {
346 struct driver_data *drv_data =
347 spi_controller_get_devdata(spi->controller);
348 u32 value, cs;
349
350 if (!config->cs_sel_mask)
351 return;
352
353 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
354
355 cs = spi->chip_select;
356 cs <<= config->cs_sel_shift;
357 if (cs != (value & config->cs_sel_mask)) {
358 /*
359 * When switching another chip select output active the
360 * output must be selected first and wait 2 ssp_clk cycles
361 * before changing state to active. Otherwise a short
362 * glitch will occur on the previous chip select since
363 * output select is latched but state control is not.
364 */
365 value &= ~config->cs_sel_mask;
366 value |= cs;
367 __lpss_ssp_write_priv(drv_data,
368 config->reg_cs_ctrl, value);
369 ndelay(1000000000 /
370 (drv_data->controller->max_speed_hz / 2));
371 }
372 }
373
374 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
375 {
376 struct driver_data *drv_data =
377 spi_controller_get_devdata(spi->controller);
378 const struct lpss_config *config;
379 u32 value;
380
381 config = lpss_get_config(drv_data);
382
383 if (enable)
384 lpss_ssp_select_cs(spi, config);
385
386 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
387 if (enable)
388 value &= ~LPSS_CS_CONTROL_CS_HIGH;
389 else
390 value |= LPSS_CS_CONTROL_CS_HIGH;
391 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
392 if (config->cs_clk_stays_gated) {
393 u32 clkgate;
394
395 /*
396 * Changing CS alone when dynamic clock gating is on won't
397 * actually flip CS at that time. This ruins SPI transfers
398 * that specify delays, or have no data. Toggle the clock mode
399 * to force on briefly to poke the CS pin to move.
400 */
401 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
402 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
403 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
404
405 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
406 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
407 }
408 }
409
410 static void cs_assert(struct spi_device *spi)
411 {
412 struct chip_data *chip = spi_get_ctldata(spi);
413 struct driver_data *drv_data =
414 spi_controller_get_devdata(spi->controller);
415
416 if (drv_data->ssp_type == CE4100_SSP) {
417 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
418 return;
419 }
420
421 if (chip->cs_control) {
422 chip->cs_control(PXA2XX_CS_ASSERT);
423 return;
424 }
425
426 if (chip->gpiod_cs) {
427 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
428 return;
429 }
430
431 if (is_lpss_ssp(drv_data))
432 lpss_ssp_cs_control(spi, true);
433 }
434
435 static void cs_deassert(struct spi_device *spi)
436 {
437 struct chip_data *chip = spi_get_ctldata(spi);
438 struct driver_data *drv_data =
439 spi_controller_get_devdata(spi->controller);
440 unsigned long timeout;
441
442 if (drv_data->ssp_type == CE4100_SSP)
443 return;
444
445 /* Wait until SSP becomes idle before deasserting the CS */
446 timeout = jiffies + msecs_to_jiffies(10);
447 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
448 !time_after(jiffies, timeout))
449 cpu_relax();
450
451 if (chip->cs_control) {
452 chip->cs_control(PXA2XX_CS_DEASSERT);
453 return;
454 }
455
456 if (chip->gpiod_cs) {
457 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
458 return;
459 }
460
461 if (is_lpss_ssp(drv_data))
462 lpss_ssp_cs_control(spi, false);
463 }
464
465 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
466 {
467 if (level)
468 cs_deassert(spi);
469 else
470 cs_assert(spi);
471 }
472
473 int pxa2xx_spi_flush(struct driver_data *drv_data)
474 {
475 unsigned long limit = loops_per_jiffy << 1;
476
477 do {
478 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
479 pxa2xx_spi_read(drv_data, SSDR);
480 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
481 write_SSSR_CS(drv_data, SSSR_ROR);
482
483 return limit;
484 }
485
486 static int null_writer(struct driver_data *drv_data)
487 {
488 u8 n_bytes = drv_data->n_bytes;
489
490 if (pxa2xx_spi_txfifo_full(drv_data)
491 || (drv_data->tx == drv_data->tx_end))
492 return 0;
493
494 pxa2xx_spi_write(drv_data, SSDR, 0);
495 drv_data->tx += n_bytes;
496
497 return 1;
498 }
499
500 static int null_reader(struct driver_data *drv_data)
501 {
502 u8 n_bytes = drv_data->n_bytes;
503
504 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
505 && (drv_data->rx < drv_data->rx_end)) {
506 pxa2xx_spi_read(drv_data, SSDR);
507 drv_data->rx += n_bytes;
508 }
509
510 return drv_data->rx == drv_data->rx_end;
511 }
512
513 static int u8_writer(struct driver_data *drv_data)
514 {
515 if (pxa2xx_spi_txfifo_full(drv_data)
516 || (drv_data->tx == drv_data->tx_end))
517 return 0;
518
519 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
520 ++drv_data->tx;
521
522 return 1;
523 }
524
525 static int u8_reader(struct driver_data *drv_data)
526 {
527 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
528 && (drv_data->rx < drv_data->rx_end)) {
529 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
530 ++drv_data->rx;
531 }
532
533 return drv_data->rx == drv_data->rx_end;
534 }
535
536 static int u16_writer(struct driver_data *drv_data)
537 {
538 if (pxa2xx_spi_txfifo_full(drv_data)
539 || (drv_data->tx == drv_data->tx_end))
540 return 0;
541
542 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
543 drv_data->tx += 2;
544
545 return 1;
546 }
547
548 static int u16_reader(struct driver_data *drv_data)
549 {
550 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
551 && (drv_data->rx < drv_data->rx_end)) {
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
553 drv_data->rx += 2;
554 }
555
556 return drv_data->rx == drv_data->rx_end;
557 }
558
559 static int u32_writer(struct driver_data *drv_data)
560 {
561 if (pxa2xx_spi_txfifo_full(drv_data)
562 || (drv_data->tx == drv_data->tx_end))
563 return 0;
564
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
566 drv_data->tx += 4;
567
568 return 1;
569 }
570
571 static int u32_reader(struct driver_data *drv_data)
572 {
573 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
574 && (drv_data->rx < drv_data->rx_end)) {
575 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
576 drv_data->rx += 4;
577 }
578
579 return drv_data->rx == drv_data->rx_end;
580 }
581
582 static void reset_sccr1(struct driver_data *drv_data)
583 {
584 struct chip_data *chip =
585 spi_get_ctldata(drv_data->controller->cur_msg->spi);
586 u32 sccr1_reg;
587
588 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
589 switch (drv_data->ssp_type) {
590 case QUARK_X1000_SSP:
591 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
592 break;
593 case CE4100_SSP:
594 sccr1_reg &= ~CE4100_SSCR1_RFT;
595 break;
596 default:
597 sccr1_reg &= ~SSCR1_RFT;
598 break;
599 }
600 sccr1_reg |= chip->threshold;
601 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
602 }
603
604 static void int_error_stop(struct driver_data *drv_data, const char* msg)
605 {
606 /* Stop and reset SSP */
607 write_SSSR_CS(drv_data, drv_data->clear_sr);
608 reset_sccr1(drv_data);
609 if (!pxa25x_ssp_comp(drv_data))
610 pxa2xx_spi_write(drv_data, SSTO, 0);
611 pxa2xx_spi_flush(drv_data);
612 pxa2xx_spi_write(drv_data, SSCR0,
613 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
614
615 dev_err(&drv_data->pdev->dev, "%s\n", msg);
616
617 drv_data->controller->cur_msg->status = -EIO;
618 spi_finalize_current_transfer(drv_data->controller);
619 }
620
621 static void int_transfer_complete(struct driver_data *drv_data)
622 {
623 /* Clear and disable interrupts */
624 write_SSSR_CS(drv_data, drv_data->clear_sr);
625 reset_sccr1(drv_data);
626 if (!pxa25x_ssp_comp(drv_data))
627 pxa2xx_spi_write(drv_data, SSTO, 0);
628
629 spi_finalize_current_transfer(drv_data->controller);
630 }
631
632 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
633 {
634 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
635 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
636
637 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
638
639 if (irq_status & SSSR_ROR) {
640 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
641 return IRQ_HANDLED;
642 }
643
644 if (irq_status & SSSR_TUR) {
645 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
646 return IRQ_HANDLED;
647 }
648
649 if (irq_status & SSSR_TINT) {
650 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
651 if (drv_data->read(drv_data)) {
652 int_transfer_complete(drv_data);
653 return IRQ_HANDLED;
654 }
655 }
656
657 /* Drain rx fifo, Fill tx fifo and prevent overruns */
658 do {
659 if (drv_data->read(drv_data)) {
660 int_transfer_complete(drv_data);
661 return IRQ_HANDLED;
662 }
663 } while (drv_data->write(drv_data));
664
665 if (drv_data->read(drv_data)) {
666 int_transfer_complete(drv_data);
667 return IRQ_HANDLED;
668 }
669
670 if (drv_data->tx == drv_data->tx_end) {
671 u32 bytes_left;
672 u32 sccr1_reg;
673
674 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
675 sccr1_reg &= ~SSCR1_TIE;
676
677 /*
678 * PXA25x_SSP has no timeout, set up rx threshould for the
679 * remaining RX bytes.
680 */
681 if (pxa25x_ssp_comp(drv_data)) {
682 u32 rx_thre;
683
684 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
685
686 bytes_left = drv_data->rx_end - drv_data->rx;
687 switch (drv_data->n_bytes) {
688 case 4:
689 bytes_left >>= 2;
690 break;
691 case 2:
692 bytes_left >>= 1;
693 break;
694 }
695
696 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
697 if (rx_thre > bytes_left)
698 rx_thre = bytes_left;
699
700 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
701 }
702 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
703 }
704
705 /* We did something */
706 return IRQ_HANDLED;
707 }
708
709 static void handle_bad_msg(struct driver_data *drv_data)
710 {
711 pxa2xx_spi_write(drv_data, SSCR0,
712 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
713 pxa2xx_spi_write(drv_data, SSCR1,
714 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
715 if (!pxa25x_ssp_comp(drv_data))
716 pxa2xx_spi_write(drv_data, SSTO, 0);
717 write_SSSR_CS(drv_data, drv_data->clear_sr);
718
719 dev_err(&drv_data->pdev->dev,
720 "bad message state in interrupt handler\n");
721 }
722
723 static irqreturn_t ssp_int(int irq, void *dev_id)
724 {
725 struct driver_data *drv_data = dev_id;
726 u32 sccr1_reg;
727 u32 mask = drv_data->mask_sr;
728 u32 status;
729
730 /*
731 * The IRQ might be shared with other peripherals so we must first
732 * check that are we RPM suspended or not. If we are we assume that
733 * the IRQ was not for us (we shouldn't be RPM suspended when the
734 * interrupt is enabled).
735 */
736 if (pm_runtime_suspended(&drv_data->pdev->dev))
737 return IRQ_NONE;
738
739 /*
740 * If the device is not yet in RPM suspended state and we get an
741 * interrupt that is meant for another device, check if status bits
742 * are all set to one. That means that the device is already
743 * powered off.
744 */
745 status = pxa2xx_spi_read(drv_data, SSSR);
746 if (status == ~0)
747 return IRQ_NONE;
748
749 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
750
751 /* Ignore possible writes if we don't need to write */
752 if (!(sccr1_reg & SSCR1_TIE))
753 mask &= ~SSSR_TFS;
754
755 /* Ignore RX timeout interrupt if it is disabled */
756 if (!(sccr1_reg & SSCR1_TINTE))
757 mask &= ~SSSR_TINT;
758
759 if (!(status & mask))
760 return IRQ_NONE;
761
762 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
764
765 if (!drv_data->controller->cur_msg) {
766 handle_bad_msg(drv_data);
767 /* Never fail */
768 return IRQ_HANDLED;
769 }
770
771 return drv_data->transfer_handler(drv_data);
772 }
773
774 /*
775 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
776 * input frequency by fractions of 2^24. It also has a divider by 5.
777 *
778 * There are formulas to get baud rate value for given input frequency and
779 * divider parameters, such as DDS_CLK_RATE and SCR:
780 *
781 * Fsys = 200MHz
782 *
783 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
784 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
785 *
786 * DDS_CLK_RATE either 2^n or 2^n / 5.
787 * SCR is in range 0 .. 255
788 *
789 * Divisor = 5^i * 2^j * 2 * k
790 * i = [0, 1] i = 1 iff j = 0 or j > 3
791 * j = [0, 23] j = 0 iff i = 1
792 * k = [1, 256]
793 * Special case: j = 0, i = 1: Divisor = 2 / 5
794 *
795 * Accordingly to the specification the recommended values for DDS_CLK_RATE
796 * are:
797 * Case 1: 2^n, n = [0, 23]
798 * Case 2: 2^24 * 2 / 5 (0x666666)
799 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
800 *
801 * In all cases the lowest possible value is better.
802 *
803 * The function calculates parameters for all cases and chooses the one closest
804 * to the asked baud rate.
805 */
806 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
807 {
808 unsigned long xtal = 200000000;
809 unsigned long fref = xtal / 2; /* mandatory division by 2,
810 see (2) */
811 /* case 3 */
812 unsigned long fref1 = fref / 2; /* case 1 */
813 unsigned long fref2 = fref * 2 / 5; /* case 2 */
814 unsigned long scale;
815 unsigned long q, q1, q2;
816 long r, r1, r2;
817 u32 mul;
818
819 /* Case 1 */
820
821 /* Set initial value for DDS_CLK_RATE */
822 mul = (1 << 24) >> 1;
823
824 /* Calculate initial quot */
825 q1 = DIV_ROUND_UP(fref1, rate);
826
827 /* Scale q1 if it's too big */
828 if (q1 > 256) {
829 /* Scale q1 to range [1, 512] */
830 scale = fls_long(q1 - 1);
831 if (scale > 9) {
832 q1 >>= scale - 9;
833 mul >>= scale - 9;
834 }
835
836 /* Round the result if we have a remainder */
837 q1 += q1 & 1;
838 }
839
840 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
841 scale = __ffs(q1);
842 q1 >>= scale;
843 mul >>= scale;
844
845 /* Get the remainder */
846 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
847
848 /* Case 2 */
849
850 q2 = DIV_ROUND_UP(fref2, rate);
851 r2 = abs(fref2 / q2 - rate);
852
853 /*
854 * Choose the best between two: less remainder we have the better. We
855 * can't go case 2 if q2 is greater than 256 since SCR register can
856 * hold only values 0 .. 255.
857 */
858 if (r2 >= r1 || q2 > 256) {
859 /* case 1 is better */
860 r = r1;
861 q = q1;
862 } else {
863 /* case 2 is better */
864 r = r2;
865 q = q2;
866 mul = (1 << 24) * 2 / 5;
867 }
868
869 /* Check case 3 only if the divisor is big enough */
870 if (fref / rate >= 80) {
871 u64 fssp;
872 u32 m;
873
874 /* Calculate initial quot */
875 q1 = DIV_ROUND_UP(fref, rate);
876 m = (1 << 24) / q1;
877
878 /* Get the remainder */
879 fssp = (u64)fref * m;
880 do_div(fssp, 1 << 24);
881 r1 = abs(fssp - rate);
882
883 /* Choose this one if it suits better */
884 if (r1 < r) {
885 /* case 3 is better */
886 q = 1;
887 mul = m;
888 }
889 }
890
891 *dds = mul;
892 return q - 1;
893 }
894
895 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
896 {
897 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
898 const struct ssp_device *ssp = drv_data->ssp;
899
900 rate = min_t(int, ssp_clk, rate);
901
902 /*
903 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
904 * that the SSP transmission rate can be greater than the device rate
905 */
906 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
907 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
908 else
909 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
910 }
911
912 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
913 int rate)
914 {
915 struct chip_data *chip =
916 spi_get_ctldata(drv_data->controller->cur_msg->spi);
917 unsigned int clk_div;
918
919 switch (drv_data->ssp_type) {
920 case QUARK_X1000_SSP:
921 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
922 break;
923 default:
924 clk_div = ssp_get_clk_div(drv_data, rate);
925 break;
926 }
927 return clk_div << 8;
928 }
929
930 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
931 struct spi_device *spi,
932 struct spi_transfer *xfer)
933 {
934 struct chip_data *chip = spi_get_ctldata(spi);
935
936 return chip->enable_dma &&
937 xfer->len <= MAX_DMA_LEN &&
938 xfer->len >= chip->dma_burst_size;
939 }
940
941 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
942 struct spi_device *spi,
943 struct spi_transfer *transfer)
944 {
945 struct driver_data *drv_data = spi_controller_get_devdata(controller);
946 struct spi_message *message = controller->cur_msg;
947 struct chip_data *chip = spi_get_ctldata(spi);
948 u32 dma_thresh = chip->dma_threshold;
949 u32 dma_burst = chip->dma_burst_size;
950 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
951 u32 clk_div;
952 u8 bits;
953 u32 speed;
954 u32 cr0;
955 u32 cr1;
956 int err;
957 int dma_mapped;
958
959 /* Check if we can DMA this transfer */
960 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
961
962 /* reject already-mapped transfers; PIO won't always work */
963 if (message->is_dma_mapped
964 || transfer->rx_dma || transfer->tx_dma) {
965 dev_err(&spi->dev,
966 "Mapped transfer length of %u is greater than %d\n",
967 transfer->len, MAX_DMA_LEN);
968 return -EINVAL;
969 }
970
971 /* warn ... we force this to PIO mode */
972 dev_warn_ratelimited(&spi->dev,
973 "DMA disabled for transfer length %ld greater than %d\n",
974 (long)transfer->len, MAX_DMA_LEN);
975 }
976
977 /* Setup the transfer state based on the type of transfer */
978 if (pxa2xx_spi_flush(drv_data) == 0) {
979 dev_err(&spi->dev, "Flush failed\n");
980 return -EIO;
981 }
982 drv_data->n_bytes = chip->n_bytes;
983 drv_data->tx = (void *)transfer->tx_buf;
984 drv_data->tx_end = drv_data->tx + transfer->len;
985 drv_data->rx = transfer->rx_buf;
986 drv_data->rx_end = drv_data->rx + transfer->len;
987 drv_data->write = drv_data->tx ? chip->write : null_writer;
988 drv_data->read = drv_data->rx ? chip->read : null_reader;
989
990 /* Change speed and bit per word on a per transfer */
991 bits = transfer->bits_per_word;
992 speed = transfer->speed_hz;
993
994 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
995
996 if (bits <= 8) {
997 drv_data->n_bytes = 1;
998 drv_data->read = drv_data->read != null_reader ?
999 u8_reader : null_reader;
1000 drv_data->write = drv_data->write != null_writer ?
1001 u8_writer : null_writer;
1002 } else if (bits <= 16) {
1003 drv_data->n_bytes = 2;
1004 drv_data->read = drv_data->read != null_reader ?
1005 u16_reader : null_reader;
1006 drv_data->write = drv_data->write != null_writer ?
1007 u16_writer : null_writer;
1008 } else if (bits <= 32) {
1009 drv_data->n_bytes = 4;
1010 drv_data->read = drv_data->read != null_reader ?
1011 u32_reader : null_reader;
1012 drv_data->write = drv_data->write != null_writer ?
1013 u32_writer : null_writer;
1014 }
1015 /*
1016 * if bits/word is changed in dma mode, then must check the
1017 * thresholds and burst also
1018 */
1019 if (chip->enable_dma) {
1020 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1021 spi,
1022 bits, &dma_burst,
1023 &dma_thresh))
1024 dev_warn_ratelimited(&spi->dev,
1025 "DMA burst size reduced to match bits_per_word\n");
1026 }
1027
1028 dma_mapped = controller->can_dma &&
1029 controller->can_dma(controller, spi, transfer) &&
1030 controller->cur_msg_mapped;
1031 if (dma_mapped) {
1032
1033 /* Ensure we have the correct interrupt handler */
1034 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1035
1036 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1037 if (err)
1038 return err;
1039
1040 /* Clear status and start DMA engine */
1041 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1042 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1043
1044 pxa2xx_spi_dma_start(drv_data);
1045 } else {
1046 /* Ensure we have the correct interrupt handler */
1047 drv_data->transfer_handler = interrupt_transfer;
1048
1049 /* Clear status */
1050 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1051 write_SSSR_CS(drv_data, drv_data->clear_sr);
1052 }
1053
1054 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1055 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1056 if (!pxa25x_ssp_comp(drv_data))
1057 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1058 controller->max_speed_hz
1059 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1060 dma_mapped ? "DMA" : "PIO");
1061 else
1062 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1063 controller->max_speed_hz / 2
1064 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1065 dma_mapped ? "DMA" : "PIO");
1066
1067 if (is_lpss_ssp(drv_data)) {
1068 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1069 != chip->lpss_rx_threshold)
1070 pxa2xx_spi_write(drv_data, SSIRF,
1071 chip->lpss_rx_threshold);
1072 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1073 != chip->lpss_tx_threshold)
1074 pxa2xx_spi_write(drv_data, SSITF,
1075 chip->lpss_tx_threshold);
1076 }
1077
1078 if (is_quark_x1000_ssp(drv_data) &&
1079 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1080 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1081
1082 /* see if we need to reload the config registers */
1083 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1084 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1085 != (cr1 & change_mask)) {
1086 /* stop the SSP, and update the other bits */
1087 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1088 if (!pxa25x_ssp_comp(drv_data))
1089 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1090 /* first set CR1 without interrupt and service enables */
1091 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1092 /* restart the SSP */
1093 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1094
1095 } else {
1096 if (!pxa25x_ssp_comp(drv_data))
1097 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1098 }
1099
1100 if (drv_data->ssp_type == MMP2_SSP) {
1101 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1102 & SSSR_TFL_MASK) >> 8;
1103
1104 if (tx_level) {
1105 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1106 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1107 tx_level);
1108 if (tx_level > transfer->len)
1109 tx_level = transfer->len;
1110 drv_data->tx += tx_level;
1111 }
1112 }
1113
1114 if (spi_controller_is_slave(controller)) {
1115 while (drv_data->write(drv_data))
1116 ;
1117 if (drv_data->gpiod_ready) {
1118 gpiod_set_value(drv_data->gpiod_ready, 1);
1119 udelay(1);
1120 gpiod_set_value(drv_data->gpiod_ready, 0);
1121 }
1122 }
1123
1124 /*
1125 * Release the data by enabling service requests and interrupts,
1126 * without changing any mode bits
1127 */
1128 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1129
1130 return 1;
1131 }
1132
1133 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1134 {
1135 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1136
1137 /* Stop and reset SSP */
1138 write_SSSR_CS(drv_data, drv_data->clear_sr);
1139 reset_sccr1(drv_data);
1140 if (!pxa25x_ssp_comp(drv_data))
1141 pxa2xx_spi_write(drv_data, SSTO, 0);
1142 pxa2xx_spi_flush(drv_data);
1143 pxa2xx_spi_write(drv_data, SSCR0,
1144 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1145
1146 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1147
1148 drv_data->controller->cur_msg->status = -EINTR;
1149 spi_finalize_current_transfer(drv_data->controller);
1150
1151 return 0;
1152 }
1153
1154 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1155 struct spi_message *msg)
1156 {
1157 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1158
1159 /* Disable the SSP */
1160 pxa2xx_spi_write(drv_data, SSCR0,
1161 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1162 /* Clear and disable interrupts and service requests */
1163 write_SSSR_CS(drv_data, drv_data->clear_sr);
1164 pxa2xx_spi_write(drv_data, SSCR1,
1165 pxa2xx_spi_read(drv_data, SSCR1)
1166 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1167 if (!pxa25x_ssp_comp(drv_data))
1168 pxa2xx_spi_write(drv_data, SSTO, 0);
1169
1170 /*
1171 * Stop the DMA if running. Note DMA callback handler may have unset
1172 * the dma_running already, which is fine as stopping is not needed
1173 * then but we shouldn't rely this flag for anything else than
1174 * stopping. For instance to differentiate between PIO and DMA
1175 * transfers.
1176 */
1177 if (atomic_read(&drv_data->dma_running))
1178 pxa2xx_spi_dma_stop(drv_data);
1179 }
1180
1181 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1182 {
1183 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1184
1185 /* Disable the SSP now */
1186 pxa2xx_spi_write(drv_data, SSCR0,
1187 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1188
1189 return 0;
1190 }
1191
1192 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1193 struct pxa2xx_spi_chip *chip_info)
1194 {
1195 struct driver_data *drv_data =
1196 spi_controller_get_devdata(spi->controller);
1197 struct gpio_desc *gpiod;
1198 int err = 0;
1199
1200 if (chip == NULL)
1201 return 0;
1202
1203 if (drv_data->cs_gpiods) {
1204 gpiod = drv_data->cs_gpiods[spi->chip_select];
1205 if (gpiod) {
1206 chip->gpiod_cs = gpiod;
1207 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1208 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1209 }
1210
1211 return 0;
1212 }
1213
1214 if (chip_info == NULL)
1215 return 0;
1216
1217 /* NOTE: setup() can be called multiple times, possibly with
1218 * different chip_info, release previously requested GPIO
1219 */
1220 if (chip->gpiod_cs) {
1221 gpiod_put(chip->gpiod_cs);
1222 chip->gpiod_cs = NULL;
1223 }
1224
1225 /* If (*cs_control) is provided, ignore GPIO chip select */
1226 if (chip_info->cs_control) {
1227 chip->cs_control = chip_info->cs_control;
1228 return 0;
1229 }
1230
1231 if (gpio_is_valid(chip_info->gpio_cs)) {
1232 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1233 if (err) {
1234 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1235 chip_info->gpio_cs);
1236 return err;
1237 }
1238
1239 gpiod = gpio_to_desc(chip_info->gpio_cs);
1240 chip->gpiod_cs = gpiod;
1241 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1242
1243 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1244 }
1245
1246 return err;
1247 }
1248
1249 static int setup(struct spi_device *spi)
1250 {
1251 struct pxa2xx_spi_chip *chip_info;
1252 struct chip_data *chip;
1253 const struct lpss_config *config;
1254 struct driver_data *drv_data =
1255 spi_controller_get_devdata(spi->controller);
1256 uint tx_thres, tx_hi_thres, rx_thres;
1257
1258 switch (drv_data->ssp_type) {
1259 case QUARK_X1000_SSP:
1260 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1261 tx_hi_thres = 0;
1262 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1263 break;
1264 case CE4100_SSP:
1265 tx_thres = TX_THRESH_CE4100_DFLT;
1266 tx_hi_thres = 0;
1267 rx_thres = RX_THRESH_CE4100_DFLT;
1268 break;
1269 case LPSS_LPT_SSP:
1270 case LPSS_BYT_SSP:
1271 case LPSS_BSW_SSP:
1272 case LPSS_SPT_SSP:
1273 case LPSS_BXT_SSP:
1274 case LPSS_CNL_SSP:
1275 config = lpss_get_config(drv_data);
1276 tx_thres = config->tx_threshold_lo;
1277 tx_hi_thres = config->tx_threshold_hi;
1278 rx_thres = config->rx_threshold;
1279 break;
1280 default:
1281 tx_hi_thres = 0;
1282 if (spi_controller_is_slave(drv_data->controller)) {
1283 tx_thres = 1;
1284 rx_thres = 2;
1285 } else {
1286 tx_thres = TX_THRESH_DFLT;
1287 rx_thres = RX_THRESH_DFLT;
1288 }
1289 break;
1290 }
1291
1292 /* Only alloc on first setup */
1293 chip = spi_get_ctldata(spi);
1294 if (!chip) {
1295 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1296 if (!chip)
1297 return -ENOMEM;
1298
1299 if (drv_data->ssp_type == CE4100_SSP) {
1300 if (spi->chip_select > 4) {
1301 dev_err(&spi->dev,
1302 "failed setup: cs number must not be > 4.\n");
1303 kfree(chip);
1304 return -EINVAL;
1305 }
1306
1307 chip->frm = spi->chip_select;
1308 }
1309 chip->enable_dma = drv_data->controller_info->enable_dma;
1310 chip->timeout = TIMOUT_DFLT;
1311 }
1312
1313 /* protocol drivers may change the chip settings, so...
1314 * if chip_info exists, use it */
1315 chip_info = spi->controller_data;
1316
1317 /* chip_info isn't always needed */
1318 chip->cr1 = 0;
1319 if (chip_info) {
1320 if (chip_info->timeout)
1321 chip->timeout = chip_info->timeout;
1322 if (chip_info->tx_threshold)
1323 tx_thres = chip_info->tx_threshold;
1324 if (chip_info->tx_hi_threshold)
1325 tx_hi_thres = chip_info->tx_hi_threshold;
1326 if (chip_info->rx_threshold)
1327 rx_thres = chip_info->rx_threshold;
1328 chip->dma_threshold = 0;
1329 if (chip_info->enable_loopback)
1330 chip->cr1 = SSCR1_LBM;
1331 }
1332 if (spi_controller_is_slave(drv_data->controller)) {
1333 chip->cr1 |= SSCR1_SCFR;
1334 chip->cr1 |= SSCR1_SCLKDIR;
1335 chip->cr1 |= SSCR1_SFRMDIR;
1336 chip->cr1 |= SSCR1_SPH;
1337 }
1338
1339 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1340 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1341 | SSITF_TxHiThresh(tx_hi_thres);
1342
1343 /* set dma burst and threshold outside of chip_info path so that if
1344 * chip_info goes away after setting chip->enable_dma, the
1345 * burst and threshold can still respond to changes in bits_per_word */
1346 if (chip->enable_dma) {
1347 /* set up legal burst and threshold for dma */
1348 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1349 spi->bits_per_word,
1350 &chip->dma_burst_size,
1351 &chip->dma_threshold)) {
1352 dev_warn(&spi->dev,
1353 "in setup: DMA burst size reduced to match bits_per_word\n");
1354 }
1355 dev_dbg(&spi->dev,
1356 "in setup: DMA burst size set to %u\n",
1357 chip->dma_burst_size);
1358 }
1359
1360 switch (drv_data->ssp_type) {
1361 case QUARK_X1000_SSP:
1362 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1363 & QUARK_X1000_SSCR1_RFT)
1364 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1365 & QUARK_X1000_SSCR1_TFT);
1366 break;
1367 case CE4100_SSP:
1368 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1369 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1370 break;
1371 default:
1372 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1373 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1374 break;
1375 }
1376
1377 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1378 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1379 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1380
1381 if (spi->mode & SPI_LOOP)
1382 chip->cr1 |= SSCR1_LBM;
1383
1384 if (spi->bits_per_word <= 8) {
1385 chip->n_bytes = 1;
1386 chip->read = u8_reader;
1387 chip->write = u8_writer;
1388 } else if (spi->bits_per_word <= 16) {
1389 chip->n_bytes = 2;
1390 chip->read = u16_reader;
1391 chip->write = u16_writer;
1392 } else if (spi->bits_per_word <= 32) {
1393 chip->n_bytes = 4;
1394 chip->read = u32_reader;
1395 chip->write = u32_writer;
1396 }
1397
1398 spi_set_ctldata(spi, chip);
1399
1400 if (drv_data->ssp_type == CE4100_SSP)
1401 return 0;
1402
1403 return setup_cs(spi, chip, chip_info);
1404 }
1405
1406 static void cleanup(struct spi_device *spi)
1407 {
1408 struct chip_data *chip = spi_get_ctldata(spi);
1409 struct driver_data *drv_data =
1410 spi_controller_get_devdata(spi->controller);
1411
1412 if (!chip)
1413 return;
1414
1415 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1416 chip->gpiod_cs)
1417 gpiod_put(chip->gpiod_cs);
1418
1419 kfree(chip);
1420 }
1421
1422 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1423 { "INT33C0", LPSS_LPT_SSP },
1424 { "INT33C1", LPSS_LPT_SSP },
1425 { "INT3430", LPSS_LPT_SSP },
1426 { "INT3431", LPSS_LPT_SSP },
1427 { "80860F0E", LPSS_BYT_SSP },
1428 { "8086228E", LPSS_BSW_SSP },
1429 { },
1430 };
1431 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1432
1433 /*
1434 * PCI IDs of compound devices that integrate both host controller and private
1435 * integrated DMA engine. Please note these are not used in module
1436 * autoloading and probing in this module but matching the LPSS SSP type.
1437 */
1438 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1439 /* SPT-LP */
1440 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1441 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1442 /* SPT-H */
1443 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1444 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1445 /* KBL-H */
1446 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1447 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1448 /* BXT A-Step */
1449 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1450 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1451 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1452 /* BXT B-Step */
1453 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1454 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1455 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1456 /* GLK */
1457 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1458 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1459 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1460 /* ICL-LP */
1461 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1462 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1463 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1464 /* EHL */
1465 { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1466 { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1467 { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1468 /* JSL */
1469 { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1470 { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1471 { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1472 /* APL */
1473 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1474 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1475 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1476 /* CNL-LP */
1477 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1478 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1479 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1480 /* CNL-H */
1481 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1482 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1483 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1484 /* CML-LP */
1485 { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1486 { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1487 { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1488 /* CML-H */
1489 { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1490 { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1491 { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1492 /* TGL-LP */
1493 { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1494 { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1495 { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1496 { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1497 { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1498 { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1499 { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1500 { },
1501 };
1502
1503 static const struct of_device_id pxa2xx_spi_of_match[] = {
1504 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1505 {},
1506 };
1507 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1508
1509 #ifdef CONFIG_ACPI
1510
1511 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1512 {
1513 unsigned int devid;
1514 int port_id = -1;
1515
1516 if (adev && adev->pnp.unique_id &&
1517 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1518 port_id = devid;
1519 return port_id;
1520 }
1521
1522 #else /* !CONFIG_ACPI */
1523
1524 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1525 {
1526 return -1;
1527 }
1528
1529 #endif /* CONFIG_ACPI */
1530
1531
1532 #ifdef CONFIG_PCI
1533
1534 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1535 {
1536 return param == chan->device->dev;
1537 }
1538
1539 #endif /* CONFIG_PCI */
1540
1541 static struct pxa2xx_spi_controller *
1542 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1543 {
1544 struct pxa2xx_spi_controller *pdata;
1545 struct acpi_device *adev;
1546 struct ssp_device *ssp;
1547 struct resource *res;
1548 const struct acpi_device_id *adev_id = NULL;
1549 const struct pci_device_id *pcidev_id = NULL;
1550 const struct of_device_id *of_id = NULL;
1551 enum pxa_ssp_type type;
1552
1553 adev = ACPI_COMPANION(&pdev->dev);
1554
1555 if (pdev->dev.of_node)
1556 of_id = of_match_device(pdev->dev.driver->of_match_table,
1557 &pdev->dev);
1558 else if (dev_is_pci(pdev->dev.parent))
1559 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1560 to_pci_dev(pdev->dev.parent));
1561 else if (adev)
1562 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1563 &pdev->dev);
1564 else
1565 return NULL;
1566
1567 if (adev_id)
1568 type = (enum pxa_ssp_type)adev_id->driver_data;
1569 else if (pcidev_id)
1570 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1571 else if (of_id)
1572 type = (enum pxa_ssp_type)of_id->data;
1573 else
1574 return NULL;
1575
1576 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1577 if (!pdata)
1578 return NULL;
1579
1580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1581 if (!res)
1582 return NULL;
1583
1584 ssp = &pdata->ssp;
1585
1586 ssp->phys_base = res->start;
1587 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1588 if (IS_ERR(ssp->mmio_base))
1589 return NULL;
1590
1591 #ifdef CONFIG_PCI
1592 if (pcidev_id) {
1593 pdata->tx_param = pdev->dev.parent;
1594 pdata->rx_param = pdev->dev.parent;
1595 pdata->dma_filter = pxa2xx_spi_idma_filter;
1596 }
1597 #endif
1598
1599 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1600 if (IS_ERR(ssp->clk))
1601 return NULL;
1602
1603 ssp->irq = platform_get_irq(pdev, 0);
1604 if (ssp->irq < 0)
1605 return NULL;
1606
1607 ssp->type = type;
1608 ssp->pdev = pdev;
1609 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1610
1611 pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
1612 pdata->num_chipselect = 1;
1613 pdata->enable_dma = true;
1614 pdata->dma_burst_size = 1;
1615
1616 return pdata;
1617 }
1618
1619 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1620 unsigned int cs)
1621 {
1622 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1623
1624 if (has_acpi_companion(&drv_data->pdev->dev)) {
1625 switch (drv_data->ssp_type) {
1626 /*
1627 * For Atoms the ACPI DeviceSelection used by the Windows
1628 * driver starts from 1 instead of 0 so translate it here
1629 * to match what Linux expects.
1630 */
1631 case LPSS_BYT_SSP:
1632 case LPSS_BSW_SSP:
1633 return cs - 1;
1634
1635 default:
1636 break;
1637 }
1638 }
1639
1640 return cs;
1641 }
1642
1643 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1644 {
1645 return MAX_DMA_LEN;
1646 }
1647
1648 static int pxa2xx_spi_probe(struct platform_device *pdev)
1649 {
1650 struct device *dev = &pdev->dev;
1651 struct pxa2xx_spi_controller *platform_info;
1652 struct spi_controller *controller;
1653 struct driver_data *drv_data;
1654 struct ssp_device *ssp;
1655 const struct lpss_config *config;
1656 int status, count;
1657 u32 tmp;
1658
1659 platform_info = dev_get_platdata(dev);
1660 if (!platform_info) {
1661 platform_info = pxa2xx_spi_init_pdata(pdev);
1662 if (!platform_info) {
1663 dev_err(&pdev->dev, "missing platform data\n");
1664 return -ENODEV;
1665 }
1666 }
1667
1668 ssp = pxa_ssp_request(pdev->id, pdev->name);
1669 if (!ssp)
1670 ssp = &platform_info->ssp;
1671
1672 if (!ssp->mmio_base) {
1673 dev_err(&pdev->dev, "failed to get ssp\n");
1674 return -ENODEV;
1675 }
1676
1677 if (platform_info->is_slave)
1678 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1679 else
1680 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1681
1682 if (!controller) {
1683 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1684 pxa_ssp_free(ssp);
1685 return -ENOMEM;
1686 }
1687 drv_data = spi_controller_get_devdata(controller);
1688 drv_data->controller = controller;
1689 drv_data->controller_info = platform_info;
1690 drv_data->pdev = pdev;
1691 drv_data->ssp = ssp;
1692
1693 controller->dev.of_node = pdev->dev.of_node;
1694 /* the spi->mode bits understood by this driver: */
1695 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1696
1697 controller->bus_num = ssp->port_id;
1698 controller->dma_alignment = DMA_ALIGNMENT;
1699 controller->cleanup = cleanup;
1700 controller->setup = setup;
1701 controller->set_cs = pxa2xx_spi_set_cs;
1702 controller->transfer_one = pxa2xx_spi_transfer_one;
1703 controller->slave_abort = pxa2xx_spi_slave_abort;
1704 controller->handle_err = pxa2xx_spi_handle_err;
1705 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1706 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1707 controller->auto_runtime_pm = true;
1708 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1709
1710 drv_data->ssp_type = ssp->type;
1711
1712 drv_data->ioaddr = ssp->mmio_base;
1713 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1714 if (pxa25x_ssp_comp(drv_data)) {
1715 switch (drv_data->ssp_type) {
1716 case QUARK_X1000_SSP:
1717 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1718 break;
1719 default:
1720 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1721 break;
1722 }
1723
1724 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1725 drv_data->dma_cr1 = 0;
1726 drv_data->clear_sr = SSSR_ROR;
1727 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1728 } else {
1729 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1730 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1731 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1732 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1733 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1734 | SSSR_ROR | SSSR_TUR;
1735 }
1736
1737 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1738 drv_data);
1739 if (status < 0) {
1740 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1741 goto out_error_controller_alloc;
1742 }
1743
1744 /* Setup DMA if requested */
1745 if (platform_info->enable_dma) {
1746 status = pxa2xx_spi_dma_setup(drv_data);
1747 if (status) {
1748 dev_warn(dev, "no DMA channels available, using PIO\n");
1749 platform_info->enable_dma = false;
1750 } else {
1751 controller->can_dma = pxa2xx_spi_can_dma;
1752 controller->max_dma_len = MAX_DMA_LEN;
1753 controller->max_transfer_size =
1754 pxa2xx_spi_max_dma_transfer_size;
1755 }
1756 }
1757
1758 /* Enable SOC clock */
1759 status = clk_prepare_enable(ssp->clk);
1760 if (status)
1761 goto out_error_dma_irq_alloc;
1762
1763 controller->max_speed_hz = clk_get_rate(ssp->clk);
1764 /*
1765 * Set minimum speed for all other platforms than Intel Quark which is
1766 * able do under 1 Hz transfers.
1767 */
1768 if (!pxa25x_ssp_comp(drv_data))
1769 controller->min_speed_hz =
1770 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1771 else if (!is_quark_x1000_ssp(drv_data))
1772 controller->min_speed_hz =
1773 DIV_ROUND_UP(controller->max_speed_hz, 512);
1774
1775 /* Load default SSP configuration */
1776 pxa2xx_spi_write(drv_data, SSCR0, 0);
1777 switch (drv_data->ssp_type) {
1778 case QUARK_X1000_SSP:
1779 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1780 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1781 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1782
1783 /* using the Motorola SPI protocol and use 8 bit frame */
1784 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1785 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1786 break;
1787 case CE4100_SSP:
1788 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1789 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1790 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1791 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1792 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1793 break;
1794 default:
1795
1796 if (spi_controller_is_slave(controller)) {
1797 tmp = SSCR1_SCFR |
1798 SSCR1_SCLKDIR |
1799 SSCR1_SFRMDIR |
1800 SSCR1_RxTresh(2) |
1801 SSCR1_TxTresh(1) |
1802 SSCR1_SPH;
1803 } else {
1804 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1805 SSCR1_TxTresh(TX_THRESH_DFLT);
1806 }
1807 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1808 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1809 if (!spi_controller_is_slave(controller))
1810 tmp |= SSCR0_SCR(2);
1811 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1812 break;
1813 }
1814
1815 if (!pxa25x_ssp_comp(drv_data))
1816 pxa2xx_spi_write(drv_data, SSTO, 0);
1817
1818 if (!is_quark_x1000_ssp(drv_data))
1819 pxa2xx_spi_write(drv_data, SSPSP, 0);
1820
1821 if (is_lpss_ssp(drv_data)) {
1822 lpss_ssp_setup(drv_data);
1823 config = lpss_get_config(drv_data);
1824 if (config->reg_capabilities >= 0) {
1825 tmp = __lpss_ssp_read_priv(drv_data,
1826 config->reg_capabilities);
1827 tmp &= LPSS_CAPS_CS_EN_MASK;
1828 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1829 platform_info->num_chipselect = ffz(tmp);
1830 } else if (config->cs_num) {
1831 platform_info->num_chipselect = config->cs_num;
1832 }
1833 }
1834 controller->num_chipselect = platform_info->num_chipselect;
1835
1836 count = gpiod_count(&pdev->dev, "cs");
1837 if (count > 0) {
1838 int i;
1839
1840 controller->num_chipselect = max_t(int, count,
1841 controller->num_chipselect);
1842
1843 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1844 controller->num_chipselect, sizeof(struct gpio_desc *),
1845 GFP_KERNEL);
1846 if (!drv_data->cs_gpiods) {
1847 status = -ENOMEM;
1848 goto out_error_clock_enabled;
1849 }
1850
1851 for (i = 0; i < controller->num_chipselect; i++) {
1852 struct gpio_desc *gpiod;
1853
1854 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1855 if (IS_ERR(gpiod)) {
1856 /* Means use native chip select */
1857 if (PTR_ERR(gpiod) == -ENOENT)
1858 continue;
1859
1860 status = PTR_ERR(gpiod);
1861 goto out_error_clock_enabled;
1862 } else {
1863 drv_data->cs_gpiods[i] = gpiod;
1864 }
1865 }
1866 }
1867
1868 if (platform_info->is_slave) {
1869 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1870 "ready", GPIOD_OUT_LOW);
1871 if (IS_ERR(drv_data->gpiod_ready)) {
1872 status = PTR_ERR(drv_data->gpiod_ready);
1873 goto out_error_clock_enabled;
1874 }
1875 }
1876
1877 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1878 pm_runtime_use_autosuspend(&pdev->dev);
1879 pm_runtime_set_active(&pdev->dev);
1880 pm_runtime_enable(&pdev->dev);
1881
1882 /* Register with the SPI framework */
1883 platform_set_drvdata(pdev, drv_data);
1884 status = spi_register_controller(controller);
1885 if (status != 0) {
1886 dev_err(&pdev->dev, "problem registering spi controller\n");
1887 goto out_error_pm_runtime_enabled;
1888 }
1889
1890 return status;
1891
1892 out_error_pm_runtime_enabled:
1893 pm_runtime_disable(&pdev->dev);
1894
1895 out_error_clock_enabled:
1896 clk_disable_unprepare(ssp->clk);
1897
1898 out_error_dma_irq_alloc:
1899 pxa2xx_spi_dma_release(drv_data);
1900 free_irq(ssp->irq, drv_data);
1901
1902 out_error_controller_alloc:
1903 spi_controller_put(controller);
1904 pxa_ssp_free(ssp);
1905 return status;
1906 }
1907
1908 static int pxa2xx_spi_remove(struct platform_device *pdev)
1909 {
1910 struct driver_data *drv_data = platform_get_drvdata(pdev);
1911 struct ssp_device *ssp;
1912
1913 if (!drv_data)
1914 return 0;
1915 ssp = drv_data->ssp;
1916
1917 pm_runtime_get_sync(&pdev->dev);
1918
1919 spi_unregister_controller(drv_data->controller);
1920
1921 /* Disable the SSP at the peripheral and SOC level */
1922 pxa2xx_spi_write(drv_data, SSCR0, 0);
1923 clk_disable_unprepare(ssp->clk);
1924
1925 /* Release DMA */
1926 if (drv_data->controller_info->enable_dma)
1927 pxa2xx_spi_dma_release(drv_data);
1928
1929 pm_runtime_put_noidle(&pdev->dev);
1930 pm_runtime_disable(&pdev->dev);
1931
1932 /* Release IRQ */
1933 free_irq(ssp->irq, drv_data);
1934
1935 /* Release SSP */
1936 pxa_ssp_free(ssp);
1937
1938 return 0;
1939 }
1940
1941 #ifdef CONFIG_PM_SLEEP
1942 static int pxa2xx_spi_suspend(struct device *dev)
1943 {
1944 struct driver_data *drv_data = dev_get_drvdata(dev);
1945 struct ssp_device *ssp = drv_data->ssp;
1946 int status;
1947
1948 status = spi_controller_suspend(drv_data->controller);
1949 if (status != 0)
1950 return status;
1951 pxa2xx_spi_write(drv_data, SSCR0, 0);
1952
1953 if (!pm_runtime_suspended(dev))
1954 clk_disable_unprepare(ssp->clk);
1955
1956 return 0;
1957 }
1958
1959 static int pxa2xx_spi_resume(struct device *dev)
1960 {
1961 struct driver_data *drv_data = dev_get_drvdata(dev);
1962 struct ssp_device *ssp = drv_data->ssp;
1963 int status;
1964
1965 /* Enable the SSP clock */
1966 if (!pm_runtime_suspended(dev)) {
1967 status = clk_prepare_enable(ssp->clk);
1968 if (status)
1969 return status;
1970 }
1971
1972 /* Start the queue running */
1973 return spi_controller_resume(drv_data->controller);
1974 }
1975 #endif
1976
1977 #ifdef CONFIG_PM
1978 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1979 {
1980 struct driver_data *drv_data = dev_get_drvdata(dev);
1981
1982 clk_disable_unprepare(drv_data->ssp->clk);
1983 return 0;
1984 }
1985
1986 static int pxa2xx_spi_runtime_resume(struct device *dev)
1987 {
1988 struct driver_data *drv_data = dev_get_drvdata(dev);
1989 int status;
1990
1991 status = clk_prepare_enable(drv_data->ssp->clk);
1992 return status;
1993 }
1994 #endif
1995
1996 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1997 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1998 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1999 pxa2xx_spi_runtime_resume, NULL)
2000 };
2001
2002 static struct platform_driver driver = {
2003 .driver = {
2004 .name = "pxa2xx-spi",
2005 .pm = &pxa2xx_spi_pm_ops,
2006 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
2007 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
2008 },
2009 .probe = pxa2xx_spi_probe,
2010 .remove = pxa2xx_spi_remove,
2011 };
2012
2013 static int __init pxa2xx_spi_init(void)
2014 {
2015 return platform_driver_register(&driver);
2016 }
2017 subsys_initcall(pxa2xx_spi_init);
2018
2019 static void __exit pxa2xx_spi_exit(void)
2020 {
2021 platform_driver_unregister(&driver);
2022 }
2023 module_exit(pxa2xx_spi_exit);
2024
2025 MODULE_SOFTDEP("pre: dw_dmac");
Linux with added FPC-III support