2 * Copyright (C) 2007, 2008, Marvell International Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 #include <linux/types.h>
23 #include <linux/dmaengine.h>
24 #include <linux/interrupt.h>
27 #define MV_XOR_POOL_SIZE PAGE_SIZE
28 #define MV_XOR_SLOT_SIZE 64
29 #define MV_XOR_THRESHOLD 1
30 #define MV_XOR_MAX_CHANNELS 2
32 #define XOR_OPERATION_MODE_XOR 0
33 #define XOR_OPERATION_MODE_MEMCPY 2
35 #define XOR_CURR_DESC(chan) (chan->mmr_base + 0x210 + (chan->idx * 4))
36 #define XOR_NEXT_DESC(chan) (chan->mmr_base + 0x200 + (chan->idx * 4))
37 #define XOR_BYTE_COUNT(chan) (chan->mmr_base + 0x220 + (chan->idx * 4))
38 #define XOR_DEST_POINTER(chan) (chan->mmr_base + 0x2B0 + (chan->idx * 4))
39 #define XOR_BLOCK_SIZE(chan) (chan->mmr_base + 0x2C0 + (chan->idx * 4))
40 #define XOR_INIT_VALUE_LOW(chan) (chan->mmr_base + 0x2E0)
41 #define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_base + 0x2E4)
43 #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
44 #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
45 #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
46 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
47 #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
48 #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
49 #define XOR_INTR_MASK_VALUE 0x3F5
51 #define WINDOW_BASE(w) (0x250 + ((w) << 2))
52 #define WINDOW_SIZE(w) (0x270 + ((w) << 2))
53 #define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
54 #define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
55 #define WINDOW_OVERRIDE_CTRL(chan) (0x2A0 + ((chan) << 2))
57 struct mv_xor_device
{
58 void __iomem
*xor_base
;
59 void __iomem
*xor_high_base
;
61 struct mv_xor_chan
*channels
[MV_XOR_MAX_CHANNELS
];
65 * struct mv_xor_chan - internal representation of a XOR channel
66 * @pending: allows batching of hardware operations
67 * @lock: serializes enqueue/dequeue operations to the descriptors pool
68 * @mmr_base: memory mapped register base
69 * @idx: the index of the xor channel
70 * @chain: device chain view of the descriptors
71 * @completed_slots: slots completed by HW but still need to be acked
72 * @device: parent device
73 * @common: common dmaengine channel object members
74 * @last_used: place holder for allocation to continue from where it left off
75 * @all_slots: complete domain of slots usable by the channel
76 * @slots_allocated: records the actual size of the descriptor slot pool
77 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
81 spinlock_t lock
; /* protects the descriptor slot pool */
82 void __iomem
*mmr_base
;
85 enum dma_transaction_type current_type
;
86 struct list_head chain
;
87 struct list_head completed_slots
;
88 dma_addr_t dma_desc_pool
;
89 void *dma_desc_pool_virt
;
91 struct dma_device dmadev
;
92 struct dma_chan dmachan
;
93 struct mv_xor_desc_slot
*last_used
;
94 struct list_head all_slots
;
96 struct tasklet_struct irq_tasklet
;
98 unsigned long cleanup_time
;
99 u32 current_on_last_cleanup
;
104 * struct mv_xor_desc_slot - software descriptor
105 * @slot_node: node on the mv_xor_chan.all_slots list
106 * @chain_node: node on the mv_xor_chan.chain list
107 * @completed_node: node on the mv_xor_chan.completed_slots list
108 * @hw_desc: virtual address of the hardware descriptor chain
109 * @phys: hardware address of the hardware descriptor chain
110 * @group_head: first operation in a transaction
111 * @slot_cnt: total slots used in an transaction (group of operations)
112 * @slots_per_op: number of slots per operation
114 * @unmap_src_cnt: number of xor sources
115 * @unmap_len: transaction bytecount
116 * @tx_list: list of slots that make up a multi-descriptor transaction
117 * @async_tx: support for the async_tx api
118 * @xor_check_result: result of zero sum
119 * @crc32_result: result crc calculation
121 struct mv_xor_desc_slot
{
122 struct list_head slot_node
;
123 struct list_head chain_node
;
124 struct list_head completed_node
;
125 enum dma_transaction_type type
;
127 struct mv_xor_desc_slot
*group_head
;
134 struct list_head tx_list
;
135 struct dma_async_tx_descriptor async_tx
;
137 u32
*xor_check_result
;
141 unsigned long arrival_time
;
142 struct timer_list timeout
;
146 /* This structure describes XOR descriptor size 64bytes */
148 u32 status
; /* descriptor execution status */
149 u32 crc32_result
; /* result of CRC-32 calculation */
150 u32 desc_command
; /* type of operation to be carried out */
151 u32 phy_next_desc
; /* next descriptor address pointer */
152 u32 byte_count
; /* size of src/dst blocks in bytes */
153 u32 phy_dest_addr
; /* destination block address */
154 u32 phy_src_addr
[8]; /* source block addresses */
159 #define to_mv_sw_desc(addr_hw_desc) \
160 container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
162 #define mv_hw_desc_slot_idx(hw_desc, idx) \
163 ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
165 #define MV_XOR_MIN_BYTE_COUNT (128)
166 #define XOR_MAX_BYTE_COUNT ((16 * 1024 * 1024) - 1)
167 #define MV_XOR_MAX_BYTE_COUNT XOR_MAX_BYTE_COUNT