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ext4: reduce contention on s_orphan_lock
[linux/fpc-iii.git] / drivers / staging / octeon-usb / octeon-hcd.c
blob8b8ce7293c521eb0492afd2ce7d29c254699d19e
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Cavium Networks
7 *
8 * Some parts of the code were originally released under BSD license:
9 *
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
11 * reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
15 * met:
16 *
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
24 *
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
28 * permission.
29 *
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
33 * countries.
34 *
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
45 */
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/usb.h>
53
54 #include <linux/time.h>
55 #include <linux/delay.h>
56
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-iob-defs.h>
59
60 #include <linux/usb/hcd.h>
61
62 #include <linux/err.h>
63
64 #include <asm/octeon/octeon.h>
65 #include <asm/octeon/cvmx-helper.h>
66 #include <asm/octeon/cvmx-sysinfo.h>
67 #include <asm/octeon/cvmx-helper-board.h>
68
69 #include "octeon-hcd.h"
70
71 /**
72 * enum cvmx_usb_speed - the possible USB device speeds
73 *
74 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
75 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
76 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
77 */
78 enum cvmx_usb_speed {
79 CVMX_USB_SPEED_HIGH = 0,
80 CVMX_USB_SPEED_FULL = 1,
81 CVMX_USB_SPEED_LOW = 2,
82 };
83
84 /**
85 * enum cvmx_usb_transfer - the possible USB transfer types
86 *
87 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
88 * transfers
89 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
90 * priority periodic transfers
91 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
92 * transfers
93 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
94 * periodic transfers
95 */
96 enum cvmx_usb_transfer {
97 CVMX_USB_TRANSFER_CONTROL = 0,
98 CVMX_USB_TRANSFER_ISOCHRONOUS = 1,
99 CVMX_USB_TRANSFER_BULK = 2,
100 CVMX_USB_TRANSFER_INTERRUPT = 3,
101 };
102
103 /**
104 * enum cvmx_usb_direction - the transfer directions
105 *
106 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
107 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
108 */
109 enum cvmx_usb_direction {
110 CVMX_USB_DIRECTION_OUT,
111 CVMX_USB_DIRECTION_IN,
112 };
113
114 /**
115 * enum cvmx_usb_complete - possible callback function status codes
116 *
117 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
118 * any errors
119 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
120 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
121 * by a user call to cvmx_usb_cancel
122 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
123 * error status
124 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
125 * from the device
126 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
127 * device even after a number of retries
128 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
129 * error even after a number of retries
130 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
131 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
132 * even after a number of retries
133 */
134 enum cvmx_usb_complete {
135 CVMX_USB_COMPLETE_SUCCESS,
136 CVMX_USB_COMPLETE_SHORT,
137 CVMX_USB_COMPLETE_CANCEL,
138 CVMX_USB_COMPLETE_ERROR,
139 CVMX_USB_COMPLETE_STALL,
140 CVMX_USB_COMPLETE_XACTERR,
141 CVMX_USB_COMPLETE_DATATGLERR,
142 CVMX_USB_COMPLETE_BABBLEERR,
143 CVMX_USB_COMPLETE_FRAMEERR,
144 };
145
146 /**
147 * struct cvmx_usb_port_status - the USB port status information
148 *
149 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
150 * @port_over_current: 1 = Over current detected, 0 = Over current not
151 * detected. Octeon doesn't support over current detection.
152 * @port_powered: 1 = Port power is being supplied to the device, 0 =
153 * power is off. Octeon doesn't support turning port power
154 * off.
155 * @port_speed: Current port speed.
156 * @connected: 1 = A device is connected to the port, 0 = No device is
157 * connected.
158 * @connect_change: 1 = Device connected state changed since the last set
159 * status call.
160 */
161 struct cvmx_usb_port_status {
162 uint32_t reserved : 25;
163 uint32_t port_enabled : 1;
164 uint32_t port_over_current : 1;
165 uint32_t port_powered : 1;
166 enum cvmx_usb_speed port_speed : 2;
167 uint32_t connected : 1;
168 uint32_t connect_change : 1;
169 };
170
171 /**
172 * union cvmx_usb_control_header - the structure of a Control packet header
173 *
174 * @s.request_type: Bit 7 tells the direction: 1=IN, 0=OUT
175 * @s.request The standard usb request to make
176 * @s.value Value parameter for the request in little endian format
177 * @s.index Index for the request in little endian format
178 * @s.length Length of the data associated with this request in
179 * little endian format
180 */
181 union cvmx_usb_control_header {
182 uint64_t u64;
183 struct {
184 uint64_t request_type : 8;
185 uint64_t request : 8;
186 uint64_t value : 16;
187 uint64_t index : 16;
188 uint64_t length : 16;
189 } s;
190 };
191
192 /**
193 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
194 *
195 * @offset: This is the offset in bytes into the main buffer where this data
196 * is stored.
197 * @length: This is the length in bytes of the data.
198 * @status: This is the status of this individual packet transfer.
199 */
200 struct cvmx_usb_iso_packet {
201 int offset;
202 int length;
203 enum cvmx_usb_complete status;
204 };
205
206 /**
207 * enum cvmx_usb_initialize_flags - flags used by the initialization function
208 *
209 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
210 * as clock source at USB_XO and
211 * USB_XI.
212 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
213 * board clock source at USB_XO.
214 * USB_XI should be tied to GND.
215 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
216 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
217 * crystal
218 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
219 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
220 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
221 * data transfer use for the USB
222 */
223 enum cvmx_usb_initialize_flags {
224 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0,
225 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1,
226 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3,
227 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3,
228 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3,
229 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3,
230 /* Bits 3-4 used to encode the clock frequency */
231 CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5,
232 };
233
234 /**
235 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
236 *
237 * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
238 * actively using hardware. Do not use.
239 * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high
240 * speed pipe is in the ping state. Do not
241 * use.
242 */
243 enum cvmx_usb_pipe_flags {
244 __CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17,
245 __CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18,
246 };
247
248 /* Normal prefetch that use the pref instruction. */
249 #define CVMX_PREFETCH(address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (0))
250
251 /* Maximum number of times to retry failed transactions */
252 #define MAX_RETRIES 3
253
254 /* Maximum number of hardware channels supported by the USB block */
255 #define MAX_CHANNELS 8
256
257 /* The highest valid USB device address */
258 #define MAX_USB_ADDRESS 127
259
260 /* The highest valid USB endpoint number */
261 #define MAX_USB_ENDPOINT 15
262
263 /* The highest valid port number on a hub */
264 #define MAX_USB_HUB_PORT 15
265
266 /*
267 * The low level hardware can transfer a maximum of this number of bytes in each
268 * transfer. The field is 19 bits wide
269 */
270 #define MAX_TRANSFER_BYTES ((1<<19)-1)
271
272 /*
273 * The low level hardware can transfer a maximum of this number of packets in
274 * each transfer. The field is 10 bits wide
275 */
276 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
277
278 /**
279 * Logical transactions may take numerous low level
280 * transactions, especially when splits are concerned. This
281 * enum represents all of the possible stages a transaction can
282 * be in. Note that split completes are always even. This is so
283 * the NAK handler can backup to the previous low level
284 * transaction with a simple clearing of bit 0.
285 */
286 enum cvmx_usb_stage {
287 CVMX_USB_STAGE_NON_CONTROL,
288 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
289 CVMX_USB_STAGE_SETUP,
290 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
291 CVMX_USB_STAGE_DATA,
292 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
293 CVMX_USB_STAGE_STATUS,
294 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
295 };
296
297 /**
298 * struct cvmx_usb_transaction - describes each pending USB transaction
299 * regardless of type. These are linked together
300 * to form a list of pending requests for a pipe.
301 *
302 * @node: List node for transactions in the pipe.
303 * @type: Type of transaction, duplicated of the pipe.
304 * @flags: State flags for this transaction.
305 * @buffer: User's physical buffer address to read/write.
306 * @buffer_length: Size of the user's buffer in bytes.
307 * @control_header: For control transactions, physical address of the 8
308 * byte standard header.
309 * @iso_start_frame: For ISO transactions, the starting frame number.
310 * @iso_number_packets: For ISO transactions, the number of packets in the
311 * request.
312 * @iso_packets: For ISO transactions, the sub packets in the request.
313 * @actual_bytes: Actual bytes transfer for this transaction.
314 * @stage: For control transactions, the current stage.
315 * @urb: URB.
316 */
317 struct cvmx_usb_transaction {
318 struct list_head node;
319 enum cvmx_usb_transfer type;
320 uint64_t buffer;
321 int buffer_length;
322 uint64_t control_header;
323 int iso_start_frame;
324 int iso_number_packets;
325 struct cvmx_usb_iso_packet *iso_packets;
326 int xfersize;
327 int pktcnt;
328 int retries;
329 int actual_bytes;
330 enum cvmx_usb_stage stage;
331 struct urb *urb;
332 };
333
334 /**
335 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
336 * and some USB device. It contains a list of pending
337 * request to the device.
338 *
339 * @node: List node for pipe list
340 * @next: Pipe after this one in the list
341 * @transactions: List of pending transactions
342 * @interval: For periodic pipes, the interval between packets in
343 * frames
344 * @next_tx_frame: The next frame this pipe is allowed to transmit on
345 * @flags: State flags for this pipe
346 * @device_speed: Speed of device connected to this pipe
347 * @transfer_type: Type of transaction supported by this pipe
348 * @transfer_dir: IN or OUT. Ignored for Control
349 * @multi_count: Max packet in a row for the device
350 * @max_packet: The device's maximum packet size in bytes
351 * @device_addr: USB device address at other end of pipe
352 * @endpoint_num: USB endpoint number at other end of pipe
353 * @hub_device_addr: Hub address this device is connected to
354 * @hub_port: Hub port this device is connected to
355 * @pid_toggle: This toggles between 0/1 on every packet send to track
356 * the data pid needed
357 * @channel: Hardware DMA channel for this pipe
358 * @split_sc_frame: The low order bits of the frame number the split
359 * complete should be sent on
360 */
361 struct cvmx_usb_pipe {
362 struct list_head node;
363 struct list_head transactions;
364 uint64_t interval;
365 uint64_t next_tx_frame;
366 enum cvmx_usb_pipe_flags flags;
367 enum cvmx_usb_speed device_speed;
368 enum cvmx_usb_transfer transfer_type;
369 enum cvmx_usb_direction transfer_dir;
370 int multi_count;
371 uint16_t max_packet;
372 uint8_t device_addr;
373 uint8_t endpoint_num;
374 uint8_t hub_device_addr;
375 uint8_t hub_port;
376 uint8_t pid_toggle;
377 uint8_t channel;
378 int8_t split_sc_frame;
379 };
380
381 struct cvmx_usb_tx_fifo {
382 struct {
383 int channel;
384 int size;
385 uint64_t address;
386 } entry[MAX_CHANNELS+1];
387 int head;
388 int tail;
389 };
390
391 /**
392 * struct cvmx_usb_state - the state of the USB block
393 *
394 * init_flags: Flags passed to initialize.
395 * index: Which USB block this is for.
396 * idle_hardware_channels: Bit set for every idle hardware channel.
397 * usbcx_hprt: Stored port status so we don't need to read a CSR to
398 * determine splits.
399 * pipe_for_channel: Map channels to pipes.
400 * pipe: Storage for pipes.
401 * indent: Used by debug output to indent functions.
402 * port_status: Last port status used for change notification.
403 * idle_pipes: List of open pipes that have no transactions.
404 * active_pipes: Active pipes indexed by transfer type.
405 * frame_number: Increments every SOF interrupt for time keeping.
406 * active_split: Points to the current active split, or NULL.
407 */
408 struct cvmx_usb_state {
409 int init_flags;
410 int index;
411 int idle_hardware_channels;
412 union cvmx_usbcx_hprt usbcx_hprt;
413 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
414 int indent;
415 struct cvmx_usb_port_status port_status;
416 struct list_head idle_pipes;
417 struct list_head active_pipes[4];
418 uint64_t frame_number;
419 struct cvmx_usb_transaction *active_split;
420 struct cvmx_usb_tx_fifo periodic;
421 struct cvmx_usb_tx_fifo nonperiodic;
422 };
423
424 struct octeon_hcd {
425 spinlock_t lock;
426 struct cvmx_usb_state usb;
427 struct tasklet_struct dequeue_tasklet;
428 struct list_head dequeue_list;
429 };
430
431 /* This macro spins on a field waiting for it to reach a value */
432 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
433 ({int result; \
434 do { \
435 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
436 octeon_get_clock_rate() / 1000000; \
437 type c; \
438 while (1) { \
439 c.u32 = __cvmx_usb_read_csr32(usb, address); \
440 if (c.s.field op (value)) { \
441 result = 0; \
442 break; \
443 } else if (cvmx_get_cycle() > done) { \
444 result = -1; \
445 break; \
446 } else \
447 cvmx_wait(100); \
448 } \
449 } while (0); \
450 result; })
451
452 /*
453 * This macro logically sets a single field in a CSR. It does the sequence
454 * read, modify, and write
455 */
456 #define USB_SET_FIELD32(address, type, field, value) \
457 do { \
458 type c; \
459 c.u32 = __cvmx_usb_read_csr32(usb, address); \
460 c.s.field = value; \
461 __cvmx_usb_write_csr32(usb, address, c.u32); \
462 } while (0)
463
464 /* Returns the IO address to push/pop stuff data from the FIFOs */
465 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
466
467 /**
468 * struct octeon_temp_buffer - a bounce buffer for USB transfers
469 * @temp_buffer: the newly allocated temporary buffer (including meta-data)
470 * @orig_buffer: the original buffer passed by the USB stack
471 * @data: the newly allocated temporary buffer (excluding meta-data)
472 *
473 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
474 * the buffer is too short, we need to allocate a temporary one, and this struct
475 * represents it.
476 */
477 struct octeon_temp_buffer {
478 void *temp_buffer;
479 void *orig_buffer;
480 u8 data[0];
481 };
482
483 /**
484 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
485 * (if needed)
486 * @urb: URB.
487 * @mem_flags: Memory allocation flags.
488 *
489 * This function allocates a temporary bounce buffer whenever it's needed
490 * due to HW limitations.
491 */
492 static int octeon_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
493 {
494 struct octeon_temp_buffer *temp;
495
496 if (urb->num_sgs || urb->sg ||
497 (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) ||
498 !(urb->transfer_buffer_length % sizeof(u32)))
499 return 0;
500
501 temp = kmalloc(ALIGN(urb->transfer_buffer_length, sizeof(u32)) +
502 sizeof(*temp), mem_flags);
503 if (!temp)
504 return -ENOMEM;
505
506 temp->temp_buffer = temp;
507 temp->orig_buffer = urb->transfer_buffer;
508 if (usb_urb_dir_out(urb))
509 memcpy(temp->data, urb->transfer_buffer,
510 urb->transfer_buffer_length);
511 urb->transfer_buffer = temp->data;
512 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
513
514 return 0;
515 }
516
517 /**
518 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
519 * @urb: URB.
520 *
521 * Frees a buffer allocated by octeon_alloc_temp_buffer().
522 */
523 static void octeon_free_temp_buffer(struct urb *urb)
524 {
525 struct octeon_temp_buffer *temp;
526
527 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
528 return;
529
530 temp = container_of(urb->transfer_buffer, struct octeon_temp_buffer,
531 data);
532 if (usb_urb_dir_in(urb))
533 memcpy(temp->orig_buffer, urb->transfer_buffer,
534 urb->actual_length);
535 urb->transfer_buffer = temp->orig_buffer;
536 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
537 kfree(temp->temp_buffer);
538 }
539
540 /**
541 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
542 * @hcd: USB HCD structure.
543 * @urb: URB.
544 * @mem_flags: Memory allocation flags.
545 */
546 static int octeon_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
547 gfp_t mem_flags)
548 {
549 int ret;
550
551 ret = octeon_alloc_temp_buffer(urb, mem_flags);
552 if (ret)
553 return ret;
554
555 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
556 if (ret)
557 octeon_free_temp_buffer(urb);
558
559 return ret;
560 }
561
562 /**
563 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
564 * @hcd: USB HCD structure.
565 * @urb: URB.
566 */
567 static void octeon_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
568 {
569 usb_hcd_unmap_urb_for_dma(hcd, urb);
570 octeon_free_temp_buffer(urb);
571 }
572
573 /**
574 * Read a USB 32bit CSR. It performs the necessary address swizzle
575 * for 32bit CSRs and logs the value in a readable format if
576 * debugging is on.
577 *
578 * @usb: USB block this access is for
579 * @address: 64bit address to read
580 *
581 * Returns: Result of the read
582 */
583 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_state *usb,
584 uint64_t address)
585 {
586 uint32_t result = cvmx_read64_uint32(address ^ 4);
587 return result;
588 }
589
590
591 /**
592 * Write a USB 32bit CSR. It performs the necessary address
593 * swizzle for 32bit CSRs and logs the value in a readable format
594 * if debugging is on.
595 *
596 * @usb: USB block this access is for
597 * @address: 64bit address to write
598 * @value: Value to write
599 */
600 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_state *usb,
601 uint64_t address, uint32_t value)
602 {
603 cvmx_write64_uint32(address ^ 4, value);
604 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
605 }
606
607
608 /**
609 * Read a USB 64bit CSR. It logs the value in a readable format if
610 * debugging is on.
611 *
612 * @usb: USB block this access is for
613 * @address: 64bit address to read
614 *
615 * Returns: Result of the read
616 */
617 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_state *usb,
618 uint64_t address)
619 {
620 uint64_t result = cvmx_read64_uint64(address);
621 return result;
622 }
623
624
625 /**
626 * Write a USB 64bit CSR. It logs the value in a readable format
627 * if debugging is on.
628 *
629 * @usb: USB block this access is for
630 * @address: 64bit address to write
631 * @value: Value to write
632 */
633 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_state *usb,
634 uint64_t address, uint64_t value)
635 {
636 cvmx_write64_uint64(address, value);
637 }
638
639 /**
640 * Return non zero if this pipe connects to a non HIGH speed
641 * device through a high speed hub.
642 *
643 * @usb: USB block this access is for
644 * @pipe: Pipe to check
645 *
646 * Returns: Non zero if we need to do split transactions
647 */
648 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_state *usb,
649 struct cvmx_usb_pipe *pipe)
650 {
651 return pipe->device_speed != CVMX_USB_SPEED_HIGH &&
652 usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH;
653 }
654
655
656 /**
657 * Trivial utility function to return the correct PID for a pipe
658 *
659 * @pipe: pipe to check
660 *
661 * Returns: PID for pipe
662 */
663 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
664 {
665 if (pipe->pid_toggle)
666 return 2; /* Data1 */
667 else
668 return 0; /* Data0 */
669 }
670
671 /**
672 * Initialize a USB port for use. This must be called before any
673 * other access to the Octeon USB port is made. The port starts
674 * off in the disabled state.
675 *
676 * @usb: Pointer to an empty struct cvmx_usb_state
677 * that will be populated by the initialize call.
678 * This structure is then passed to all other USB
679 * functions.
680 * @usb_port_number:
681 * Which Octeon USB port to initialize.
682 *
683 * Returns: 0 or a negative error code.
684 */
685 static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
686 int usb_port_number,
687 enum cvmx_usb_initialize_flags flags)
688 {
689 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
690 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
691 int i;
692
693 /* At first allow 0-1 for the usb port number */
694 if ((usb_port_number < 0) || (usb_port_number > 1))
695 return -EINVAL;
696
697 memset(usb, 0, sizeof(*usb));
698 usb->init_flags = flags;
699
700 /* Initialize the USB state structure */
701 usb->index = usb_port_number;
702 INIT_LIST_HEAD(&usb->idle_pipes);
703 for (i = 0; i < ARRAY_SIZE(usb->active_pipes); i++)
704 INIT_LIST_HEAD(&usb->active_pipes[i]);
705
706 /*
707 * Power On Reset and PHY Initialization
708 *
709 * 1. Wait for DCOK to assert (nothing to do)
710 *
711 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
712 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
713 */
714 usbn_clk_ctl.u64 =
715 __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
716 usbn_clk_ctl.s.por = 1;
717 usbn_clk_ctl.s.hrst = 0;
718 usbn_clk_ctl.s.prst = 0;
719 usbn_clk_ctl.s.hclk_rst = 0;
720 usbn_clk_ctl.s.enable = 0;
721 /*
722 * 2b. Select the USB reference clock/crystal parameters by writing
723 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
724 */
725 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
726 /*
727 * The USB port uses 12/24/48MHz 2.5V board clock
728 * source at USB_XO. USB_XI should be tied to GND.
729 * Most Octeon evaluation boards require this setting
730 */
731 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
732 OCTEON_IS_MODEL(OCTEON_CN56XX) ||
733 OCTEON_IS_MODEL(OCTEON_CN50XX))
734 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
735 usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */
736 else
737 /* From CN52XX manual */
738 usbn_clk_ctl.s.p_rtype = 1;
739
740 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
741 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
742 usbn_clk_ctl.s.p_c_sel = 0;
743 break;
744 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
745 usbn_clk_ctl.s.p_c_sel = 1;
746 break;
747 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
748 usbn_clk_ctl.s.p_c_sel = 2;
749 break;
750 }
751 } else {
752 /*
753 * The USB port uses a 12MHz crystal as clock source
754 * at USB_XO and USB_XI
755 */
756 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
757 /* From CN31XX,CN30XX manual */
758 usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */
759 else
760 /* From CN56XX,CN52XX,CN50XX manuals. */
761 usbn_clk_ctl.s.p_rtype = 0;
762
763 usbn_clk_ctl.s.p_c_sel = 0;
764 }
765 /*
766 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
767 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
768 * such that USB is as close as possible to 125Mhz
769 */
770 {
771 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
772 /* Lower than 4 doesn't seem to work properly */
773 if (divisor < 4)
774 divisor = 4;
775 usbn_clk_ctl.s.divide = divisor;
776 usbn_clk_ctl.s.divide2 = 0;
777 }
778 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
779 usbn_clk_ctl.u64);
780 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
781 usbn_clk_ctl.s.hclk_rst = 1;
782 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
783 usbn_clk_ctl.u64);
784 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
785 cvmx_wait(64);
786 /*
787 * 3. Program the power-on reset field in the USBN clock-control
788 * register:
789 * USBN_CLK_CTL[POR] = 0
790 */
791 usbn_clk_ctl.s.por = 0;
792 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
793 usbn_clk_ctl.u64);
794 /* 4. Wait 1 ms for PHY clock to start */
795 mdelay(1);
796 /*
797 * 5. Program the Reset input from automatic test equipment field in the
798 * USBP control and status register:
799 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
800 */
801 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb,
802 CVMX_USBNX_USBP_CTL_STATUS(usb->index));
803 usbn_usbp_ctl_status.s.ate_reset = 1;
804 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
805 usbn_usbp_ctl_status.u64);
806 /* 6. Wait 10 cycles */
807 cvmx_wait(10);
808 /*
809 * 7. Clear ATE_RESET field in the USBN clock-control register:
810 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
811 */
812 usbn_usbp_ctl_status.s.ate_reset = 0;
813 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
814 usbn_usbp_ctl_status.u64);
815 /*
816 * 8. Program the PHY reset field in the USBN clock-control register:
817 * USBN_CLK_CTL[PRST] = 1
818 */
819 usbn_clk_ctl.s.prst = 1;
820 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
821 usbn_clk_ctl.u64);
822 /*
823 * 9. Program the USBP control and status register to select host or
824 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
825 * device
826 */
827 usbn_usbp_ctl_status.s.hst_mode = 0;
828 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
829 usbn_usbp_ctl_status.u64);
830 /* 10. Wait 1 us */
831 udelay(1);
832 /*
833 * 11. Program the hreset_n field in the USBN clock-control register:
834 * USBN_CLK_CTL[HRST] = 1
835 */
836 usbn_clk_ctl.s.hrst = 1;
837 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
838 usbn_clk_ctl.u64);
839 /* 12. Proceed to USB core initialization */
840 usbn_clk_ctl.s.enable = 1;
841 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
842 usbn_clk_ctl.u64);
843 udelay(1);
844
845 /*
846 * USB Core Initialization
847 *
848 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
849 * determine USB core configuration parameters.
850 *
851 * Nothing needed
852 *
853 * 2. Program the following fields in the global AHB configuration
854 * register (USBC_GAHBCFG)
855 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
856 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
857 * Nonperiodic TxFIFO empty level (slave mode only),
858 * USBC_GAHBCFG[NPTXFEMPLVL]
859 * Periodic TxFIFO empty level (slave mode only),
860 * USBC_GAHBCFG[PTXFEMPLVL]
861 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
862 */
863 {
864 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
865 /* Due to an errata, CN31XX doesn't support DMA */
866 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
867 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
868 usbcx_gahbcfg.u32 = 0;
869 usbcx_gahbcfg.s.dmaen = !(usb->init_flags &
870 CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
871 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
872 /* Only use one channel with non DMA */
873 usb->idle_hardware_channels = 0x1;
874 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
875 /* CN5XXX have an errata with channel 3 */
876 usb->idle_hardware_channels = 0xf7;
877 else
878 usb->idle_hardware_channels = 0xff;
879 usbcx_gahbcfg.s.hbstlen = 0;
880 usbcx_gahbcfg.s.nptxfemplvl = 1;
881 usbcx_gahbcfg.s.ptxfemplvl = 1;
882 usbcx_gahbcfg.s.glblintrmsk = 1;
883 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
884 usbcx_gahbcfg.u32);
885 }
886 /*
887 * 3. Program the following fields in USBC_GUSBCFG register.
888 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
889 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
890 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
891 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
892 */
893 {
894 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
895 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb,
896 CVMX_USBCX_GUSBCFG(usb->index));
897 usbcx_gusbcfg.s.toutcal = 0;
898 usbcx_gusbcfg.s.ddrsel = 0;
899 usbcx_gusbcfg.s.usbtrdtim = 0x5;
900 usbcx_gusbcfg.s.phylpwrclksel = 0;
901 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
902 usbcx_gusbcfg.u32);
903 }
904 /*
905 * 4. The software must unmask the following bits in the USBC_GINTMSK
906 * register.
907 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
908 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
909 */
910 {
911 union cvmx_usbcx_gintmsk usbcx_gintmsk;
912 int channel;
913
914 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb,
915 CVMX_USBCX_GINTMSK(usb->index));
916 usbcx_gintmsk.s.otgintmsk = 1;
917 usbcx_gintmsk.s.modemismsk = 1;
918 usbcx_gintmsk.s.hchintmsk = 1;
919 usbcx_gintmsk.s.sofmsk = 0;
920 /* We need RX FIFO interrupts if we don't have DMA */
921 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
922 usbcx_gintmsk.s.rxflvlmsk = 1;
923 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
924 usbcx_gintmsk.u32);
925
926 /*
927 * Disable all channel interrupts. We'll enable them per channel
928 * later.
929 */
930 for (channel = 0; channel < 8; channel++)
931 __cvmx_usb_write_csr32(usb,
932 CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
933 }
934
935 {
936 /*
937 * Host Port Initialization
938 *
939 * 1. Program the host-port interrupt-mask field to unmask,
940 * USBC_GINTMSK[PRTINT] = 1
941 */
942 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
943 union cvmx_usbcx_gintmsk, prtintmsk, 1);
944 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
945 union cvmx_usbcx_gintmsk, disconnintmsk, 1);
946 /*
947 * 2. Program the USBC_HCFG register to select full-speed host
948 * or high-speed host.
949 */
950 {
951 union cvmx_usbcx_hcfg usbcx_hcfg;
952 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb,
953 CVMX_USBCX_HCFG(usb->index));
954 usbcx_hcfg.s.fslssupp = 0;
955 usbcx_hcfg.s.fslspclksel = 0;
956 __cvmx_usb_write_csr32(usb,
957 CVMX_USBCX_HCFG(usb->index),
958 usbcx_hcfg.u32);
959 }
960 /*
961 * 3. Program the port power bit to drive VBUS on the USB,
962 * USBC_HPRT[PRTPWR] = 1
963 */
964 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index),
965 union cvmx_usbcx_hprt, prtpwr, 1);
966
967 /*
968 * Steps 4-15 from the manual are done later in the port enable
969 */
970 }
971
972 return 0;
973 }
974
975
976 /**
977 * Shutdown a USB port after a call to cvmx_usb_initialize().
978 * The port should be disabled with all pipes closed when this
979 * function is called.
980 *
981 * @usb: USB device state populated by cvmx_usb_initialize().
982 *
983 * Returns: 0 or a negative error code.
984 */
985 static int cvmx_usb_shutdown(struct cvmx_usb_state *usb)
986 {
987 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
988
989 /* Make sure all pipes are closed */
990 if (!list_empty(&usb->idle_pipes) ||
991 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) ||
992 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) ||
993 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) ||
994 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK]))
995 return -EBUSY;
996
997 /* Disable the clocks and put them in power on reset */
998 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb,
999 CVMX_USBNX_CLK_CTL(usb->index));
1000 usbn_clk_ctl.s.enable = 1;
1001 usbn_clk_ctl.s.por = 1;
1002 usbn_clk_ctl.s.hclk_rst = 1;
1003 usbn_clk_ctl.s.prst = 0;
1004 usbn_clk_ctl.s.hrst = 0;
1005 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
1006 usbn_clk_ctl.u64);
1007 return 0;
1008 }
1009
1010
1011 /**
1012 * Enable a USB port. After this call succeeds, the USB port is
1013 * online and servicing requests.
1014 *
1015 * @usb: USB device state populated by cvmx_usb_initialize().
1016 *
1017 * Returns: 0 or a negative error code.
1018 */
1019 static int cvmx_usb_enable(struct cvmx_usb_state *usb)
1020 {
1021 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
1022
1023 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb,
1024 CVMX_USBCX_HPRT(usb->index));
1025
1026 /*
1027 * If the port is already enabled the just return. We don't need to do
1028 * anything
1029 */
1030 if (usb->usbcx_hprt.s.prtena)
1031 return 0;
1032
1033 /* If there is nothing plugged into the port then fail immediately */
1034 if (!usb->usbcx_hprt.s.prtconnsts)
1035 return -ETIMEDOUT;
1036
1037 /* Program the port reset bit to start the reset process */
1038 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1039 prtrst, 1);
1040
1041 /*
1042 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
1043 * process to complete.
1044 */
1045 mdelay(50);
1046
1047 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
1048 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1049 prtrst, 0);
1050
1051 /* Wait for the USBC_HPRT[PRTENA]. */
1052 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index),
1053 union cvmx_usbcx_hprt, prtena, ==, 1, 100000))
1054 return -ETIMEDOUT;
1055
1056 /*
1057 * Read the port speed field to get the enumerated speed,
1058 * USBC_HPRT[PRTSPD].
1059 */
1060 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb,
1061 CVMX_USBCX_HPRT(usb->index));
1062 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb,
1063 CVMX_USBCX_GHWCFG3(usb->index));
1064
1065 /*
1066 * 13. Program the USBC_GRXFSIZ register to select the size of the
1067 * receive FIFO (25%).
1068 */
1069 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index),
1070 union cvmx_usbcx_grxfsiz, rxfdep,
1071 usbcx_ghwcfg3.s.dfifodepth / 4);
1072 /*
1073 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1074 * start address of the non- periodic transmit FIFO for nonperiodic
1075 * transactions (50%).
1076 */
1077 {
1078 union cvmx_usbcx_gnptxfsiz siz;
1079 siz.u32 = __cvmx_usb_read_csr32(usb,
1080 CVMX_USBCX_GNPTXFSIZ(usb->index));
1081 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
1082 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
1083 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index),
1084 siz.u32);
1085 }
1086 /*
1087 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1088 * address of the periodic transmit FIFO for periodic transactions
1089 * (25%).
1090 */
1091 {
1092 union cvmx_usbcx_hptxfsiz siz;
1093 siz.u32 = __cvmx_usb_read_csr32(usb,
1094 CVMX_USBCX_HPTXFSIZ(usb->index));
1095 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
1096 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
1097 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index),
1098 siz.u32);
1099 }
1100 /* Flush all FIFOs */
1101 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1102 union cvmx_usbcx_grstctl, txfnum, 0x10);
1103 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1104 union cvmx_usbcx_grstctl, txfflsh, 1);
1105 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1106 union cvmx_usbcx_grstctl,
1107 txfflsh, ==, 0, 100);
1108 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1109 union cvmx_usbcx_grstctl, rxfflsh, 1);
1110 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1111 union cvmx_usbcx_grstctl,
1112 rxfflsh, ==, 0, 100);
1113
1114 return 0;
1115 }
1116
1117
1118 /**
1119 * Disable a USB port. After this call the USB port will not
1120 * generate data transfers and will not generate events.
1121 * Transactions in process will fail and call their
1122 * associated callbacks.
1123 *
1124 * @usb: USB device state populated by cvmx_usb_initialize().
1125 *
1126 * Returns: 0 or a negative error code.
1127 */
1128 static int cvmx_usb_disable(struct cvmx_usb_state *usb)
1129 {
1130 /* Disable the port */
1131 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1132 prtena, 1);
1133 return 0;
1134 }
1135
1136
1137 /**
1138 * Get the current state of the USB port. Use this call to
1139 * determine if the usb port has anything connected, is enabled,
1140 * or has some sort of error condition. The return value of this
1141 * call has "changed" bits to signal of the value of some fields
1142 * have changed between calls.
1143 *
1144 * @usb: USB device state populated by cvmx_usb_initialize().
1145 *
1146 * Returns: Port status information
1147 */
1148 static struct cvmx_usb_port_status cvmx_usb_get_status(
1149 struct cvmx_usb_state *usb)
1150 {
1151 union cvmx_usbcx_hprt usbc_hprt;
1152 struct cvmx_usb_port_status result;
1153
1154 memset(&result, 0, sizeof(result));
1155
1156 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb,
1157 CVMX_USBCX_HPRT(usb->index));
1158 result.port_enabled = usbc_hprt.s.prtena;
1159 result.port_over_current = usbc_hprt.s.prtovrcurract;
1160 result.port_powered = usbc_hprt.s.prtpwr;
1161 result.port_speed = usbc_hprt.s.prtspd;
1162 result.connected = usbc_hprt.s.prtconnsts;
1163 result.connect_change =
1164 (result.connected != usb->port_status.connected);
1165
1166 return result;
1167 }
1168
1169 /**
1170 * Open a virtual pipe between the host and a USB device. A pipe
1171 * must be opened before data can be transferred between a device
1172 * and Octeon.
1173 *
1174 * @usb: USB device state populated by cvmx_usb_initialize().
1175 * @device_addr:
1176 * USB device address to open the pipe to
1177 * (0-127).
1178 * @endpoint_num:
1179 * USB endpoint number to open the pipe to
1180 * (0-15).
1181 * @device_speed:
1182 * The speed of the device the pipe is going
1183 * to. This must match the device's speed,
1184 * which may be different than the port speed.
1185 * @max_packet: The maximum packet length the device can
1186 * transmit/receive (low speed=0-8, full
1187 * speed=0-1023, high speed=0-1024). This value
1188 * comes from the standard endpoint descriptor
1189 * field wMaxPacketSize bits <10:0>.
1190 * @transfer_type:
1191 * The type of transfer this pipe is for.
1192 * @transfer_dir:
1193 * The direction the pipe is in. This is not
1194 * used for control pipes.
1195 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1196 * this is how often the transfer is scheduled
1197 * for. All other transfers should specify
1198 * zero. The units are in frames (8000/sec at
1199 * high speed, 1000/sec for full speed).
1200 * @multi_count:
1201 * For high speed devices, this is the maximum
1202 * allowed number of packet per microframe.
1203 * Specify zero for non high speed devices. This
1204 * value comes from the standard endpoint descriptor
1205 * field wMaxPacketSize bits <12:11>.
1206 * @hub_device_addr:
1207 * Hub device address this device is connected
1208 * to. Devices connected directly to Octeon
1209 * use zero. This is only used when the device
1210 * is full/low speed behind a high speed hub.
1211 * The address will be of the high speed hub,
1212 * not and full speed hubs after it.
1213 * @hub_port: Which port on the hub the device is
1214 * connected. Use zero for devices connected
1215 * directly to Octeon. Like hub_device_addr,
1216 * this is only used for full/low speed
1217 * devices behind a high speed hub.
1218 *
1219 * Returns: A non-NULL value is a pipe. NULL means an error.
1220 */
1221 static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct cvmx_usb_state *usb,
1222 int device_addr, int
1223 endpoint_num,
1224 enum cvmx_usb_speed
1225 device_speed,
1226 int max_packet,
1227 enum cvmx_usb_transfer
1228 transfer_type,
1229 enum cvmx_usb_direction
1230 transfer_dir,
1231 int interval, int multi_count,
1232 int hub_device_addr,
1233 int hub_port)
1234 {
1235 struct cvmx_usb_pipe *pipe;
1236
1237 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1238 return NULL;
1239 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1240 return NULL;
1241 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1242 return NULL;
1243 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1244 return NULL;
1245 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1246 return NULL;
1247 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1248 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1249 return NULL;
1250 if (unlikely(interval < 0))
1251 return NULL;
1252 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1253 return NULL;
1254 if (unlikely(multi_count < 0))
1255 return NULL;
1256 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1257 (multi_count != 0)))
1258 return NULL;
1259 if (unlikely((hub_device_addr < 0) ||
1260 (hub_device_addr > MAX_USB_ADDRESS)))
1261 return NULL;
1262 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1263 return NULL;
1264
1265 pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC);
1266 if (!pipe)
1267 return NULL;
1268 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1269 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1270 (transfer_type == CVMX_USB_TRANSFER_BULK))
1271 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1272 pipe->device_addr = device_addr;
1273 pipe->endpoint_num = endpoint_num;
1274 pipe->device_speed = device_speed;
1275 pipe->max_packet = max_packet;
1276 pipe->transfer_type = transfer_type;
1277 pipe->transfer_dir = transfer_dir;
1278 INIT_LIST_HEAD(&pipe->transactions);
1279
1280 /*
1281 * All pipes use interval to rate limit NAK processing. Force an
1282 * interval if one wasn't supplied
1283 */
1284 if (!interval)
1285 interval = 1;
1286 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1287 pipe->interval = interval*8;
1288 /* Force start splits to be schedule on uFrame 0 */
1289 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1290 } else {
1291 pipe->interval = interval;
1292 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1293 }
1294 pipe->multi_count = multi_count;
1295 pipe->hub_device_addr = hub_device_addr;
1296 pipe->hub_port = hub_port;
1297 pipe->pid_toggle = 0;
1298 pipe->split_sc_frame = -1;
1299 list_add_tail(&pipe->node, &usb->idle_pipes);
1300
1301 /*
1302 * We don't need to tell the hardware about this pipe yet since
1303 * it doesn't have any submitted requests
1304 */
1305
1306 return pipe;
1307 }
1308
1309
1310 /**
1311 * Poll the RX FIFOs and remove data as needed. This function is only used
1312 * in non DMA mode. It is very important that this function be called quickly
1313 * enough to prevent FIFO overflow.
1314 *
1315 * @usb: USB device state populated by cvmx_usb_initialize().
1316 */
1317 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb)
1318 {
1319 union cvmx_usbcx_grxstsph rx_status;
1320 int channel;
1321 int bytes;
1322 uint64_t address;
1323 uint32_t *ptr;
1324
1325 rx_status.u32 = __cvmx_usb_read_csr32(usb,
1326 CVMX_USBCX_GRXSTSPH(usb->index));
1327 /* Only read data if IN data is there */
1328 if (rx_status.s.pktsts != 2)
1329 return;
1330 /* Check if no data is available */
1331 if (!rx_status.s.bcnt)
1332 return;
1333
1334 channel = rx_status.s.chnum;
1335 bytes = rx_status.s.bcnt;
1336 if (!bytes)
1337 return;
1338
1339 /* Get where the DMA engine would have written this data */
1340 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1341 ptr = cvmx_phys_to_ptr(address);
1342 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1343
1344 /* Loop writing the FIFO data for this packet into memory */
1345 while (bytes > 0) {
1346 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1347 bytes -= 4;
1348 }
1349 CVMX_SYNCW;
1350
1351 return;
1352 }
1353
1354
1355 /**
1356 * Fill the TX hardware fifo with data out of the software
1357 * fifos
1358 *
1359 * @usb: USB device state populated by cvmx_usb_initialize().
1360 * @fifo: Software fifo to use
1361 * @available: Amount of space in the hardware fifo
1362 *
1363 * Returns: Non zero if the hardware fifo was too small and needs
1364 * to be serviced again.
1365 */
1366 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_state *usb,
1367 struct cvmx_usb_tx_fifo *fifo, int available)
1368 {
1369 /*
1370 * We're done either when there isn't anymore space or the software FIFO
1371 * is empty
1372 */
1373 while (available && (fifo->head != fifo->tail)) {
1374 int i = fifo->tail;
1375 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1376 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel,
1377 usb->index) ^ 4;
1378 int words = available;
1379
1380 /* Limit the amount of data to waht the SW fifo has */
1381 if (fifo->entry[i].size <= available) {
1382 words = fifo->entry[i].size;
1383 fifo->tail++;
1384 if (fifo->tail > MAX_CHANNELS)
1385 fifo->tail = 0;
1386 }
1387
1388 /* Update the next locations and counts */
1389 available -= words;
1390 fifo->entry[i].address += words * 4;
1391 fifo->entry[i].size -= words;
1392
1393 /*
1394 * Write the HW fifo data. The read every three writes is due
1395 * to an errata on CN3XXX chips
1396 */
1397 while (words > 3) {
1398 cvmx_write64_uint32(csr_address, *ptr++);
1399 cvmx_write64_uint32(csr_address, *ptr++);
1400 cvmx_write64_uint32(csr_address, *ptr++);
1401 cvmx_read64_uint64(
1402 CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1403 words -= 3;
1404 }
1405 cvmx_write64_uint32(csr_address, *ptr++);
1406 if (--words) {
1407 cvmx_write64_uint32(csr_address, *ptr++);
1408 if (--words)
1409 cvmx_write64_uint32(csr_address, *ptr++);
1410 }
1411 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1412 }
1413 return fifo->head != fifo->tail;
1414 }
1415
1416
1417 /**
1418 * Check the hardware FIFOs and fill them as needed
1419 *
1420 * @usb: USB device state populated by cvmx_usb_initialize().
1421 */
1422 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_state *usb)
1423 {
1424 if (usb->periodic.head != usb->periodic.tail) {
1425 union cvmx_usbcx_hptxsts tx_status;
1426 tx_status.u32 = __cvmx_usb_read_csr32(usb,
1427 CVMX_USBCX_HPTXSTS(usb->index));
1428 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic,
1429 tx_status.s.ptxfspcavail))
1430 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1431 union cvmx_usbcx_gintmsk,
1432 ptxfempmsk, 1);
1433 else
1434 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1435 union cvmx_usbcx_gintmsk,
1436 ptxfempmsk, 0);
1437 }
1438
1439 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1440 union cvmx_usbcx_gnptxsts tx_status;
1441 tx_status.u32 = __cvmx_usb_read_csr32(usb,
1442 CVMX_USBCX_GNPTXSTS(usb->index));
1443 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic,
1444 tx_status.s.nptxfspcavail))
1445 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1446 union cvmx_usbcx_gintmsk,
1447 nptxfempmsk, 1);
1448 else
1449 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1450 union cvmx_usbcx_gintmsk,
1451 nptxfempmsk, 0);
1452 }
1453
1454 return;
1455 }
1456
1457
1458 /**
1459 * Fill the TX FIFO with an outgoing packet
1460 *
1461 * @usb: USB device state populated by cvmx_usb_initialize().
1462 * @channel: Channel number to get packet from
1463 */
1464 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel)
1465 {
1466 union cvmx_usbcx_hccharx hcchar;
1467 union cvmx_usbcx_hcspltx usbc_hcsplt;
1468 union cvmx_usbcx_hctsizx usbc_hctsiz;
1469 struct cvmx_usb_tx_fifo *fifo;
1470
1471 /* We only need to fill data on outbound channels */
1472 hcchar.u32 = __cvmx_usb_read_csr32(usb,
1473 CVMX_USBCX_HCCHARX(channel, usb->index));
1474 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1475 return;
1476
1477 /* OUT Splits only have data on the start and not the complete */
1478 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb,
1479 CVMX_USBCX_HCSPLTX(channel, usb->index));
1480 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1481 return;
1482
1483 /*
1484 * Find out how many bytes we need to fill and convert it into 32bit
1485 * words.
1486 */
1487 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb,
1488 CVMX_USBCX_HCTSIZX(channel, usb->index));
1489 if (!usbc_hctsiz.s.xfersize)
1490 return;
1491
1492 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1493 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1494 fifo = &usb->periodic;
1495 else
1496 fifo = &usb->nonperiodic;
1497
1498 fifo->entry[fifo->head].channel = channel;
1499 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1500 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1501 fifo->head++;
1502 if (fifo->head > MAX_CHANNELS)
1503 fifo->head = 0;
1504
1505 __cvmx_usb_poll_tx_fifo(usb);
1506
1507 return;
1508 }
1509
1510 /**
1511 * Perform channel specific setup for Control transactions. All
1512 * the generic stuff will already have been done in
1513 * __cvmx_usb_start_channel()
1514 *
1515 * @usb: USB device state populated by cvmx_usb_initialize().
1516 * @channel: Channel to setup
1517 * @pipe: Pipe for control transaction
1518 */
1519 static void __cvmx_usb_start_channel_control(struct cvmx_usb_state *usb,
1520 int channel,
1521 struct cvmx_usb_pipe *pipe)
1522 {
1523 struct cvmx_usb_transaction *transaction =
1524 list_first_entry(&pipe->transactions, typeof(*transaction),
1525 node);
1526 union cvmx_usb_control_header *header =
1527 cvmx_phys_to_ptr(transaction->control_header);
1528 int bytes_to_transfer = transaction->buffer_length -
1529 transaction->actual_bytes;
1530 int packets_to_transfer;
1531 union cvmx_usbcx_hctsizx usbc_hctsiz;
1532
1533 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb,
1534 CVMX_USBCX_HCTSIZX(channel, usb->index));
1535
1536 switch (transaction->stage) {
1537 case CVMX_USB_STAGE_NON_CONTROL:
1538 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1539 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1540 break;
1541 case CVMX_USB_STAGE_SETUP:
1542 usbc_hctsiz.s.pid = 3; /* Setup */
1543 bytes_to_transfer = sizeof(*header);
1544 /* All Control operations start with a setup going OUT */
1545 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1546 /*
1547 * Setup send the control header instead of the buffer data. The
1548 * buffer data will be used in the next stage
1549 */
1550 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1551 break;
1552 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1553 usbc_hctsiz.s.pid = 3; /* Setup */
1554 bytes_to_transfer = 0;
1555 /* All Control operations start with a setup going OUT */
1556 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1557 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1558 break;
1559 case CVMX_USB_STAGE_DATA:
1560 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1561 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1562 if (header->s.request_type & 0x80)
1563 bytes_to_transfer = 0;
1564 else if (bytes_to_transfer > pipe->max_packet)
1565 bytes_to_transfer = pipe->max_packet;
1566 }
1567 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1568 union cvmx_usbcx_hccharx, epdir,
1569 ((header->s.request_type & 0x80) ?
1570 CVMX_USB_DIRECTION_IN :
1571 CVMX_USB_DIRECTION_OUT));
1572 break;
1573 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1574 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1575 if (!(header->s.request_type & 0x80))
1576 bytes_to_transfer = 0;
1577 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1578 union cvmx_usbcx_hccharx, epdir,
1579 ((header->s.request_type & 0x80) ?
1580 CVMX_USB_DIRECTION_IN :
1581 CVMX_USB_DIRECTION_OUT));
1582 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1583 union cvmx_usbcx_hcspltx, compsplt, 1);
1584 break;
1585 case CVMX_USB_STAGE_STATUS:
1586 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1587 bytes_to_transfer = 0;
1588 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1589 union cvmx_usbcx_hccharx, epdir,
1590 ((header->s.request_type & 0x80) ?
1591 CVMX_USB_DIRECTION_OUT :
1592 CVMX_USB_DIRECTION_IN));
1593 break;
1594 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1595 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1596 bytes_to_transfer = 0;
1597 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1598 union cvmx_usbcx_hccharx, epdir,
1599 ((header->s.request_type & 0x80) ?
1600 CVMX_USB_DIRECTION_OUT :
1601 CVMX_USB_DIRECTION_IN));
1602 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1603 union cvmx_usbcx_hcspltx, compsplt, 1);
1604 break;
1605 }
1606
1607 /*
1608 * Make sure the transfer never exceeds the byte limit of the hardware.
1609 * Further bytes will be sent as continued transactions
1610 */
1611 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1612 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1613 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1614 bytes_to_transfer *= pipe->max_packet;
1615 }
1616
1617 /*
1618 * Calculate the number of packets to transfer. If the length is zero
1619 * we still need to transfer one packet
1620 */
1621 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) /
1622 pipe->max_packet;
1623 if (packets_to_transfer == 0)
1624 packets_to_transfer = 1;
1625 else if ((packets_to_transfer > 1) &&
1626 (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1627 /*
1628 * Limit to one packet when not using DMA. Channels must be
1629 * restarted between every packet for IN transactions, so there
1630 * is no reason to do multiple packets in a row
1631 */
1632 packets_to_transfer = 1;
1633 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1634 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1635 /*
1636 * Limit the number of packet and data transferred to what the
1637 * hardware can handle
1638 */
1639 packets_to_transfer = MAX_TRANSFER_PACKETS;
1640 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1641 }
1642
1643 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1644 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1645
1646 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index),
1647 usbc_hctsiz.u32);
1648 return;
1649 }
1650
1651
1652 /**
1653 * Start a channel to perform the pipe's head transaction
1654 *
1655 * @usb: USB device state populated by cvmx_usb_initialize().
1656 * @channel: Channel to setup
1657 * @pipe: Pipe to start
1658 */
1659 static void __cvmx_usb_start_channel(struct cvmx_usb_state *usb,
1660 int channel,
1661 struct cvmx_usb_pipe *pipe)
1662 {
1663 struct cvmx_usb_transaction *transaction =
1664 list_first_entry(&pipe->transactions, typeof(*transaction),
1665 node);
1666
1667 /* Make sure all writes to the DMA region get flushed */
1668 CVMX_SYNCW;
1669
1670 /* Attach the channel to the pipe */
1671 usb->pipe_for_channel[channel] = pipe;
1672 pipe->channel = channel;
1673 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1674
1675 /* Mark this channel as in use */
1676 usb->idle_hardware_channels &= ~(1<<channel);
1677
1678 /* Enable the channel interrupt bits */
1679 {
1680 union cvmx_usbcx_hcintx usbc_hcint;
1681 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1682 union cvmx_usbcx_haintmsk usbc_haintmsk;
1683
1684 /* Clear all channel status bits */
1685 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb,
1686 CVMX_USBCX_HCINTX(channel, usb->index));
1687 __cvmx_usb_write_csr32(usb,
1688 CVMX_USBCX_HCINTX(channel, usb->index),
1689 usbc_hcint.u32);
1690
1691 usbc_hcintmsk.u32 = 0;
1692 usbc_hcintmsk.s.chhltdmsk = 1;
1693 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1694 /*
1695 * Channels need these extra interrupts when we aren't
1696 * in DMA mode.
1697 */
1698 usbc_hcintmsk.s.datatglerrmsk = 1;
1699 usbc_hcintmsk.s.frmovrunmsk = 1;
1700 usbc_hcintmsk.s.bblerrmsk = 1;
1701 usbc_hcintmsk.s.xacterrmsk = 1;
1702 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1703 /*
1704 * Splits don't generate xfercompl, so we need
1705 * ACK and NYET.
1706 */
1707 usbc_hcintmsk.s.nyetmsk = 1;
1708 usbc_hcintmsk.s.ackmsk = 1;
1709 }
1710 usbc_hcintmsk.s.nakmsk = 1;
1711 usbc_hcintmsk.s.stallmsk = 1;
1712 usbc_hcintmsk.s.xfercomplmsk = 1;
1713 }
1714 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1715
1716 /* Enable the channel interrupt to propagate */
1717 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1718 usbc_haintmsk.s.haintmsk |= 1<<channel;
1719 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1720 }
1721
1722 /* Setup the locations the DMA engines use */
1723 {
1724 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1725 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1726 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1727 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1728 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1729 }
1730
1731 /* Setup both the size of the transfer and the SPLIT characteristics */
1732 {
1733 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1734 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1735 int packets_to_transfer;
1736 int bytes_to_transfer = transaction->buffer_length -
1737 transaction->actual_bytes;
1738
1739 /*
1740 * ISOCHRONOUS transactions store each individual transfer size
1741 * in the packet structure, not the global buffer_length
1742 */
1743 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1744 bytes_to_transfer =
1745 transaction->iso_packets[0].length -
1746 transaction->actual_bytes;
1747
1748 /*
1749 * We need to do split transactions when we are talking to non
1750 * high speed devices that are behind a high speed hub
1751 */
1752 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1753 /*
1754 * On the start split phase (stage is even) record the
1755 * frame number we will need to send the split complete.
1756 * We only store the lower two bits since the time ahead
1757 * can only be two frames
1758 */
1759 if ((transaction->stage&1) == 0) {
1760 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1761 pipe->split_sc_frame =
1762 (usb->frame_number + 1) & 0x7f;
1763 else
1764 pipe->split_sc_frame =
1765 (usb->frame_number + 2) & 0x7f;
1766 } else
1767 pipe->split_sc_frame = -1;
1768
1769 usbc_hcsplt.s.spltena = 1;
1770 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1771 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1772 usbc_hcsplt.s.compsplt = (transaction->stage ==
1773 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1774
1775 /*
1776 * SPLIT transactions can only ever transmit one data
1777 * packet so limit the transfer size to the max packet
1778 * size
1779 */
1780 if (bytes_to_transfer > pipe->max_packet)
1781 bytes_to_transfer = pipe->max_packet;
1782
1783 /*
1784 * ISOCHRONOUS OUT splits are unique in that they limit
1785 * data transfers to 188 byte chunks representing the
1786 * begin/middle/end of the data or all
1787 */
1788 if (!usbc_hcsplt.s.compsplt &&
1789 (pipe->transfer_dir ==
1790 CVMX_USB_DIRECTION_OUT) &&
1791 (pipe->transfer_type ==
1792 CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1793 /*
1794 * Clear the split complete frame number as
1795 * there isn't going to be a split complete
1796 */
1797 pipe->split_sc_frame = -1;
1798 /*
1799 * See if we've started this transfer and sent
1800 * data
1801 */
1802 if (transaction->actual_bytes == 0) {
1803 /*
1804 * Nothing sent yet, this is either a
1805 * begin or the entire payload
1806 */
1807 if (bytes_to_transfer <= 188)
1808 /* Entire payload in one go */
1809 usbc_hcsplt.s.xactpos = 3;
1810 else
1811 /* First part of payload */
1812 usbc_hcsplt.s.xactpos = 2;
1813 } else {
1814 /*
1815 * Continuing the previous data, we must
1816 * either be in the middle or at the end
1817 */
1818 if (bytes_to_transfer <= 188)
1819 /* End of payload */
1820 usbc_hcsplt.s.xactpos = 1;
1821 else
1822 /* Middle of payload */
1823 usbc_hcsplt.s.xactpos = 0;
1824 }
1825 /*
1826 * Again, the transfer size is limited to 188
1827 * bytes
1828 */
1829 if (bytes_to_transfer > 188)
1830 bytes_to_transfer = 188;
1831 }
1832 }
1833
1834 /*
1835 * Make sure the transfer never exceeds the byte limit of the
1836 * hardware. Further bytes will be sent as continued
1837 * transactions
1838 */
1839 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1840 /*
1841 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1842 * size
1843 */
1844 bytes_to_transfer = MAX_TRANSFER_BYTES /
1845 pipe->max_packet;
1846 bytes_to_transfer *= pipe->max_packet;
1847 }
1848
1849 /*
1850 * Calculate the number of packets to transfer. If the length is
1851 * zero we still need to transfer one packet
1852 */
1853 packets_to_transfer =
1854 (bytes_to_transfer + pipe->max_packet - 1) /
1855 pipe->max_packet;
1856 if (packets_to_transfer == 0)
1857 packets_to_transfer = 1;
1858 else if ((packets_to_transfer > 1) &&
1859 (usb->init_flags &
1860 CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1861 /*
1862 * Limit to one packet when not using DMA. Channels must
1863 * be restarted between every packet for IN
1864 * transactions, so there is no reason to do multiple
1865 * packets in a row
1866 */
1867 packets_to_transfer = 1;
1868 bytes_to_transfer = packets_to_transfer *
1869 pipe->max_packet;
1870 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1871 /*
1872 * Limit the number of packet and data transferred to
1873 * what the hardware can handle
1874 */
1875 packets_to_transfer = MAX_TRANSFER_PACKETS;
1876 bytes_to_transfer = packets_to_transfer *
1877 pipe->max_packet;
1878 }
1879
1880 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1881 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1882
1883 /* Update the DATA0/DATA1 toggle */
1884 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1885 /*
1886 * High speed pipes may need a hardware ping before they start
1887 */
1888 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1889 usbc_hctsiz.s.dopng = 1;
1890
1891 __cvmx_usb_write_csr32(usb,
1892 CVMX_USBCX_HCSPLTX(channel, usb->index),
1893 usbc_hcsplt.u32);
1894 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel,
1895 usb->index), usbc_hctsiz.u32);
1896 }
1897
1898 /* Setup the Host Channel Characteristics Register */
1899 {
1900 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1901
1902 /*
1903 * Set the startframe odd/even properly. This is only used for
1904 * periodic
1905 */
1906 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1907
1908 /*
1909 * Set the number of back to back packets allowed by this
1910 * endpoint. Split transactions interpret "ec" as the number of
1911 * immediate retries of failure. These retries happen too
1912 * quickly, so we disable these entirely for splits
1913 */
1914 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1915 usbc_hcchar.s.ec = 1;
1916 else if (pipe->multi_count < 1)
1917 usbc_hcchar.s.ec = 1;
1918 else if (pipe->multi_count > 3)
1919 usbc_hcchar.s.ec = 3;
1920 else
1921 usbc_hcchar.s.ec = pipe->multi_count;
1922
1923 /* Set the rest of the endpoint specific settings */
1924 usbc_hcchar.s.devaddr = pipe->device_addr;
1925 usbc_hcchar.s.eptype = transaction->type;
1926 usbc_hcchar.s.lspddev =
1927 (pipe->device_speed == CVMX_USB_SPEED_LOW);
1928 usbc_hcchar.s.epdir = pipe->transfer_dir;
1929 usbc_hcchar.s.epnum = pipe->endpoint_num;
1930 usbc_hcchar.s.mps = pipe->max_packet;
1931 __cvmx_usb_write_csr32(usb,
1932 CVMX_USBCX_HCCHARX(channel, usb->index),
1933 usbc_hcchar.u32);
1934 }
1935
1936 /* Do transaction type specific fixups as needed */
1937 switch (transaction->type) {
1938 case CVMX_USB_TRANSFER_CONTROL:
1939 __cvmx_usb_start_channel_control(usb, channel, pipe);
1940 break;
1941 case CVMX_USB_TRANSFER_BULK:
1942 case CVMX_USB_TRANSFER_INTERRUPT:
1943 break;
1944 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1945 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1946 /*
1947 * ISO transactions require different PIDs depending on
1948 * direction and how many packets are needed
1949 */
1950 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1951 if (pipe->multi_count < 2) /* Need DATA0 */
1952 USB_SET_FIELD32(
1953 CVMX_USBCX_HCTSIZX(channel,
1954 usb->index),
1955 union cvmx_usbcx_hctsizx,
1956 pid, 0);
1957 else /* Need MDATA */
1958 USB_SET_FIELD32(
1959 CVMX_USBCX_HCTSIZX(channel,
1960 usb->index),
1961 union cvmx_usbcx_hctsizx,
1962 pid, 3);
1963 }
1964 }
1965 break;
1966 }
1967 {
1968 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 =
1969 __cvmx_usb_read_csr32(usb,
1970 CVMX_USBCX_HCTSIZX(channel, usb->index))};
1971 transaction->xfersize = usbc_hctsiz.s.xfersize;
1972 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1973 }
1974 /* Remeber when we start a split transaction */
1975 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1976 usb->active_split = transaction;
1977 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1978 union cvmx_usbcx_hccharx, chena, 1);
1979 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1980 __cvmx_usb_fill_tx_fifo(usb, channel);
1981 return;
1982 }
1983
1984
1985 /**
1986 * Find a pipe that is ready to be scheduled to hardware.
1987 * @usb: USB device state populated by cvmx_usb_initialize().
1988 * @list: Pipe list to search
1989 * @current_frame:
1990 * Frame counter to use as a time reference.
1991 *
1992 * Returns: Pipe or NULL if none are ready
1993 */
1994 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(
1995 struct cvmx_usb_state *usb,
1996 struct list_head *list,
1997 uint64_t current_frame)
1998 {
1999 struct cvmx_usb_pipe *pipe;
2000
2001 list_for_each_entry(pipe, list, node) {
2002 struct cvmx_usb_transaction *t =
2003 list_first_entry(&pipe->transactions, typeof(*t),
2004 node);
2005 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && t &&
2006 (pipe->next_tx_frame <= current_frame) &&
2007 ((pipe->split_sc_frame == -1) ||
2008 ((((int)current_frame - (int)pipe->split_sc_frame)
2009 & 0x7f) < 0x40)) &&
2010 (!usb->active_split || (usb->active_split == t))) {
2011 CVMX_PREFETCH(pipe, 128);
2012 CVMX_PREFETCH(t, 0);
2013 return pipe;
2014 }
2015 }
2016 return NULL;
2017 }
2018
2019
2020 /**
2021 * Called whenever a pipe might need to be scheduled to the
2022 * hardware.
2023 *
2024 * @usb: USB device state populated by cvmx_usb_initialize().
2025 * @is_sof: True if this schedule was called on a SOF interrupt.
2026 */
2027 static void __cvmx_usb_schedule(struct cvmx_usb_state *usb, int is_sof)
2028 {
2029 int channel;
2030 struct cvmx_usb_pipe *pipe;
2031 int need_sof;
2032 enum cvmx_usb_transfer ttype;
2033
2034 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2035 /*
2036 * Without DMA we need to be careful to not schedule something
2037 * at the end of a frame and cause an overrun.
2038 */
2039 union cvmx_usbcx_hfnum hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
2040 union cvmx_usbcx_hfir hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
2041 if (hfnum.s.frrem < hfir.s.frint/4)
2042 goto done;
2043 }
2044
2045 while (usb->idle_hardware_channels) {
2046 /* Find an idle channel */
2047 channel = __fls(usb->idle_hardware_channels);
2048 if (unlikely(channel > 7))
2049 break;
2050
2051 /* Find a pipe needing service */
2052 pipe = NULL;
2053 if (is_sof) {
2054 /*
2055 * Only process periodic pipes on SOF interrupts. This
2056 * way we are sure that the periodic data is sent in the
2057 * beginning of the frame
2058 */
2059 pipe = __cvmx_usb_find_ready_pipe(usb,
2060 usb->active_pipes +
2061 CVMX_USB_TRANSFER_ISOCHRONOUS,
2062 usb->frame_number);
2063 if (likely(!pipe))
2064 pipe = __cvmx_usb_find_ready_pipe(usb,
2065 usb->active_pipes +
2066 CVMX_USB_TRANSFER_INTERRUPT,
2067 usb->frame_number);
2068 }
2069 if (likely(!pipe)) {
2070 pipe = __cvmx_usb_find_ready_pipe(usb,
2071 usb->active_pipes +
2072 CVMX_USB_TRANSFER_CONTROL,
2073 usb->frame_number);
2074 if (likely(!pipe))
2075 pipe = __cvmx_usb_find_ready_pipe(usb,
2076 usb->active_pipes +
2077 CVMX_USB_TRANSFER_BULK,
2078 usb->frame_number);
2079 }
2080 if (!pipe)
2081 break;
2082
2083 __cvmx_usb_start_channel(usb, channel, pipe);
2084 }
2085
2086 done:
2087 /*
2088 * Only enable SOF interrupts when we have transactions pending in the
2089 * future that might need to be scheduled
2090 */
2091 need_sof = 0;
2092 for (ttype = CVMX_USB_TRANSFER_CONTROL;
2093 ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
2094 list_for_each_entry(pipe, &usb->active_pipes[ttype], node) {
2095 if (pipe->next_tx_frame > usb->frame_number) {
2096 need_sof = 1;
2097 break;
2098 }
2099 }
2100 }
2101 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
2102 union cvmx_usbcx_gintmsk, sofmsk, need_sof);
2103 return;
2104 }
2105
2106 static inline struct octeon_hcd *cvmx_usb_to_octeon(struct cvmx_usb_state *p)
2107 {
2108 return container_of(p, struct octeon_hcd, usb);
2109 }
2110
2111 static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p)
2112 {
2113 return container_of((void *)p, struct usb_hcd, hcd_priv);
2114 }
2115
2116 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state *usb,
2117 enum cvmx_usb_complete status,
2118 struct cvmx_usb_pipe *pipe,
2119 struct cvmx_usb_transaction
2120 *transaction,
2121 int bytes_transferred,
2122 struct urb *urb)
2123 {
2124 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2125 struct usb_hcd *hcd = octeon_to_hcd(priv);
2126 struct device *dev = hcd->self.controller;
2127
2128 urb->actual_length = bytes_transferred;
2129 urb->hcpriv = NULL;
2130
2131 if (!list_empty(&urb->urb_list))
2132 /*
2133 * It is on the dequeue_list, but we are going to call
2134 * usb_hcd_giveback_urb(), so we must clear it from
2135 * the list. We got to it before the
2136 * octeon_usb_urb_dequeue_work() tasklet did.
2137 */
2138 list_del_init(&urb->urb_list);
2139
2140 /* For Isochronous transactions we need to update the URB packet status
2141 list from data in our private copy */
2142 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2143 int i;
2144 /*
2145 * The pointer to the private list is stored in the setup_packet
2146 * field.
2147 */
2148 struct cvmx_usb_iso_packet *iso_packet =
2149 (struct cvmx_usb_iso_packet *) urb->setup_packet;
2150 /* Recalculate the transfer size by adding up each packet */
2151 urb->actual_length = 0;
2152 for (i = 0; i < urb->number_of_packets; i++) {
2153 if (iso_packet[i].status ==
2154 CVMX_USB_COMPLETE_SUCCESS) {
2155 urb->iso_frame_desc[i].status = 0;
2156 urb->iso_frame_desc[i].actual_length =
2157 iso_packet[i].length;
2158 urb->actual_length +=
2159 urb->iso_frame_desc[i].actual_length;
2160 } else {
2161 dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2162 i, urb->number_of_packets,
2163 iso_packet[i].status, pipe,
2164 transaction, iso_packet[i].length);
2165 urb->iso_frame_desc[i].status = -EREMOTEIO;
2166 }
2167 }
2168 /* Free the private list now that we don't need it anymore */
2169 kfree(iso_packet);
2170 urb->setup_packet = NULL;
2171 }
2172
2173 switch (status) {
2174 case CVMX_USB_COMPLETE_SUCCESS:
2175 urb->status = 0;
2176 break;
2177 case CVMX_USB_COMPLETE_CANCEL:
2178 if (urb->status == 0)
2179 urb->status = -ENOENT;
2180 break;
2181 case CVMX_USB_COMPLETE_STALL:
2182 dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n",
2183 pipe, transaction, bytes_transferred);
2184 urb->status = -EPIPE;
2185 break;
2186 case CVMX_USB_COMPLETE_BABBLEERR:
2187 dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n",
2188 pipe, transaction, bytes_transferred);
2189 urb->status = -EPIPE;
2190 break;
2191 case CVMX_USB_COMPLETE_SHORT:
2192 dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n",
2193 pipe, transaction, bytes_transferred);
2194 urb->status = -EREMOTEIO;
2195 break;
2196 case CVMX_USB_COMPLETE_ERROR:
2197 case CVMX_USB_COMPLETE_XACTERR:
2198 case CVMX_USB_COMPLETE_DATATGLERR:
2199 case CVMX_USB_COMPLETE_FRAMEERR:
2200 dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n",
2201 status, pipe, transaction, bytes_transferred);
2202 urb->status = -EPROTO;
2203 break;
2204 }
2205 spin_unlock(&priv->lock);
2206 usb_hcd_giveback_urb(octeon_to_hcd(priv), urb, urb->status);
2207 spin_lock(&priv->lock);
2208 }
2209
2210 /**
2211 * Signal the completion of a transaction and free it. The
2212 * transaction will be removed from the pipe transaction list.
2213 *
2214 * @usb: USB device state populated by cvmx_usb_initialize().
2215 * @pipe: Pipe the transaction is on
2216 * @transaction:
2217 * Transaction that completed
2218 * @complete_code:
2219 * Completion code
2220 */
2221 static void __cvmx_usb_perform_complete(
2222 struct cvmx_usb_state *usb,
2223 struct cvmx_usb_pipe *pipe,
2224 struct cvmx_usb_transaction *transaction,
2225 enum cvmx_usb_complete complete_code)
2226 {
2227 /* If this was a split then clear our split in progress marker */
2228 if (usb->active_split == transaction)
2229 usb->active_split = NULL;
2230
2231 /*
2232 * Isochronous transactions need extra processing as they might not be
2233 * done after a single data transfer
2234 */
2235 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2236 /* Update the number of bytes transferred in this ISO packet */
2237 transaction->iso_packets[0].length = transaction->actual_bytes;
2238 transaction->iso_packets[0].status = complete_code;
2239
2240 /*
2241 * If there are more ISOs pending and we succeeded, schedule the
2242 * next one
2243 */
2244 if ((transaction->iso_number_packets > 1) &&
2245 (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2246 /* No bytes transferred for this packet as of yet */
2247 transaction->actual_bytes = 0;
2248 /* One less ISO waiting to transfer */
2249 transaction->iso_number_packets--;
2250 /* Increment to the next location in our packet array */
2251 transaction->iso_packets++;
2252 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2253 goto done;
2254 }
2255 }
2256
2257 /* Remove the transaction from the pipe list */
2258 list_del(&transaction->node);
2259 if (list_empty(&pipe->transactions))
2260 list_move_tail(&pipe->node, &usb->idle_pipes);
2261 octeon_usb_urb_complete_callback(usb, complete_code, pipe,
2262 transaction,
2263 transaction->actual_bytes,
2264 transaction->urb);
2265 kfree(transaction);
2266 done:
2267 return;
2268 }
2269
2270
2271 /**
2272 * Submit a usb transaction to a pipe. Called for all types
2273 * of transactions.
2274 *
2275 * @usb:
2276 * @pipe: Which pipe to submit to.
2277 * @type: Transaction type
2278 * @buffer: User buffer for the transaction
2279 * @buffer_length:
2280 * User buffer's length in bytes
2281 * @control_header:
2282 * For control transactions, the 8 byte standard header
2283 * @iso_start_frame:
2284 * For ISO transactions, the start frame
2285 * @iso_number_packets:
2286 * For ISO, the number of packet in the transaction.
2287 * @iso_packets:
2288 * A description of each ISO packet
2289 * @urb: URB for the callback
2290 *
2291 * Returns: Transaction or NULL on failure.
2292 */
2293 static struct cvmx_usb_transaction *__cvmx_usb_submit_transaction(
2294 struct cvmx_usb_state *usb,
2295 struct cvmx_usb_pipe *pipe,
2296 enum cvmx_usb_transfer type,
2297 uint64_t buffer,
2298 int buffer_length,
2299 uint64_t control_header,
2300 int iso_start_frame,
2301 int iso_number_packets,
2302 struct cvmx_usb_iso_packet *iso_packets,
2303 struct urb *urb)
2304 {
2305 struct cvmx_usb_transaction *transaction;
2306
2307 if (unlikely(pipe->transfer_type != type))
2308 return NULL;
2309
2310 transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC);
2311 if (unlikely(!transaction))
2312 return NULL;
2313
2314 transaction->type = type;
2315 transaction->buffer = buffer;
2316 transaction->buffer_length = buffer_length;
2317 transaction->control_header = control_header;
2318 /* FIXME: This is not used, implement it. */
2319 transaction->iso_start_frame = iso_start_frame;
2320 transaction->iso_number_packets = iso_number_packets;
2321 transaction->iso_packets = iso_packets;
2322 transaction->urb = urb;
2323 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2324 transaction->stage = CVMX_USB_STAGE_SETUP;
2325 else
2326 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2327
2328 if (!list_empty(&pipe->transactions)) {
2329 list_add_tail(&transaction->node, &pipe->transactions);
2330 } else {
2331 list_add_tail(&transaction->node, &pipe->transactions);
2332 list_move_tail(&pipe->node,
2333 &usb->active_pipes[pipe->transfer_type]);
2334
2335 /*
2336 * We may need to schedule the pipe if this was the head of the
2337 * pipe.
2338 */
2339 __cvmx_usb_schedule(usb, 0);
2340 }
2341
2342 return transaction;
2343 }
2344
2345
2346 /**
2347 * Call to submit a USB Bulk transfer to a pipe.
2348 *
2349 * @usb: USB device state populated by cvmx_usb_initialize().
2350 * @pipe: Handle to the pipe for the transfer.
2351 * @urb: URB.
2352 *
2353 * Returns: A submitted transaction or NULL on failure.
2354 */
2355 static struct cvmx_usb_transaction *cvmx_usb_submit_bulk(
2356 struct cvmx_usb_state *usb,
2357 struct cvmx_usb_pipe *pipe,
2358 struct urb *urb)
2359 {
2360 return __cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK,
2361 urb->transfer_dma,
2362 urb->transfer_buffer_length,
2363 0, /* control_header */
2364 0, /* iso_start_frame */
2365 0, /* iso_number_packets */
2366 NULL, /* iso_packets */
2367 urb);
2368 }
2369
2370
2371 /**
2372 * Call to submit a USB Interrupt transfer to a pipe.
2373 *
2374 * @usb: USB device state populated by cvmx_usb_initialize().
2375 * @pipe: Handle to the pipe for the transfer.
2376 * @urb: URB returned when the callback is called.
2377 *
2378 * Returns: A submitted transaction or NULL on failure.
2379 */
2380 static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt(
2381 struct cvmx_usb_state *usb,
2382 struct cvmx_usb_pipe *pipe,
2383 struct urb *urb)
2384 {
2385 return __cvmx_usb_submit_transaction(usb, pipe,
2386 CVMX_USB_TRANSFER_INTERRUPT,
2387 urb->transfer_dma,
2388 urb->transfer_buffer_length,
2389 0, /* control_header */
2390 0, /* iso_start_frame */
2391 0, /* iso_number_packets */
2392 NULL, /* iso_packets */
2393 urb);
2394 }
2395
2396
2397 /**
2398 * Call to submit a USB Control transfer to a pipe.
2399 *
2400 * @usb: USB device state populated by cvmx_usb_initialize().
2401 * @pipe: Handle to the pipe for the transfer.
2402 * @urb: URB.
2403 *
2404 * Returns: A submitted transaction or NULL on failure.
2405 */
2406 static struct cvmx_usb_transaction *cvmx_usb_submit_control(
2407 struct cvmx_usb_state *usb,
2408 struct cvmx_usb_pipe *pipe,
2409 struct urb *urb)
2410 {
2411 int buffer_length = urb->transfer_buffer_length;
2412 uint64_t control_header = urb->setup_dma;
2413 union cvmx_usb_control_header *header =
2414 cvmx_phys_to_ptr(control_header);
2415
2416 if ((header->s.request_type & 0x80) == 0)
2417 buffer_length = le16_to_cpu(header->s.length);
2418
2419 return __cvmx_usb_submit_transaction(usb, pipe,
2420 CVMX_USB_TRANSFER_CONTROL,
2421 urb->transfer_dma, buffer_length,
2422 control_header,
2423 0, /* iso_start_frame */
2424 0, /* iso_number_packets */
2425 NULL, /* iso_packets */
2426 urb);
2427 }
2428
2429
2430 /**
2431 * Call to submit a USB Isochronous transfer to a pipe.
2432 *
2433 * @usb: USB device state populated by cvmx_usb_initialize().
2434 * @pipe: Handle to the pipe for the transfer.
2435 * @urb: URB returned when the callback is called.
2436 *
2437 * Returns: A submitted transaction or NULL on failure.
2438 */
2439 static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous(
2440 struct cvmx_usb_state *usb,
2441 struct cvmx_usb_pipe *pipe,
2442 struct urb *urb)
2443 {
2444 struct cvmx_usb_iso_packet *packets;
2445
2446 packets = (struct cvmx_usb_iso_packet *) urb->setup_packet;
2447 return __cvmx_usb_submit_transaction(usb, pipe,
2448 CVMX_USB_TRANSFER_ISOCHRONOUS,
2449 urb->transfer_dma,
2450 urb->transfer_buffer_length,
2451 0, /* control_header */
2452 urb->start_frame,
2453 urb->number_of_packets,
2454 packets, urb);
2455 }
2456
2457
2458 /**
2459 * Cancel one outstanding request in a pipe. Canceling a request
2460 * can fail if the transaction has already completed before cancel
2461 * is called. Even after a successful cancel call, it may take
2462 * a frame or two for the cvmx_usb_poll() function to call the
2463 * associated callback.
2464 *
2465 * @usb: USB device state populated by cvmx_usb_initialize().
2466 * @pipe: Pipe to cancel requests in.
2467 * @transaction: Transaction to cancel, returned by the submit function.
2468 *
2469 * Returns: 0 or a negative error code.
2470 */
2471 static int cvmx_usb_cancel(struct cvmx_usb_state *usb,
2472 struct cvmx_usb_pipe *pipe,
2473 struct cvmx_usb_transaction *transaction)
2474 {
2475 /*
2476 * If the transaction is the HEAD of the queue and scheduled. We need to
2477 * treat it special
2478 */
2479 if (list_first_entry(&pipe->transactions, typeof(*transaction), node) ==
2480 transaction && (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2481 union cvmx_usbcx_hccharx usbc_hcchar;
2482
2483 usb->pipe_for_channel[pipe->channel] = NULL;
2484 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2485
2486 CVMX_SYNCW;
2487
2488 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb,
2489 CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2490 /*
2491 * If the channel isn't enabled then the transaction already
2492 * completed.
2493 */
2494 if (usbc_hcchar.s.chena) {
2495 usbc_hcchar.s.chdis = 1;
2496 __cvmx_usb_write_csr32(usb,
2497 CVMX_USBCX_HCCHARX(pipe->channel,
2498 usb->index),
2499 usbc_hcchar.u32);
2500 }
2501 }
2502 __cvmx_usb_perform_complete(usb, pipe, transaction,
2503 CVMX_USB_COMPLETE_CANCEL);
2504 return 0;
2505 }
2506
2507
2508 /**
2509 * Cancel all outstanding requests in a pipe. Logically all this
2510 * does is call cvmx_usb_cancel() in a loop.
2511 *
2512 * @usb: USB device state populated by cvmx_usb_initialize().
2513 * @pipe: Pipe to cancel requests in.
2514 *
2515 * Returns: 0 or a negative error code.
2516 */
2517 static int cvmx_usb_cancel_all(struct cvmx_usb_state *usb,
2518 struct cvmx_usb_pipe *pipe)
2519 {
2520 struct cvmx_usb_transaction *transaction, *next;
2521
2522 /* Simply loop through and attempt to cancel each transaction */
2523 list_for_each_entry_safe(transaction, next, &pipe->transactions, node) {
2524 int result = cvmx_usb_cancel(usb, pipe, transaction);
2525 if (unlikely(result != 0))
2526 return result;
2527 }
2528 return 0;
2529 }
2530
2531
2532 /**
2533 * Close a pipe created with cvmx_usb_open_pipe().
2534 *
2535 * @usb: USB device state populated by cvmx_usb_initialize().
2536 * @pipe: Pipe to close.
2537 *
2538 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2539 * outstanding transfers.
2540 */
2541 static int cvmx_usb_close_pipe(struct cvmx_usb_state *usb,
2542 struct cvmx_usb_pipe *pipe)
2543 {
2544 /* Fail if the pipe has pending transactions */
2545 if (!list_empty(&pipe->transactions))
2546 return -EBUSY;
2547
2548 list_del(&pipe->node);
2549 kfree(pipe);
2550
2551 return 0;
2552 }
2553
2554 /**
2555 * Get the current USB protocol level frame number. The frame
2556 * number is always in the range of 0-0x7ff.
2557 *
2558 * @usb: USB device state populated by cvmx_usb_initialize().
2559 *
2560 * Returns: USB frame number
2561 */
2562 static int cvmx_usb_get_frame_number(struct cvmx_usb_state *usb)
2563 {
2564 int frame_number;
2565 union cvmx_usbcx_hfnum usbc_hfnum;
2566
2567 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb,
2568 CVMX_USBCX_HFNUM(usb->index));
2569 frame_number = usbc_hfnum.s.frnum;
2570
2571 return frame_number;
2572 }
2573
2574
2575 /**
2576 * Poll a channel for status
2577 *
2578 * @usb: USB device
2579 * @channel: Channel to poll
2580 *
2581 * Returns: Zero on success
2582 */
2583 static int __cvmx_usb_poll_channel(struct cvmx_usb_state *usb, int channel)
2584 {
2585 union cvmx_usbcx_hcintx usbc_hcint;
2586 union cvmx_usbcx_hctsizx usbc_hctsiz;
2587 union cvmx_usbcx_hccharx usbc_hcchar;
2588 struct cvmx_usb_pipe *pipe;
2589 struct cvmx_usb_transaction *transaction;
2590 int bytes_this_transfer;
2591 int bytes_in_last_packet;
2592 int packets_processed;
2593 int buffer_space_left;
2594
2595 /* Read the interrupt status bits for the channel */
2596 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb,
2597 CVMX_USBCX_HCINTX(channel, usb->index));
2598
2599 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2600 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb,
2601 CVMX_USBCX_HCCHARX(channel, usb->index));
2602
2603 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2604 /*
2605 * There seems to be a bug in CN31XX which can cause
2606 * interrupt IN transfers to get stuck until we do a
2607 * write of HCCHARX without changing things
2608 */
2609 __cvmx_usb_write_csr32(usb,
2610 CVMX_USBCX_HCCHARX(channel,
2611 usb->index),
2612 usbc_hcchar.u32);
2613 return 0;
2614 }
2615
2616 /*
2617 * In non DMA mode the channels don't halt themselves. We need
2618 * to manually disable channels that are left running
2619 */
2620 if (!usbc_hcint.s.chhltd) {
2621 if (usbc_hcchar.s.chena) {
2622 union cvmx_usbcx_hcintmskx hcintmsk;
2623 /* Disable all interrupts except CHHLTD */
2624 hcintmsk.u32 = 0;
2625 hcintmsk.s.chhltdmsk = 1;
2626 __cvmx_usb_write_csr32(usb,
2627 CVMX_USBCX_HCINTMSKX(channel,
2628 usb->index),
2629 hcintmsk.u32);
2630 usbc_hcchar.s.chdis = 1;
2631 __cvmx_usb_write_csr32(usb,
2632 CVMX_USBCX_HCCHARX(channel,
2633 usb->index),
2634 usbc_hcchar.u32);
2635 return 0;
2636 } else if (usbc_hcint.s.xfercompl) {
2637 /*
2638 * Successful IN/OUT with transfer complete.
2639 * Channel halt isn't needed.
2640 */
2641 } else {
2642 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n",
2643 usb->index, channel);
2644 return 0;
2645 }
2646 }
2647 } else {
2648 /*
2649 * There is are no interrupts that we need to process when the
2650 * channel is still running
2651 */
2652 if (!usbc_hcint.s.chhltd)
2653 return 0;
2654 }
2655
2656 /* Disable the channel interrupts now that it is done */
2657 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2658 usb->idle_hardware_channels |= (1<<channel);
2659
2660 /* Make sure this channel is tied to a valid pipe */
2661 pipe = usb->pipe_for_channel[channel];
2662 CVMX_PREFETCH(pipe, 0);
2663 CVMX_PREFETCH(pipe, 128);
2664 if (!pipe)
2665 return 0;
2666 transaction = list_first_entry(&pipe->transactions,
2667 typeof(*transaction),
2668 node);
2669 CVMX_PREFETCH(transaction, 0);
2670
2671 /*
2672 * Disconnect this pipe from the HW channel. Later the schedule
2673 * function will figure out which pipe needs to go
2674 */
2675 usb->pipe_for_channel[channel] = NULL;
2676 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2677
2678 /*
2679 * Read the channel config info so we can figure out how much data
2680 * transfered
2681 */
2682 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb,
2683 CVMX_USBCX_HCCHARX(channel, usb->index));
2684 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb,
2685 CVMX_USBCX_HCTSIZX(channel, usb->index));
2686
2687 /*
2688 * Calculating the number of bytes successfully transferred is dependent
2689 * on the transfer direction
2690 */
2691 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2692 if (usbc_hcchar.s.epdir) {
2693 /*
2694 * IN transactions are easy. For every byte received the
2695 * hardware decrements xfersize. All we need to do is subtract
2696 * the current value of xfersize from its starting value and we
2697 * know how many bytes were written to the buffer
2698 */
2699 bytes_this_transfer = transaction->xfersize -
2700 usbc_hctsiz.s.xfersize;
2701 } else {
2702 /*
2703 * OUT transaction don't decrement xfersize. Instead pktcnt is
2704 * decremented on every successful packet send. The hardware
2705 * does this when it receives an ACK, or NYET. If it doesn't
2706 * receive one of these responses pktcnt doesn't change
2707 */
2708 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2709 /*
2710 * The last packet may not be a full transfer if we didn't have
2711 * enough data
2712 */
2713 if (bytes_this_transfer > transaction->xfersize)
2714 bytes_this_transfer = transaction->xfersize;
2715 }
2716 /* Figure out how many bytes were in the last packet of the transfer */
2717 if (packets_processed)
2718 bytes_in_last_packet = bytes_this_transfer -
2719 (packets_processed - 1) * usbc_hcchar.s.mps;
2720 else
2721 bytes_in_last_packet = bytes_this_transfer;
2722
2723 /*
2724 * As a special case, setup transactions output the setup header, not
2725 * the user's data. For this reason we don't count setup data as bytes
2726 * transferred
2727 */
2728 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2729 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2730 bytes_this_transfer = 0;
2731
2732 /*
2733 * Add the bytes transferred to the running total. It is important that
2734 * bytes_this_transfer doesn't count any data that needs to be
2735 * retransmitted
2736 */
2737 transaction->actual_bytes += bytes_this_transfer;
2738 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2739 buffer_space_left = transaction->iso_packets[0].length -
2740 transaction->actual_bytes;
2741 else
2742 buffer_space_left = transaction->buffer_length -
2743 transaction->actual_bytes;
2744
2745 /*
2746 * We need to remember the PID toggle state for the next transaction.
2747 * The hardware already updated it for the next transaction
2748 */
2749 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2750
2751 /*
2752 * For high speed bulk out, assume the next transaction will need to do
2753 * a ping before proceeding. If this isn't true the ACK processing below
2754 * will clear this flag
2755 */
2756 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2757 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2758 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2759 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2760
2761 if (usbc_hcint.s.stall) {
2762 /*
2763 * STALL as a response means this transaction cannot be
2764 * completed because the device can't process transactions. Tell
2765 * the user. Any data that was transferred will be counted on
2766 * the actual bytes transferred
2767 */
2768 pipe->pid_toggle = 0;
2769 __cvmx_usb_perform_complete(usb, pipe, transaction,
2770 CVMX_USB_COMPLETE_STALL);
2771 } else if (usbc_hcint.s.xacterr) {
2772 /*
2773 * We know at least one packet worked if we get a ACK or NAK.
2774 * Reset the retry counter
2775 */
2776 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2777 transaction->retries = 0;
2778 transaction->retries++;
2779 if (transaction->retries > MAX_RETRIES) {
2780 /*
2781 * XactErr as a response means the device signaled
2782 * something wrong with the transfer. For example, PID
2783 * toggle errors cause these
2784 */
2785 __cvmx_usb_perform_complete(usb, pipe, transaction,
2786 CVMX_USB_COMPLETE_XACTERR);
2787 } else {
2788 /*
2789 * If this was a split then clear our split in progress
2790 * marker
2791 */
2792 if (usb->active_split == transaction)
2793 usb->active_split = NULL;
2794 /*
2795 * Rewind to the beginning of the transaction by anding
2796 * off the split complete bit
2797 */
2798 transaction->stage &= ~1;
2799 pipe->split_sc_frame = -1;
2800 pipe->next_tx_frame += pipe->interval;
2801 if (pipe->next_tx_frame < usb->frame_number)
2802 pipe->next_tx_frame =
2803 usb->frame_number + pipe->interval -
2804 (usb->frame_number -
2805 pipe->next_tx_frame) % pipe->interval;
2806 }
2807 } else if (usbc_hcint.s.bblerr) {
2808 /* Babble Error (BblErr) */
2809 __cvmx_usb_perform_complete(usb, pipe, transaction,
2810 CVMX_USB_COMPLETE_BABBLEERR);
2811 } else if (usbc_hcint.s.datatglerr) {
2812 /* We'll retry the exact same transaction again */
2813 transaction->retries++;
2814 } else if (usbc_hcint.s.nyet) {
2815 /*
2816 * NYET as a response is only allowed in three cases: as a
2817 * response to a ping, as a response to a split transaction, and
2818 * as a response to a bulk out. The ping case is handled by
2819 * hardware, so we only have splits and bulk out
2820 */
2821 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2822 transaction->retries = 0;
2823 /*
2824 * If there is more data to go then we need to try
2825 * again. Otherwise this transaction is complete
2826 */
2827 if ((buffer_space_left == 0) ||
2828 (bytes_in_last_packet < pipe->max_packet))
2829 __cvmx_usb_perform_complete(usb, pipe,
2830 transaction,
2831 CVMX_USB_COMPLETE_SUCCESS);
2832 } else {
2833 /*
2834 * Split transactions retry the split complete 4 times
2835 * then rewind to the start split and do the entire
2836 * transactions again
2837 */
2838 transaction->retries++;
2839 if ((transaction->retries & 0x3) == 0) {
2840 /*
2841 * Rewind to the beginning of the transaction by
2842 * anding off the split complete bit
2843 */
2844 transaction->stage &= ~1;
2845 pipe->split_sc_frame = -1;
2846 }
2847 }
2848 } else if (usbc_hcint.s.ack) {
2849 transaction->retries = 0;
2850 /*
2851 * The ACK bit can only be checked after the other error bits.
2852 * This is because a multi packet transfer may succeed in a
2853 * number of packets and then get a different response on the
2854 * last packet. In this case both ACK and the last response bit
2855 * will be set. If none of the other response bits is set, then
2856 * the last packet must have been an ACK
2857 *
2858 * Since we got an ACK, we know we don't need to do a ping on
2859 * this pipe
2860 */
2861 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2862
2863 switch (transaction->type) {
2864 case CVMX_USB_TRANSFER_CONTROL:
2865 switch (transaction->stage) {
2866 case CVMX_USB_STAGE_NON_CONTROL:
2867 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2868 /* This should be impossible */
2869 __cvmx_usb_perform_complete(usb, pipe,
2870 transaction, CVMX_USB_COMPLETE_ERROR);
2871 break;
2872 case CVMX_USB_STAGE_SETUP:
2873 pipe->pid_toggle = 1;
2874 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2875 transaction->stage =
2876 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2877 else {
2878 union cvmx_usb_control_header *header =
2879 cvmx_phys_to_ptr(transaction->control_header);
2880 if (header->s.length)
2881 transaction->stage = CVMX_USB_STAGE_DATA;
2882 else
2883 transaction->stage = CVMX_USB_STAGE_STATUS;
2884 }
2885 break;
2886 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2887 {
2888 union cvmx_usb_control_header *header =
2889 cvmx_phys_to_ptr(transaction->control_header);
2890 if (header->s.length)
2891 transaction->stage = CVMX_USB_STAGE_DATA;
2892 else
2893 transaction->stage = CVMX_USB_STAGE_STATUS;
2894 }
2895 break;
2896 case CVMX_USB_STAGE_DATA:
2897 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2898 transaction->stage =
2899 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2900 /*
2901 * For setup OUT data that are splits,
2902 * the hardware doesn't appear to count
2903 * transferred data. Here we manually
2904 * update the data transferred
2905 */
2906 if (!usbc_hcchar.s.epdir) {
2907 if (buffer_space_left < pipe->max_packet)
2908 transaction->actual_bytes +=
2909 buffer_space_left;
2910 else
2911 transaction->actual_bytes +=
2912 pipe->max_packet;
2913 }
2914 } else if ((buffer_space_left == 0) ||
2915 (bytes_in_last_packet <
2916 pipe->max_packet)) {
2917 pipe->pid_toggle = 1;
2918 transaction->stage =
2919 CVMX_USB_STAGE_STATUS;
2920 }
2921 break;
2922 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2923 if ((buffer_space_left == 0) ||
2924 (bytes_in_last_packet <
2925 pipe->max_packet)) {
2926 pipe->pid_toggle = 1;
2927 transaction->stage =
2928 CVMX_USB_STAGE_STATUS;
2929 } else {
2930 transaction->stage =
2931 CVMX_USB_STAGE_DATA;
2932 }
2933 break;
2934 case CVMX_USB_STAGE_STATUS:
2935 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2936 transaction->stage =
2937 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2938 else
2939 __cvmx_usb_perform_complete(usb, pipe,
2940 transaction,
2941 CVMX_USB_COMPLETE_SUCCESS);
2942 break;
2943 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2944 __cvmx_usb_perform_complete(usb, pipe,
2945 transaction,
2946 CVMX_USB_COMPLETE_SUCCESS);
2947 break;
2948 }
2949 break;
2950 case CVMX_USB_TRANSFER_BULK:
2951 case CVMX_USB_TRANSFER_INTERRUPT:
2952 /*
2953 * The only time a bulk transfer isn't complete when it
2954 * finishes with an ACK is during a split transaction.
2955 * For splits we need to continue the transfer if more
2956 * data is needed
2957 */
2958 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2959 if (transaction->stage ==
2960 CVMX_USB_STAGE_NON_CONTROL)
2961 transaction->stage =
2962 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2963 else {
2964 if (buffer_space_left &&
2965 (bytes_in_last_packet ==
2966 pipe->max_packet))
2967 transaction->stage =
2968 CVMX_USB_STAGE_NON_CONTROL;
2969 else {
2970 if (transaction->type ==
2971 CVMX_USB_TRANSFER_INTERRUPT)
2972 pipe->next_tx_frame +=
2973 pipe->interval;
2974 __cvmx_usb_perform_complete(
2975 usb,
2976 pipe,
2977 transaction,
2978 CVMX_USB_COMPLETE_SUCCESS);
2979 }
2980 }
2981 } else {
2982 if ((pipe->device_speed ==
2983 CVMX_USB_SPEED_HIGH) &&
2984 (pipe->transfer_type ==
2985 CVMX_USB_TRANSFER_BULK) &&
2986 (pipe->transfer_dir ==
2987 CVMX_USB_DIRECTION_OUT) &&
2988 (usbc_hcint.s.nak))
2989 pipe->flags |=
2990 __CVMX_USB_PIPE_FLAGS_NEED_PING;
2991 if (!buffer_space_left ||
2992 (bytes_in_last_packet <
2993 pipe->max_packet)) {
2994 if (transaction->type ==
2995 CVMX_USB_TRANSFER_INTERRUPT)
2996 pipe->next_tx_frame +=
2997 pipe->interval;
2998 __cvmx_usb_perform_complete(usb,
2999 pipe,
3000 transaction,
3001 CVMX_USB_COMPLETE_SUCCESS);
3002 }
3003 }
3004 break;
3005 case CVMX_USB_TRANSFER_ISOCHRONOUS:
3006 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
3007 /*
3008 * ISOCHRONOUS OUT splits don't require a
3009 * complete split stage. Instead they use a
3010 * sequence of begin OUT splits to transfer the
3011 * data 188 bytes at a time. Once the transfer
3012 * is complete, the pipe sleeps until the next
3013 * schedule interval
3014 */
3015 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
3016 /*
3017 * If no space left or this wasn't a max
3018 * size packet then this transfer is
3019 * complete. Otherwise start it again to
3020 * send the next 188 bytes
3021 */
3022 if (!buffer_space_left ||
3023 (bytes_this_transfer < 188)) {
3024 pipe->next_tx_frame += pipe->interval;
3025 __cvmx_usb_perform_complete(
3026 usb,
3027 pipe,
3028 transaction,
3029 CVMX_USB_COMPLETE_SUCCESS);
3030 }
3031 } else {
3032 if (transaction->stage ==
3033 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
3034 /*
3035 * We are in the incoming data
3036 * phase. Keep getting data
3037 * until we run out of space or
3038 * get a small packet
3039 */
3040 if ((buffer_space_left == 0) ||
3041 (bytes_in_last_packet <
3042 pipe->max_packet)) {
3043 pipe->next_tx_frame +=
3044 pipe->interval;
3045 __cvmx_usb_perform_complete(
3046 usb,
3047 pipe,
3048 transaction,
3049 CVMX_USB_COMPLETE_SUCCESS);
3050 }
3051 } else
3052 transaction->stage =
3053 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
3054 }
3055 } else {
3056 pipe->next_tx_frame += pipe->interval;
3057 __cvmx_usb_perform_complete(usb,
3058 pipe,
3059 transaction,
3060 CVMX_USB_COMPLETE_SUCCESS);
3061 }
3062 break;
3063 }
3064 } else if (usbc_hcint.s.nak) {
3065 /*
3066 * If this was a split then clear our split in progress marker.
3067 */
3068 if (usb->active_split == transaction)
3069 usb->active_split = NULL;
3070 /*
3071 * NAK as a response means the device couldn't accept the
3072 * transaction, but it should be retried in the future. Rewind
3073 * to the beginning of the transaction by anding off the split
3074 * complete bit. Retry in the next interval
3075 */
3076 transaction->retries = 0;
3077 transaction->stage &= ~1;
3078 pipe->next_tx_frame += pipe->interval;
3079 if (pipe->next_tx_frame < usb->frame_number)
3080 pipe->next_tx_frame = usb->frame_number +
3081 pipe->interval -
3082 (usb->frame_number - pipe->next_tx_frame) %
3083 pipe->interval;
3084 } else {
3085 struct cvmx_usb_port_status port;
3086 port = cvmx_usb_get_status(usb);
3087 if (port.port_enabled) {
3088 /* We'll retry the exact same transaction again */
3089 transaction->retries++;
3090 } else {
3091 /*
3092 * We get channel halted interrupts with no result bits
3093 * sets when the cable is unplugged
3094 */
3095 __cvmx_usb_perform_complete(usb, pipe, transaction,
3096 CVMX_USB_COMPLETE_ERROR);
3097 }
3098 }
3099 return 0;
3100 }
3101
3102 static void octeon_usb_port_callback(struct cvmx_usb_state *usb)
3103 {
3104 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
3105
3106 spin_unlock(&priv->lock);
3107 usb_hcd_poll_rh_status(octeon_to_hcd(priv));
3108 spin_lock(&priv->lock);
3109 }
3110
3111 /**
3112 * Poll the USB block for status and call all needed callback
3113 * handlers. This function is meant to be called in the interrupt
3114 * handler for the USB controller. It can also be called
3115 * periodically in a loop for non-interrupt based operation.
3116 *
3117 * @usb: USB device state populated by cvmx_usb_initialize().
3118 *
3119 * Returns: 0 or a negative error code.
3120 */
3121 static int cvmx_usb_poll(struct cvmx_usb_state *usb)
3122 {
3123 union cvmx_usbcx_hfnum usbc_hfnum;
3124 union cvmx_usbcx_gintsts usbc_gintsts;
3125
3126 CVMX_PREFETCH(usb, 0);
3127 CVMX_PREFETCH(usb, 1*128);
3128 CVMX_PREFETCH(usb, 2*128);
3129 CVMX_PREFETCH(usb, 3*128);
3130 CVMX_PREFETCH(usb, 4*128);
3131
3132 /* Update the frame counter */
3133 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
3134 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
3135 usb->frame_number += 0x4000;
3136 usb->frame_number &= ~0x3fffull;
3137 usb->frame_number |= usbc_hfnum.s.frnum;
3138
3139 /* Read the pending interrupts */
3140 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
3141
3142 /* Clear the interrupts now that we know about them */
3143 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
3144
3145 if (usbc_gintsts.s.rxflvl) {
3146 /*
3147 * RxFIFO Non-Empty (RxFLvl)
3148 * Indicates that there is at least one packet pending to be
3149 * read from the RxFIFO.
3150 *
3151 * In DMA mode this is handled by hardware
3152 */
3153 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3154 __cvmx_usb_poll_rx_fifo(usb);
3155 }
3156 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3157 /* Fill the Tx FIFOs when not in DMA mode */
3158 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3159 __cvmx_usb_poll_tx_fifo(usb);
3160 }
3161 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3162 union cvmx_usbcx_hprt usbc_hprt;
3163 /*
3164 * Disconnect Detected Interrupt (DisconnInt)
3165 * Asserted when a device disconnect is detected.
3166 *
3167 * Host Port Interrupt (PrtInt)
3168 * The core sets this bit to indicate a change in port status of
3169 * one of the O2P USB core ports in Host mode. The application
3170 * must read the Host Port Control and Status (HPRT) register to
3171 * determine the exact event that caused this interrupt. The
3172 * application must clear the appropriate status bit in the Host
3173 * Port Control and Status register to clear this bit.
3174 *
3175 * Call the user's port callback
3176 */
3177 octeon_usb_port_callback(usb);
3178 /* Clear the port change bits */
3179 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb,
3180 CVMX_USBCX_HPRT(usb->index));
3181 usbc_hprt.s.prtena = 0;
3182 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index),
3183 usbc_hprt.u32);
3184 }
3185 if (usbc_gintsts.s.hchint) {
3186 /*
3187 * Host Channels Interrupt (HChInt)
3188 * The core sets this bit to indicate that an interrupt is
3189 * pending on one of the channels of the core (in Host mode).
3190 * The application must read the Host All Channels Interrupt
3191 * (HAINT) register to determine the exact number of the channel
3192 * on which the interrupt occurred, and then read the
3193 * corresponding Host Channel-n Interrupt (HCINTn) register to
3194 * determine the exact cause of the interrupt. The application
3195 * must clear the appropriate status bit in the HCINTn register
3196 * to clear this bit.
3197 */
3198 union cvmx_usbcx_haint usbc_haint;
3199 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
3200 while (usbc_haint.u32) {
3201 int channel;
3202
3203 channel = __fls(usbc_haint.u32);
3204 __cvmx_usb_poll_channel(usb, channel);
3205 usbc_haint.u32 ^= 1<<channel;
3206 }
3207 }
3208
3209 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3210
3211 return 0;
3212 }
3213
3214 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3215 static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd)
3216 {
3217 return (struct octeon_hcd *)(hcd->hcd_priv);
3218 }
3219
3220 static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd)
3221 {
3222 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3223 unsigned long flags;
3224
3225 spin_lock_irqsave(&priv->lock, flags);
3226 cvmx_usb_poll(&priv->usb);
3227 spin_unlock_irqrestore(&priv->lock, flags);
3228 return IRQ_HANDLED;
3229 }
3230
3231 static int octeon_usb_start(struct usb_hcd *hcd)
3232 {
3233 hcd->state = HC_STATE_RUNNING;
3234 return 0;
3235 }
3236
3237 static void octeon_usb_stop(struct usb_hcd *hcd)
3238 {
3239 hcd->state = HC_STATE_HALT;
3240 }
3241
3242 static int octeon_usb_get_frame_number(struct usb_hcd *hcd)
3243 {
3244 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3245
3246 return cvmx_usb_get_frame_number(&priv->usb);
3247 }
3248
3249 static int octeon_usb_urb_enqueue(struct usb_hcd *hcd,
3250 struct urb *urb,
3251 gfp_t mem_flags)
3252 {
3253 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3254 struct device *dev = hcd->self.controller;
3255 struct cvmx_usb_transaction *transaction = NULL;
3256 struct cvmx_usb_pipe *pipe;
3257 unsigned long flags;
3258 struct cvmx_usb_iso_packet *iso_packet;
3259 struct usb_host_endpoint *ep = urb->ep;
3260
3261 urb->status = 0;
3262 INIT_LIST_HEAD(&urb->urb_list); /* not enqueued on dequeue_list */
3263 spin_lock_irqsave(&priv->lock, flags);
3264
3265 if (!ep->hcpriv) {
3266 enum cvmx_usb_transfer transfer_type;
3267 enum cvmx_usb_speed speed;
3268 int split_device = 0;
3269 int split_port = 0;
3270 switch (usb_pipetype(urb->pipe)) {
3271 case PIPE_ISOCHRONOUS:
3272 transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS;
3273 break;
3274 case PIPE_INTERRUPT:
3275 transfer_type = CVMX_USB_TRANSFER_INTERRUPT;
3276 break;
3277 case PIPE_CONTROL:
3278 transfer_type = CVMX_USB_TRANSFER_CONTROL;
3279 break;
3280 default:
3281 transfer_type = CVMX_USB_TRANSFER_BULK;
3282 break;
3283 }
3284 switch (urb->dev->speed) {
3285 case USB_SPEED_LOW:
3286 speed = CVMX_USB_SPEED_LOW;
3287 break;
3288 case USB_SPEED_FULL:
3289 speed = CVMX_USB_SPEED_FULL;
3290 break;
3291 default:
3292 speed = CVMX_USB_SPEED_HIGH;
3293 break;
3294 }
3295 /*
3296 * For slow devices on high speed ports we need to find the hub
3297 * that does the speed translation so we know where to send the
3298 * split transactions.
3299 */
3300 if (speed != CVMX_USB_SPEED_HIGH) {
3301 /*
3302 * Start at this device and work our way up the usb
3303 * tree.
3304 */
3305 struct usb_device *dev = urb->dev;
3306 while (dev->parent) {
3307 /*
3308 * If our parent is high speed then he'll
3309 * receive the splits.
3310 */
3311 if (dev->parent->speed == USB_SPEED_HIGH) {
3312 split_device = dev->parent->devnum;
3313 split_port = dev->portnum;
3314 break;
3315 }
3316 /*
3317 * Move up the tree one level. If we make it all
3318 * the way up the tree, then the port must not
3319 * be in high speed mode and we don't need a
3320 * split.
3321 */
3322 dev = dev->parent;
3323 }
3324 }
3325 pipe = cvmx_usb_open_pipe(&priv->usb, usb_pipedevice(urb->pipe),
3326 usb_pipeendpoint(urb->pipe), speed,
3327 le16_to_cpu(ep->desc.wMaxPacketSize)
3328 & 0x7ff,
3329 transfer_type,
3330 usb_pipein(urb->pipe) ?
3331 CVMX_USB_DIRECTION_IN :
3332 CVMX_USB_DIRECTION_OUT,
3333 urb->interval,
3334 (le16_to_cpu(ep->desc.wMaxPacketSize)
3335 >> 11) & 0x3,
3336 split_device, split_port);
3337 if (!pipe) {
3338 spin_unlock_irqrestore(&priv->lock, flags);
3339 dev_dbg(dev, "Failed to create pipe\n");
3340 return -ENOMEM;
3341 }
3342 ep->hcpriv = pipe;
3343 } else {
3344 pipe = ep->hcpriv;
3345 }
3346
3347 switch (usb_pipetype(urb->pipe)) {
3348 case PIPE_ISOCHRONOUS:
3349 dev_dbg(dev, "Submit isochronous to %d.%d\n",
3350 usb_pipedevice(urb->pipe),
3351 usb_pipeendpoint(urb->pipe));
3352 /*
3353 * Allocate a structure to use for our private list of
3354 * isochronous packets.
3355 */
3356 iso_packet = kmalloc(urb->number_of_packets *
3357 sizeof(struct cvmx_usb_iso_packet),
3358 GFP_ATOMIC);
3359 if (iso_packet) {
3360 int i;
3361 /* Fill the list with the data from the URB */
3362 for (i = 0; i < urb->number_of_packets; i++) {
3363 iso_packet[i].offset =
3364 urb->iso_frame_desc[i].offset;
3365 iso_packet[i].length =
3366 urb->iso_frame_desc[i].length;
3367 iso_packet[i].status =
3368 CVMX_USB_COMPLETE_ERROR;
3369 }
3370 /*
3371 * Store a pointer to the list in the URB setup_packet
3372 * field. We know this currently isn't being used and
3373 * this saves us a bunch of logic.
3374 */
3375 urb->setup_packet = (char *)iso_packet;
3376 transaction = cvmx_usb_submit_isochronous(&priv->usb,
3377 pipe, urb);
3378 /*
3379 * If submit failed we need to free our private packet
3380 * list.
3381 */
3382 if (!transaction) {
3383 urb->setup_packet = NULL;
3384 kfree(iso_packet);
3385 }
3386 }
3387 break;
3388 case PIPE_INTERRUPT:
3389 dev_dbg(dev, "Submit interrupt to %d.%d\n",
3390 usb_pipedevice(urb->pipe),
3391 usb_pipeendpoint(urb->pipe));
3392 transaction = cvmx_usb_submit_interrupt(&priv->usb, pipe, urb);
3393 break;
3394 case PIPE_CONTROL:
3395 dev_dbg(dev, "Submit control to %d.%d\n",
3396 usb_pipedevice(urb->pipe),
3397 usb_pipeendpoint(urb->pipe));
3398 transaction = cvmx_usb_submit_control(&priv->usb, pipe, urb);
3399 break;
3400 case PIPE_BULK:
3401 dev_dbg(dev, "Submit bulk to %d.%d\n",
3402 usb_pipedevice(urb->pipe),
3403 usb_pipeendpoint(urb->pipe));
3404 transaction = cvmx_usb_submit_bulk(&priv->usb, pipe, urb);
3405 break;
3406 }
3407 if (!transaction) {
3408 spin_unlock_irqrestore(&priv->lock, flags);
3409 dev_dbg(dev, "Failed to submit\n");
3410 return -ENOMEM;
3411 }
3412 urb->hcpriv = transaction;
3413 spin_unlock_irqrestore(&priv->lock, flags);
3414 return 0;
3415 }
3416
3417 static void octeon_usb_urb_dequeue_work(unsigned long arg)
3418 {
3419 struct urb *urb;
3420 struct urb *next;
3421 unsigned long flags;
3422 struct octeon_hcd *priv = (struct octeon_hcd *)arg;
3423
3424 spin_lock_irqsave(&priv->lock, flags);
3425
3426 list_for_each_entry_safe(urb, next, &priv->dequeue_list, urb_list) {
3427 list_del_init(&urb->urb_list);
3428 cvmx_usb_cancel(&priv->usb, urb->ep->hcpriv, urb->hcpriv);
3429 }
3430
3431 spin_unlock_irqrestore(&priv->lock, flags);
3432 }
3433
3434 static int octeon_usb_urb_dequeue(struct usb_hcd *hcd,
3435 struct urb *urb,
3436 int status)
3437 {
3438 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3439 unsigned long flags;
3440
3441 if (!urb->dev)
3442 return -EINVAL;
3443
3444 spin_lock_irqsave(&priv->lock, flags);
3445
3446 urb->status = status;
3447 list_add_tail(&urb->urb_list, &priv->dequeue_list);
3448
3449 spin_unlock_irqrestore(&priv->lock, flags);
3450
3451 tasklet_schedule(&priv->dequeue_tasklet);
3452
3453 return 0;
3454 }
3455
3456 static void octeon_usb_endpoint_disable(struct usb_hcd *hcd,
3457 struct usb_host_endpoint *ep)
3458 {
3459 struct device *dev = hcd->self.controller;
3460
3461 if (ep->hcpriv) {
3462 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3463 struct cvmx_usb_pipe *pipe = ep->hcpriv;
3464 unsigned long flags;
3465 spin_lock_irqsave(&priv->lock, flags);
3466 cvmx_usb_cancel_all(&priv->usb, pipe);
3467 if (cvmx_usb_close_pipe(&priv->usb, pipe))
3468 dev_dbg(dev, "Closing pipe %p failed\n", pipe);
3469 spin_unlock_irqrestore(&priv->lock, flags);
3470 ep->hcpriv = NULL;
3471 }
3472 }
3473
3474 static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf)
3475 {
3476 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3477 struct cvmx_usb_port_status port_status;
3478 unsigned long flags;
3479
3480 spin_lock_irqsave(&priv->lock, flags);
3481 port_status = cvmx_usb_get_status(&priv->usb);
3482 spin_unlock_irqrestore(&priv->lock, flags);
3483 buf[0] = 0;
3484 buf[0] = port_status.connect_change << 1;
3485
3486 return (buf[0] != 0);
3487 }
3488
3489 static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
3490 {
3491 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3492 struct device *dev = hcd->self.controller;
3493 struct cvmx_usb_port_status usb_port_status;
3494 int port_status;
3495 struct usb_hub_descriptor *desc;
3496 unsigned long flags;
3497
3498 switch (typeReq) {
3499 case ClearHubFeature:
3500 dev_dbg(dev, "ClearHubFeature\n");
3501 switch (wValue) {
3502 case C_HUB_LOCAL_POWER:
3503 case C_HUB_OVER_CURRENT:
3504 /* Nothing required here */
3505 break;
3506 default:
3507 return -EINVAL;
3508 }
3509 break;
3510 case ClearPortFeature:
3511 dev_dbg(dev, "ClearPortFeature\n");
3512 if (wIndex != 1) {
3513 dev_dbg(dev, " INVALID\n");
3514 return -EINVAL;
3515 }
3516
3517 switch (wValue) {
3518 case USB_PORT_FEAT_ENABLE:
3519 dev_dbg(dev, " ENABLE\n");
3520 spin_lock_irqsave(&priv->lock, flags);
3521 cvmx_usb_disable(&priv->usb);
3522 spin_unlock_irqrestore(&priv->lock, flags);
3523 break;
3524 case USB_PORT_FEAT_SUSPEND:
3525 dev_dbg(dev, " SUSPEND\n");
3526 /* Not supported on Octeon */
3527 break;
3528 case USB_PORT_FEAT_POWER:
3529 dev_dbg(dev, " POWER\n");
3530 /* Not supported on Octeon */
3531 break;
3532 case USB_PORT_FEAT_INDICATOR:
3533 dev_dbg(dev, " INDICATOR\n");
3534 /* Port inidicator not supported */
3535 break;
3536 case USB_PORT_FEAT_C_CONNECTION:
3537 dev_dbg(dev, " C_CONNECTION\n");
3538 /* Clears drivers internal connect status change flag */
3539 spin_lock_irqsave(&priv->lock, flags);
3540 priv->usb.port_status =
3541 cvmx_usb_get_status(&priv->usb);
3542 spin_unlock_irqrestore(&priv->lock, flags);
3543 break;
3544 case USB_PORT_FEAT_C_RESET:
3545 dev_dbg(dev, " C_RESET\n");
3546 /*
3547 * Clears the driver's internal Port Reset Change flag.
3548 */
3549 spin_lock_irqsave(&priv->lock, flags);
3550 priv->usb.port_status =
3551 cvmx_usb_get_status(&priv->usb);
3552 spin_unlock_irqrestore(&priv->lock, flags);
3553 break;
3554 case USB_PORT_FEAT_C_ENABLE:
3555 dev_dbg(dev, " C_ENABLE\n");
3556 /*
3557 * Clears the driver's internal Port Enable/Disable
3558 * Change flag.
3559 */
3560 spin_lock_irqsave(&priv->lock, flags);
3561 priv->usb.port_status =
3562 cvmx_usb_get_status(&priv->usb);
3563 spin_unlock_irqrestore(&priv->lock, flags);
3564 break;
3565 case USB_PORT_FEAT_C_SUSPEND:
3566 dev_dbg(dev, " C_SUSPEND\n");
3567 /*
3568 * Clears the driver's internal Port Suspend Change
3569 * flag, which is set when resume signaling on the host
3570 * port is complete.
3571 */
3572 break;
3573 case USB_PORT_FEAT_C_OVER_CURRENT:
3574 dev_dbg(dev, " C_OVER_CURRENT\n");
3575 /* Clears the driver's overcurrent Change flag */
3576 spin_lock_irqsave(&priv->lock, flags);
3577 priv->usb.port_status =
3578 cvmx_usb_get_status(&priv->usb);
3579 spin_unlock_irqrestore(&priv->lock, flags);
3580 break;
3581 default:
3582 dev_dbg(dev, " UNKNOWN\n");
3583 return -EINVAL;
3584 }
3585 break;
3586 case GetHubDescriptor:
3587 dev_dbg(dev, "GetHubDescriptor\n");
3588 desc = (struct usb_hub_descriptor *)buf;
3589 desc->bDescLength = 9;
3590 desc->bDescriptorType = 0x29;
3591 desc->bNbrPorts = 1;
3592 desc->wHubCharacteristics = 0x08;
3593 desc->bPwrOn2PwrGood = 1;
3594 desc->bHubContrCurrent = 0;
3595 desc->u.hs.DeviceRemovable[0] = 0;
3596 desc->u.hs.DeviceRemovable[1] = 0xff;
3597 break;
3598 case GetHubStatus:
3599 dev_dbg(dev, "GetHubStatus\n");
3600 *(__le32 *) buf = 0;
3601 break;
3602 case GetPortStatus:
3603 dev_dbg(dev, "GetPortStatus\n");
3604 if (wIndex != 1) {
3605 dev_dbg(dev, " INVALID\n");
3606 return -EINVAL;
3607 }
3608
3609 spin_lock_irqsave(&priv->lock, flags);
3610 usb_port_status = cvmx_usb_get_status(&priv->usb);
3611 spin_unlock_irqrestore(&priv->lock, flags);
3612 port_status = 0;
3613
3614 if (usb_port_status.connect_change) {
3615 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
3616 dev_dbg(dev, " C_CONNECTION\n");
3617 }
3618
3619 if (usb_port_status.port_enabled) {
3620 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
3621 dev_dbg(dev, " C_ENABLE\n");
3622 }
3623
3624 if (usb_port_status.connected) {
3625 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
3626 dev_dbg(dev, " CONNECTION\n");
3627 }
3628
3629 if (usb_port_status.port_enabled) {
3630 port_status |= (1 << USB_PORT_FEAT_ENABLE);
3631 dev_dbg(dev, " ENABLE\n");
3632 }
3633
3634 if (usb_port_status.port_over_current) {
3635 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
3636 dev_dbg(dev, " OVER_CURRENT\n");
3637 }
3638
3639 if (usb_port_status.port_powered) {
3640 port_status |= (1 << USB_PORT_FEAT_POWER);
3641 dev_dbg(dev, " POWER\n");
3642 }
3643
3644 if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) {
3645 port_status |= USB_PORT_STAT_HIGH_SPEED;
3646 dev_dbg(dev, " HIGHSPEED\n");
3647 } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) {
3648 port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
3649 dev_dbg(dev, " LOWSPEED\n");
3650 }
3651
3652 *((__le32 *) buf) = cpu_to_le32(port_status);
3653 break;
3654 case SetHubFeature:
3655 dev_dbg(dev, "SetHubFeature\n");
3656 /* No HUB features supported */
3657 break;
3658 case SetPortFeature:
3659 dev_dbg(dev, "SetPortFeature\n");
3660 if (wIndex != 1) {
3661 dev_dbg(dev, " INVALID\n");
3662 return -EINVAL;
3663 }
3664
3665 switch (wValue) {
3666 case USB_PORT_FEAT_SUSPEND:
3667 dev_dbg(dev, " SUSPEND\n");
3668 return -EINVAL;
3669 case USB_PORT_FEAT_POWER:
3670 dev_dbg(dev, " POWER\n");
3671 return -EINVAL;
3672 case USB_PORT_FEAT_RESET:
3673 dev_dbg(dev, " RESET\n");
3674 spin_lock_irqsave(&priv->lock, flags);
3675 cvmx_usb_disable(&priv->usb);
3676 if (cvmx_usb_enable(&priv->usb))
3677 dev_dbg(dev, "Failed to enable the port\n");
3678 spin_unlock_irqrestore(&priv->lock, flags);
3679 return 0;
3680 case USB_PORT_FEAT_INDICATOR:
3681 dev_dbg(dev, " INDICATOR\n");
3682 /* Not supported */
3683 break;
3684 default:
3685 dev_dbg(dev, " UNKNOWN\n");
3686 return -EINVAL;
3687 }
3688 break;
3689 default:
3690 dev_dbg(dev, "Unknown root hub request\n");
3691 return -EINVAL;
3692 }
3693 return 0;
3694 }
3695
3696 static const struct hc_driver octeon_hc_driver = {
3697 .description = "Octeon USB",
3698 .product_desc = "Octeon Host Controller",
3699 .hcd_priv_size = sizeof(struct octeon_hcd),
3700 .irq = octeon_usb_irq,
3701 .flags = HCD_MEMORY | HCD_USB2,
3702 .start = octeon_usb_start,
3703 .stop = octeon_usb_stop,
3704 .urb_enqueue = octeon_usb_urb_enqueue,
3705 .urb_dequeue = octeon_usb_urb_dequeue,
3706 .endpoint_disable = octeon_usb_endpoint_disable,
3707 .get_frame_number = octeon_usb_get_frame_number,
3708 .hub_status_data = octeon_usb_hub_status_data,
3709 .hub_control = octeon_usb_hub_control,
3710 .map_urb_for_dma = octeon_map_urb_for_dma,
3711 .unmap_urb_for_dma = octeon_unmap_urb_for_dma,
3712 };
3713
3714 static int octeon_usb_probe(struct platform_device *pdev)
3715 {
3716 int status;
3717 int initialize_flags;
3718 int usb_num;
3719 struct resource *res_mem;
3720 struct device_node *usbn_node;
3721 int irq = platform_get_irq(pdev, 0);
3722 struct device *dev = &pdev->dev;
3723 struct octeon_hcd *priv;
3724 struct usb_hcd *hcd;
3725 unsigned long flags;
3726 u32 clock_rate = 48000000;
3727 bool is_crystal_clock = false;
3728 const char *clock_type;
3729 int i;
3730
3731 if (dev->of_node == NULL) {
3732 dev_err(dev, "Error: empty of_node\n");
3733 return -ENXIO;
3734 }
3735 usbn_node = dev->of_node->parent;
3736
3737 i = of_property_read_u32(usbn_node,
3738 "refclk-frequency", &clock_rate);
3739 if (i) {
3740 dev_err(dev, "No USBN \"refclk-frequency\"\n");
3741 return -ENXIO;
3742 }
3743 switch (clock_rate) {
3744 case 12000000:
3745 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
3746 break;
3747 case 24000000:
3748 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
3749 break;
3750 case 48000000:
3751 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
3752 break;
3753 default:
3754 dev_err(dev, "Illebal USBN \"refclk-frequency\" %u\n",
3755 clock_rate);
3756 return -ENXIO;
3757
3758 }
3759
3760 i = of_property_read_string(usbn_node,
3761 "refclk-type", &clock_type);
3762
3763 if (!i && strcmp("crystal", clock_type) == 0)
3764 is_crystal_clock = true;
3765
3766 if (is_crystal_clock)
3767 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
3768 else
3769 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
3770
3771 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3772 if (res_mem == NULL) {
3773 dev_err(dev, "found no memory resource\n");
3774 return -ENXIO;
3775 }
3776 usb_num = (res_mem->start >> 44) & 1;
3777
3778 if (irq < 0) {
3779 /* Defective device tree, but we know how to fix it. */
3780 irq_hw_number_t hwirq = usb_num ? (1 << 6) + 17 : 56;
3781 irq = irq_create_mapping(NULL, hwirq);
3782 }
3783
3784 /*
3785 * Set the DMA mask to 64bits so we get buffers already translated for
3786 * DMA.
3787 */
3788 dev->coherent_dma_mask = ~0;
3789 dev->dma_mask = &dev->coherent_dma_mask;
3790
3791 /*
3792 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3793 * IOB priority registers. Under heavy network load USB
3794 * hardware can be starved by the IOB causing a crash. Give
3795 * it a priority boost if it has been waiting more than 400
3796 * cycles to avoid this situation.
3797 *
3798 * Testing indicates that a cnt_val of 8192 is not sufficient,
3799 * but no failures are seen with 4096. We choose a value of
3800 * 400 to give a safety factor of 10.
3801 */
3802 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
3803 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt;
3804
3805 pri_cnt.u64 = 0;
3806 pri_cnt.s.cnt_enb = 1;
3807 pri_cnt.s.cnt_val = 400;
3808 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64);
3809 }
3810
3811 hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev));
3812 if (!hcd) {
3813 dev_dbg(dev, "Failed to allocate memory for HCD\n");
3814 return -1;
3815 }
3816 hcd->uses_new_polling = 1;
3817 priv = (struct octeon_hcd *)hcd->hcd_priv;
3818
3819 spin_lock_init(&priv->lock);
3820
3821 tasklet_init(&priv->dequeue_tasklet, octeon_usb_urb_dequeue_work,
3822 (unsigned long)priv);
3823 INIT_LIST_HEAD(&priv->dequeue_list);
3824
3825 status = cvmx_usb_initialize(&priv->usb, usb_num, initialize_flags);
3826 if (status) {
3827 dev_dbg(dev, "USB initialization failed with %d\n", status);
3828 kfree(hcd);
3829 return -1;
3830 }
3831
3832 /* This delay is needed for CN3010, but I don't know why... */
3833 mdelay(10);
3834
3835 spin_lock_irqsave(&priv->lock, flags);
3836 cvmx_usb_poll(&priv->usb);
3837 spin_unlock_irqrestore(&priv->lock, flags);
3838
3839 status = usb_add_hcd(hcd, irq, 0);
3840 if (status) {
3841 dev_dbg(dev, "USB add HCD failed with %d\n", status);
3842 kfree(hcd);
3843 return -1;
3844 }
3845 device_wakeup_enable(hcd->self.controller);
3846
3847 dev_info(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
3848
3849 return 0;
3850 }
3851
3852 static int octeon_usb_remove(struct platform_device *pdev)
3853 {
3854 int status;
3855 struct device *dev = &pdev->dev;
3856 struct usb_hcd *hcd = dev_get_drvdata(dev);
3857 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3858 unsigned long flags;
3859
3860 usb_remove_hcd(hcd);
3861 tasklet_kill(&priv->dequeue_tasklet);
3862 spin_lock_irqsave(&priv->lock, flags);
3863 status = cvmx_usb_shutdown(&priv->usb);
3864 spin_unlock_irqrestore(&priv->lock, flags);
3865 if (status)
3866 dev_dbg(dev, "USB shutdown failed with %d\n", status);
3867
3868 kfree(hcd);
3869
3870 return 0;
3871 }
3872
3873 static struct of_device_id octeon_usb_match[] = {
3874 {
3875 .compatible = "cavium,octeon-5750-usbc",
3876 },
3877 {},
3878 };
3879
3880 static struct platform_driver octeon_usb_driver = {
3881 .driver = {
3882 .name = "OcteonUSB",
3883 .owner = THIS_MODULE,
3884 .of_match_table = octeon_usb_match,
3885 },
3886 .probe = octeon_usb_probe,
3887 .remove = octeon_usb_remove,
3888 };
3889
3890 static int __init octeon_usb_driver_init(void)
3891 {
3892 if (usb_disabled())
3893 return 0;
3894
3895 return platform_driver_register(&octeon_usb_driver);
3896 }
3897 module_init(octeon_usb_driver_init);
3898
3899 static void __exit octeon_usb_driver_exit(void)
3900 {
3901 if (usb_disabled())
3902 return;
3903
3904 platform_driver_unregister(&octeon_usb_driver);
3905 }
3906 module_exit(octeon_usb_driver_exit);
3907
3908 MODULE_LICENSE("GPL");
3909 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3910 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");
Linux with added FPC-III support