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ext4: reduce contention on s_orphan_lock
[linux/fpc-iii.git] / drivers / staging / rts5139 / ms.c
blob390292ad456659c60b5fe2149cc051acb15f6049
1 /* Driver for Realtek RTS51xx USB card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 * Maintainer:
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
24 */
25
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/vmalloc.h>
31
32 #include "debug.h"
33 #include "trace.h"
34 #include "rts51x.h"
35 #include "rts51x_transport.h"
36 #include "rts51x_scsi.h"
37 #include "rts51x_card.h"
38 #include "ms.h"
39
40 static inline void ms_set_err_code(struct rts51x_chip *chip, u8 err_code)
41 {
42 struct ms_info *ms_card = &(chip->ms_card);
43
44 ms_card->err_code = err_code;
45 }
46
47 static inline int ms_check_err_code(struct rts51x_chip *chip, u8 err_code)
48 {
49 struct ms_info *ms_card = &(chip->ms_card);
50
51 return ms_card->err_code == err_code;
52 }
53
54 static int ms_parse_err_code(struct rts51x_chip *chip)
55 {
56 TRACE_RET(chip, STATUS_FAIL);
57 }
58
59 static int ms_transfer_tpc(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,
60 u8 cnt, u8 cfg)
61 {
62 struct ms_info *ms_card = &(chip->ms_card);
63 int retval;
64
65 RTS51X_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);
66
67 rts51x_init_cmd(chip);
68
69 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
70 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
71 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
72 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
73 PINGPONG_BUFFER);
74
75 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
76 MS_TRANSFER_START | trans_mode);
77 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
78 MS_TRANSFER_END);
79
80 rts51x_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
81
82 retval = rts51x_send_cmd(chip, MODE_CR, 100);
83 if (retval != STATUS_SUCCESS)
84 TRACE_RET(chip, retval);
85
86 retval = rts51x_get_rsp(chip, 2, 5000);
87 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
88 rts51x_clear_ms_error(chip);
89 ms_set_err_code(chip, MS_TO_ERROR);
90 TRACE_RET(chip, ms_parse_err_code(chip));
91 }
92
93 if (!(tpc & 0x08)) { /* Read Packet */
94 /* Check CRC16 & Ready Timeout */
95 if (chip->rsp_buf[1] & MS_CRC16_ERR) {
96 ms_set_err_code(chip, MS_CRC16_ERROR);
97 TRACE_RET(chip, ms_parse_err_code(chip));
98 }
99 } else { /* Write Packet */
100 if (CHK_MSPRO(ms_card) && !(chip->rsp_buf[1] & 0x80)) {
101 if (chip->rsp_buf[1] & (MS_INT_ERR | MS_INT_CMDNK)) {
102 ms_set_err_code(chip, MS_CMD_NK);
103 TRACE_RET(chip, ms_parse_err_code(chip));
104 }
105 }
106 }
107
108 /* Check Timeout of Ready Signal */
109 if (chip->rsp_buf[1] & MS_RDY_TIMEOUT) {
110 rts51x_clear_ms_error(chip);
111 ms_set_err_code(chip, MS_TO_ERROR);
112 TRACE_RET(chip, ms_parse_err_code(chip));
113 }
114
115 return STATUS_SUCCESS;
116 }
117
118 int ms_transfer_data(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,
119 u16 sec_cnt, u8 cfg, int mode_2k, int use_sg, void *buf,
120 int buf_len)
121 {
122 struct ms_info *ms_card = &(chip->ms_card);
123 int retval;
124 u8 val, err_code = 0, flag = 0;
125 enum dma_data_direction dir;
126 unsigned int pipe;
127
128 if (!buf || !buf_len)
129 TRACE_RET(chip, STATUS_FAIL);
130
131 if (trans_mode == MS_TM_AUTO_READ) {
132 pipe = RCV_BULK_PIPE(chip);
133 dir = DMA_FROM_DEVICE;
134 flag = MODE_CDIR;
135 err_code = MS_FLASH_READ_ERROR;
136 } else if (trans_mode == MS_TM_AUTO_WRITE) {
137 pipe = SND_BULK_PIPE(chip);
138 dir = DMA_TO_DEVICE;
139 flag = MODE_CDOR;
140 err_code = MS_FLASH_WRITE_ERROR;
141 } else {
142 TRACE_RET(chip, STATUS_FAIL);
143 }
144
145 rts51x_init_cmd(chip);
146
147 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
148 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF,
149 (u8) (sec_cnt >> 8));
150 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
151 (u8) sec_cnt);
152 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
153 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
154 RING_BUFFER);
155
156 if (mode_2k)
157 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,
158 MS_2K_SECTOR_MODE);
159 else
160 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,
161 0);
162
163 rts51x_trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
164
165 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
166 MS_TRANSFER_START | trans_mode);
167 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
168 MS_TRANSFER_END);
169
170 retval = rts51x_send_cmd(chip, flag | STAGE_MS_STATUS, 100);
171 if (retval != STATUS_SUCCESS)
172 TRACE_RET(chip, retval);
173
174 retval =
175 rts51x_transfer_data_rcc(chip, pipe, buf, buf_len, use_sg, NULL,
176 15000, flag);
177 if (retval != STATUS_SUCCESS) {
178 ms_set_err_code(chip, err_code);
179 rts51x_clear_ms_error(chip);
180 TRACE_RET(chip, retval);
181 }
182
183 retval = rts51x_get_rsp(chip, 3, 15000);
184 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
185 ms_set_err_code(chip, err_code);
186 rts51x_clear_ms_error(chip);
187 TRACE_RET(chip, STATUS_FAIL);
188 }
189
190 ms_card->last_rw_int = val = chip->rsp_buf[1];
191 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
192 TRACE_RET(chip, STATUS_FAIL);
193
194 return STATUS_SUCCESS;
195 }
196
197 int ms_write_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,
198 int data_len)
199 {
200 struct ms_info *ms_card = &(chip->ms_card);
201 int retval, i;
202
203 if (!data || (data_len < cnt))
204 TRACE_RET(chip, STATUS_ERROR);
205
206 rts51x_init_cmd(chip);
207
208 for (i = 0; i < cnt; i++) {
209 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,
210 data[i]);
211 }
212 if (cnt % 2)
213 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i,
214 0xFF, 0xFF);
215
216 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
217 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
218 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
219 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
220 PINGPONG_BUFFER);
221
222 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
223 MS_TRANSFER_START | MS_TM_WRITE_BYTES);
224 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
225 MS_TRANSFER_END);
226
227 retval = rts51x_send_cmd(chip, MODE_CR, 100);
228 if (retval != STATUS_SUCCESS)
229 TRACE_RET(chip, retval);
230
231 retval = rts51x_get_rsp(chip, 1, 5000);
232 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
233 u8 val = 0;
234
235 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
236 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
237
238 rts51x_clear_ms_error(chip);
239
240 if (!(tpc & 0x08)) { /* Read Packet */
241 /* Check CRC16 & Ready Timeout */
242 if (val & MS_CRC16_ERR) {
243 ms_set_err_code(chip, MS_CRC16_ERROR);
244 TRACE_RET(chip, ms_parse_err_code(chip));
245 }
246 } else { /* Write Packet */
247 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
248 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
249 ms_set_err_code(chip, MS_CMD_NK);
250 TRACE_RET(chip,
251 ms_parse_err_code(chip));
252 }
253 }
254 }
255
256 /* Check Timeout of Ready Signal */
257 if (val & MS_RDY_TIMEOUT) {
258 ms_set_err_code(chip, MS_TO_ERROR);
259 TRACE_RET(chip, ms_parse_err_code(chip));
260 }
261
262 ms_set_err_code(chip, MS_TO_ERROR);
263 TRACE_RET(chip, ms_parse_err_code(chip));
264 }
265
266 return STATUS_SUCCESS;
267 }
268
269 int ms_read_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,
270 int data_len)
271 {
272 struct ms_info *ms_card = &(chip->ms_card);
273 int retval, i;
274
275 if (!data)
276 TRACE_RET(chip, STATUS_ERROR);
277
278 rts51x_init_cmd(chip);
279
280 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
281 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
282 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
283 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
284 PINGPONG_BUFFER);
285
286 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
287 MS_TRANSFER_START | MS_TM_READ_BYTES);
288 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
289 MS_TRANSFER_END);
290
291 for (i = 0; i < data_len - 1; i++)
292 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
293
294 if (data_len % 2)
295 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0,
296 0);
297 else
298 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
299 0, 0);
300
301 retval = rts51x_send_cmd(chip, MODE_CR, 100);
302 if (retval != STATUS_SUCCESS)
303 TRACE_RET(chip, retval);
304
305 retval = rts51x_get_rsp(chip, data_len + 1, 5000);
306 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
307 u8 val = 0;
308
309 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
310 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
311
312 rts51x_clear_ms_error(chip);
313
314 if (!(tpc & 0x08)) { /* Read Packet */
315 /* Check CRC16 & Ready Timeout */
316 if (val & MS_CRC16_ERR) {
317 ms_set_err_code(chip, MS_CRC16_ERROR);
318 TRACE_RET(chip, ms_parse_err_code(chip));
319 }
320 } else { /* Write Packet */
321 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
322 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
323 ms_set_err_code(chip, MS_CMD_NK);
324 TRACE_RET(chip,
325 ms_parse_err_code(chip));
326 }
327 }
328 }
329
330 /* Check Timeout of Ready Signal */
331 if (val & MS_RDY_TIMEOUT) {
332 ms_set_err_code(chip, MS_TO_ERROR);
333 TRACE_RET(chip, ms_parse_err_code(chip));
334 }
335
336 ms_set_err_code(chip, MS_TO_ERROR);
337 TRACE_RET(chip, ms_parse_err_code(chip));
338 }
339
340 rts51x_read_rsp_buf(chip, 1, data, data_len);
341
342 return STATUS_SUCCESS;
343 }
344
345 int ms_set_rw_reg_addr(struct rts51x_chip *chip,
346 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
347 {
348 int retval, i;
349 u8 data[4];
350
351 data[0] = read_start;
352 data[1] = read_cnt;
353 data[2] = write_start;
354 data[3] = write_cnt;
355
356 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
357 retval =
358 ms_write_bytes(chip, SET_RW_REG_ADRS, 4, NO_WAIT_INT, data,
359 4);
360 if (retval == STATUS_SUCCESS)
361 return STATUS_SUCCESS;
362 rts51x_clear_ms_error(chip);
363 }
364
365 TRACE_RET(chip, STATUS_FAIL);
366 }
367
368 static int ms_send_cmd(struct rts51x_chip *chip, u8 cmd, u8 cfg)
369 {
370 u8 data[2];
371
372 data[0] = cmd;
373 data[1] = 0;
374
375 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
376 }
377
378 static int ms_set_cmd(struct rts51x_chip *chip,
379 u8 read_start, u8 read_count,
380 u8 write_start, u8 write_count,
381 u8 cmd, u8 cfg, u8 *data, int data_len, u8 *int_stat)
382 {
383 int retval, i;
384 u8 val;
385
386 if (!data || (data_len <= 0) || (data_len > 128)) {
387 RTS51X_DEBUGP("ms_set_cmd (data_len = %d)\n", data_len);
388 TRACE_RET(chip, STATUS_FAIL);
389 }
390
391 retval =
392 ms_set_rw_reg_addr(chip, read_start, read_count, write_start,
393 write_count);
394 if (retval != STATUS_SUCCESS)
395 TRACE_RET(chip, retval);
396
397 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
398 retval =
399 ms_write_bytes(chip, WRITE_REG, write_count, NO_WAIT_INT,
400 data, data_len);
401 if (retval == STATUS_SUCCESS)
402 break;
403 }
404 if (i == MS_MAX_RETRY_COUNT)
405 TRACE_RET(chip, STATUS_FAIL);
406
407 ms_set_err_code(chip, MS_NO_ERROR);
408
409 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
410 retval = ms_send_cmd(chip, cmd, WAIT_INT);
411 if (retval == STATUS_SUCCESS)
412 break;
413 }
414 if (i == MS_MAX_RETRY_COUNT)
415 TRACE_RET(chip, STATUS_FAIL);
416 /* GET_INT Register */
417 ms_set_err_code(chip, MS_NO_ERROR);
418 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
419 if (retval != STATUS_SUCCESS)
420 TRACE_RET(chip, retval);
421
422 if (int_stat)
423 *int_stat = val;
424
425 return STATUS_SUCCESS;
426 }
427
428 #ifdef MS_SPEEDUP
429 static int ms_auto_set_cmd(struct rts51x_chip *chip,
430 u8 read_start, u8 read_count,
431 u8 write_start, u8 write_count,
432 u8 cmd, u8 cfg, u8 *data, int data_len,
433 u8 *int_stat)
434 {
435 int retval;
436 int i;
437
438 if (!data || (data_len <= 0) || (data_len > 128)) {
439 RTS51X_DEBUGP("ms_auto_set_cmd (data_len = %d)\n", data_len);
440 TRACE_RET(chip, STATUS_FAIL);
441 }
442
443 rts51x_init_cmd(chip);
444
445 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_START, 0xFF, read_start);
446 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_COUNT, 0xFF, read_count);
447 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_START, 0xFF, write_start);
448 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_COUNT, 0xFF, write_count);
449 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_COMMAND, 0xFF, cmd);
450
451 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
452 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
453 PINGPONG_BUFFER);
454
455 for (i = 0; i < data_len; i++) {
456 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,
457 data[i]);
458 }
459
460 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
461 MS_TRANSFER_START | MS_TM_SET_CMD);
462 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
463 MS_TRANSFER_END);
464
465 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);
466 if (retval != STATUS_SUCCESS)
467 TRACE_RET(chip, retval);
468
469 retval = rts51x_get_rsp(chip, 3, 5000);
470
471 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
472 rts51x_clear_ms_error(chip);
473 TRACE_RET(chip, STATUS_FAIL);
474 }
475
476 if (int_stat)
477 *int_stat = chip->rsp_buf[2];
478
479 return STATUS_SUCCESS;
480 }
481 #endif
482
483 static int ms_set_init_para(struct rts51x_chip *chip)
484 {
485 struct ms_info *ms_card = &(chip->ms_card);
486 int retval;
487
488 if (CHK_HG8BIT(ms_card)) {
489 if (chip->asic_code)
490 ms_card->ms_clock = chip->option.asic_ms_hg_clk;
491 else
492 ms_card->ms_clock = chip->option.fpga_ms_hg_clk;
493 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
494 if (chip->asic_code)
495 ms_card->ms_clock = chip->option.asic_ms_4bit_clk;
496 else
497 ms_card->ms_clock = chip->option.fpga_ms_4bit_clk;
498 } else {
499 if (chip->asic_code)
500 ms_card->ms_clock = 38;
501 else
502 ms_card->ms_clock = CLK_40;
503 }
504
505 retval = switch_clock(chip, ms_card->ms_clock);
506 if (retval != STATUS_SUCCESS)
507 TRACE_RET(chip, retval);
508
509 retval = rts51x_select_card(chip, MS_CARD);
510 if (retval != STATUS_SUCCESS)
511 TRACE_RET(chip, retval);
512
513 return STATUS_SUCCESS;
514 }
515
516 int ms_switch_clock(struct rts51x_chip *chip)
517 {
518 struct ms_info *ms_card = &(chip->ms_card);
519 int retval;
520
521 retval = rts51x_select_card(chip, MS_CARD);
522 if (retval != STATUS_SUCCESS)
523 TRACE_RET(chip, retval);
524
525 retval = switch_clock(chip, ms_card->ms_clock);
526 if (retval != STATUS_SUCCESS)
527 TRACE_RET(chip, retval);
528
529 return STATUS_SUCCESS;
530 }
531
532 static void ms_pull_ctl_disable(struct rts51x_chip *chip)
533 {
534 if (CHECK_PKG(chip, LQFP48)) {
535 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
536 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
537 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
538 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
539 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
540 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
541 } else {
542 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
543 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
544 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
545 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
546 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
547 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
548 }
549 }
550
551 static void ms_pull_ctl_enable(struct rts51x_chip *chip)
552 {
553 if (CHECK_PKG(chip, LQFP48)) {
554 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
555 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
556 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
557 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
558 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
559 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
560 } else {
561 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
562 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
563 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
564 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
565 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
566 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
567 }
568 }
569
570 static int ms_prepare_reset(struct rts51x_chip *chip)
571 {
572 struct ms_info *ms_card = &(chip->ms_card);
573 int retval;
574
575 ms_card->ms_type = 0;
576 ms_card->check_ms_flow = 0;
577 ms_card->switch_8bit_fail = 0;
578 ms_card->delay_write.delay_write_flag = 0;
579
580 ms_card->pro_under_formatting = 0;
581
582 rts51x_init_cmd(chip);
583
584 if (chip->asic_code) {
585 ms_pull_ctl_enable(chip);
586 } else {
587 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
588 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
589 }
590 /* Tri-state MS output */
591 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
592
593 if (!chip->option.FT2_fast_mode) {
594 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
595 POWER_OFF);
596 }
597
598 retval = rts51x_send_cmd(chip, MODE_C, 100);
599 if (retval != STATUS_SUCCESS)
600 TRACE_RET(chip, retval);
601
602 if (!chip->option.FT2_fast_mode) {
603 wait_timeout(250);
604
605 rts51x_card_power_on(chip, MS_CARD);
606 wait_timeout(150);
607
608 #ifdef SUPPORT_OCP
609 rts51x_get_card_status(chip, &(chip->card_status));
610 /* get OCP status */
611 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
612
613 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
614 RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
615 chip->ocp_stat);
616 TRACE_RET(chip, STATUS_FAIL);
617 }
618 #endif
619 }
620
621 rts51x_init_cmd(chip);
622
623 /* Enable MS Output */
624 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN,
625 MS_OUTPUT_EN);
626
627 /* Reset Registers */
628 if (chip->asic_code)
629 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,
630 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
631 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
632 else
633 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,
634 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
635 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
636 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
637 NO_WAIT_INT | NO_AUTO_READ_INT_REG);
638
639 retval = rts51x_send_cmd(chip, MODE_C, 100);
640 if (retval != STATUS_SUCCESS)
641 TRACE_RET(chip, retval);
642
643 return ms_set_init_para(chip);
644 }
645
646 static int ms_identify_media_type(struct rts51x_chip *chip, int switch_8bit_bus)
647 {
648 struct ms_info *ms_card = &(chip->ms_card);
649 int retval, i;
650 u8 val;
651
652 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
653 if (retval != STATUS_SUCCESS)
654 TRACE_RET(chip, retval);
655
656 /* Get Register form MS-PRO card */
657 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
658 retval =
659 ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6,
660 NO_WAIT_INT);
661 if (retval == STATUS_SUCCESS)
662 break;
663 }
664 if (i == MS_MAX_RETRY_COUNT)
665 TRACE_RET(chip, STATUS_FAIL);
666
667 RTS51X_READ_REG(chip, PPBUF_BASE2 + 2, &val);
668 RTS51X_DEBUGP("Type register: 0x%x\n", val);
669 if (val != 0x01) {
670 if (val != 0x02)
671 ms_card->check_ms_flow = 1;
672 TRACE_RET(chip, STATUS_FAIL);
673 }
674 /* Category Register */
675 RTS51X_READ_REG(chip, PPBUF_BASE2 + 4, &val);
676 RTS51X_DEBUGP("Category register: 0x%x\n", val);
677 if (val != 0) {
678 ms_card->check_ms_flow = 1;
679 TRACE_RET(chip, STATUS_FAIL);
680 }
681 /* Class Register */
682 RTS51X_READ_REG(chip, PPBUF_BASE2 + 5, &val);
683 RTS51X_DEBUGP("Class register: 0x%x\n", val);
684 if (val == 0) {
685 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
686 if (val & WRT_PRTCT)
687 chip->card_wp |= MS_CARD;
688 else
689 chip->card_wp &= ~MS_CARD;
690 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
691 chip->card_wp |= MS_CARD;
692 } else {
693 ms_card->check_ms_flow = 1;
694 TRACE_RET(chip, STATUS_FAIL);
695 }
696
697 ms_card->ms_type |= TYPE_MSPRO;
698
699 /* Check MSPro-HG Card, use IF Mode Register to distinguish */
700 RTS51X_READ_REG(chip, PPBUF_BASE2 + 3, &val);
701 RTS51X_DEBUGP("IF Mode register: 0x%x\n", val);
702 if (val == 0) {
703 ms_card->ms_type &= 0x0F;
704 } else if (val == 7) {
705 if (switch_8bit_bus)
706 ms_card->ms_type |= MS_HG;
707 else
708 ms_card->ms_type &= 0x0F;
709 } else {
710 TRACE_RET(chip, STATUS_FAIL);
711 }
712
713 /* end Procedure to identify Media Type */
714 return STATUS_SUCCESS;
715 }
716
717 static int ms_confirm_cpu_startup(struct rts51x_chip *chip)
718 {
719 int retval, i, k;
720 u8 val;
721
722 /* Confirm CPU StartUp */
723 k = 0;
724 do {
725 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
726 TRACE_RET(chip, STATUS_FAIL);
727
728 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
729 retval =
730 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
731 1);
732 if (retval == STATUS_SUCCESS)
733 break;
734 }
735 if (i == MS_MAX_RETRY_COUNT)
736 TRACE_RET(chip, STATUS_FAIL);
737
738 if (k > 100)
739 TRACE_RET(chip, STATUS_FAIL);
740 k++;
741 wait_timeout(100);
742 } while (!(val & INT_REG_CED));
743
744 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
745 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
746 if (retval == STATUS_SUCCESS)
747 break;
748 }
749 if (i == MS_MAX_RETRY_COUNT)
750 TRACE_RET(chip, STATUS_FAIL);
751
752 if (val & INT_REG_ERR) {
753 if (val & INT_REG_CMDNK) { /* CMDNK = 1 */
754 chip->card_wp |= (MS_CARD);
755 } else { /* CMDNK = 0 */
756 TRACE_RET(chip, STATUS_FAIL);
757 }
758 }
759 /*-- end confirm CPU startup */
760
761 return STATUS_SUCCESS;
762 }
763
764 static int ms_switch_parallel_bus(struct rts51x_chip *chip)
765 {
766 int retval, i;
767 u8 data[2];
768
769 data[0] = PARALLEL_4BIT_IF;
770 data[1] = 0;
771 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
772 retval =
773 ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
774 if (retval == STATUS_SUCCESS)
775 break;
776 }
777 if (retval != STATUS_SUCCESS)
778 TRACE_RET(chip, retval);
779
780 return STATUS_SUCCESS;
781 }
782
783 static int ms_switch_8bit_bus(struct rts51x_chip *chip)
784 {
785 struct ms_info *ms_card = &(chip->ms_card);
786 int retval, i;
787 u8 data[2];
788
789 data[0] = PARALLEL_8BIT_IF;
790 data[1] = 0;
791 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
792 retval =
793 ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
794 if (retval == STATUS_SUCCESS)
795 break;
796 }
797 if (retval != STATUS_SUCCESS)
798 TRACE_RET(chip, STATUS_FAIL);
799
800 RTS51X_WRITE_REG(chip, MS_CFG, 0x98,
801 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
802 ms_card->ms_type |= MS_8BIT;
803
804 retval = ms_set_init_para(chip);
805 if (retval != STATUS_SUCCESS)
806 TRACE_RET(chip, retval);
807
808 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
809 retval =
810 ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
811 NO_WAIT_INT);
812 if (retval != STATUS_SUCCESS)
813 TRACE_RET(chip, retval);
814 }
815
816 return STATUS_SUCCESS;
817 }
818
819 static int ms_pro_reset_flow(struct rts51x_chip *chip, int switch_8bit_bus)
820 {
821 struct ms_info *ms_card = &(chip->ms_card);
822 int retval, i;
823
824 for (i = 0; i < 3; i++) {
825 retval = ms_prepare_reset(chip);
826 if (retval != STATUS_SUCCESS)
827 TRACE_RET(chip, retval);
828
829 retval = ms_identify_media_type(chip, switch_8bit_bus);
830 if (retval != STATUS_SUCCESS)
831 TRACE_RET(chip, retval);
832
833 retval = ms_confirm_cpu_startup(chip);
834 if (retval != STATUS_SUCCESS)
835 TRACE_RET(chip, retval);
836
837 retval = ms_switch_parallel_bus(chip);
838 if (retval != STATUS_SUCCESS) {
839 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
840 TRACE_RET(chip, STATUS_FAIL);
841 continue;
842 } else {
843 break;
844 }
845 }
846
847 if (retval != STATUS_SUCCESS)
848 TRACE_RET(chip, retval);
849
850 RTS51X_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
851
852 RTS51X_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
853
854 retval = ms_set_init_para(chip);
855 if (retval != STATUS_SUCCESS)
856 TRACE_RET(chip, retval);
857
858 if (CHK_MSHG(ms_card) && switch_8bit_bus) {
859 retval = ms_switch_8bit_bus(chip);
860 if (retval != STATUS_SUCCESS) {
861 ms_card->switch_8bit_fail = 1;
862 TRACE_RET(chip, retval);
863 }
864 }
865
866 return STATUS_SUCCESS;
867 }
868
869 #ifdef XC_POWERCLASS
870 static int msxc_change_power(struct rts51x_chip *chip, u8 mode)
871 {
872 int retval;
873 u8 buf[6];
874
875 rts51x_ms_cleanup_work(chip);
876
877 /* Set Parameter Register */
878 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
879 if (retval != STATUS_SUCCESS)
880 TRACE_RET(chip, retval);
881
882 buf[0] = 0;
883 buf[1] = mode;
884 buf[2] = 0;
885 buf[3] = 0;
886 buf[4] = 0;
887 buf[5] = 0;
888
889 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
890 if (retval != STATUS_SUCCESS)
891 TRACE_RET(chip, retval);
892
893 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
894 if (retval != STATUS_SUCCESS)
895 TRACE_RET(chip, retval);
896
897 RTS51X_READ_REG(chip, MS_TRANS_CFG, buf);
898 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
899 TRACE_RET(chip, STATUS_FAIL);
900
901 return STATUS_SUCCESS;
902 }
903 #endif
904
905 static int ms_read_attribute_info(struct rts51x_chip *chip)
906 {
907 struct ms_info *ms_card = &(chip->ms_card);
908 int retval, i;
909 u8 val, *buf, class_code, device_type, sub_class, data[16];
910 u16 total_blk = 0, blk_size = 0;
911 #ifdef SUPPORT_MSXC
912 u32 xc_total_blk = 0, xc_blk_size = 0;
913 #endif
914 u32 sys_info_addr = 0, sys_info_size;
915 #ifdef SUPPORT_PCGL_1P18
916 u32 model_name_addr = 0, model_name_size;
917 int found_sys_info = 0, found_model_name = 0;
918 #endif
919
920 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
921 if (retval != STATUS_SUCCESS)
922 TRACE_RET(chip, retval);
923
924 if (CHK_MS8BIT(ms_card))
925 data[0] = PARALLEL_8BIT_IF;
926 else
927 data[0] = PARALLEL_4BIT_IF;
928 data[1] = 0;
929
930 data[2] = 0x40;
931 data[3] = 0;
932 data[4] = 0;
933 data[5] = 0;
934 /* Start address 0 */
935 data[6] = 0;
936 data[7] = 0;
937
938 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
939 retval =
940 ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data,
941 8);
942 if (retval == STATUS_SUCCESS)
943 break;
944 }
945 if (retval != STATUS_SUCCESS)
946 TRACE_RET(chip, retval);
947
948 buf = kmalloc(64 * 512, GFP_KERNEL);
949 if (buf == NULL)
950 TRACE_RET(chip, STATUS_NOMEM);
951
952 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
953 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
954 if (retval != STATUS_SUCCESS)
955 continue;
956
957 retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);
958 if (retval != STATUS_SUCCESS) {
959 kfree(buf);
960 TRACE_RET(chip, STATUS_FAIL);
961 }
962 if (!(val & MS_INT_BREQ)) {
963 kfree(buf);
964 TRACE_RET(chip, STATUS_FAIL);
965 }
966
967 retval =
968 ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
969 0x40, WAIT_INT, 0, 0, buf, 64 * 512);
970 if (retval == STATUS_SUCCESS)
971 break;
972 else
973 rts51x_clear_ms_error(chip);
974 }
975 if (retval != STATUS_SUCCESS) {
976 kfree(buf);
977 TRACE_RET(chip, retval);
978 }
979
980 i = 0;
981 do {
982 retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);
983 if (retval != STATUS_SUCCESS) {
984 kfree(buf);
985 TRACE_RET(chip, retval);
986 }
987
988 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
989 break;
990
991 retval =
992 ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA,
993 0, WAIT_INT);
994 if (retval != STATUS_SUCCESS) {
995 kfree(buf);
996 TRACE_RET(chip, retval);
997 }
998
999 i++;
1000 } while (i < 1024);
1001
1002 if (retval != STATUS_SUCCESS) {
1003 kfree(buf);
1004 TRACE_RET(chip, retval);
1005 }
1006
1007 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
1008 /* Signature code is wrong */
1009 kfree(buf);
1010 TRACE_RET(chip, STATUS_FAIL);
1011 }
1012
1013 if ((buf[4] < 1) || (buf[4] > 12)) {
1014 kfree(buf);
1015 TRACE_RET(chip, STATUS_FAIL);
1016 }
1017
1018 for (i = 0; i < buf[4]; i++) {
1019 int cur_addr_off = 16 + i * 12;
1020
1021 #ifdef SUPPORT_MSXC
1022 if ((buf[cur_addr_off + 8] == 0x10)
1023 || (buf[cur_addr_off + 8] == 0x13)) {
1024 #else
1025 if (buf[cur_addr_off + 8] == 0x10) {
1026 #endif
1027 sys_info_addr = ((u32) buf[cur_addr_off + 0] << 24) |
1028 ((u32) buf[cur_addr_off + 1] << 16) |
1029 ((u32) buf[cur_addr_off + 2] << 8) |
1030 buf[cur_addr_off + 3];
1031 sys_info_size =
1032 ((u32) buf[cur_addr_off + 4] << 24) |
1033 ((u32) buf[cur_addr_off + 5] << 16) |
1034 ((u32) buf[cur_addr_off + 6] << 8) |
1035 buf[cur_addr_off + 7];
1036 RTS51X_DEBUGP("sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
1037 sys_info_addr, sys_info_size);
1038 if (sys_info_size != 96) {
1039 kfree(buf);
1040 TRACE_RET(chip, STATUS_FAIL);
1041 }
1042 if (sys_info_addr < 0x1A0) {
1043 kfree(buf);
1044 TRACE_RET(chip, STATUS_FAIL);
1045 }
1046 if ((sys_info_size + sys_info_addr) > 0x8000) {
1047 kfree(buf);
1048 TRACE_RET(chip, STATUS_FAIL);
1049 }
1050 #ifdef SUPPORT_MSXC
1051 if (buf[cur_addr_off + 8] == 0x13)
1052 ms_card->ms_type |= MS_XC;
1053 #endif
1054 #ifdef SUPPORT_PCGL_1P18
1055 found_sys_info = 1;
1056 #else
1057 break;
1058 #endif
1059 }
1060 #ifdef SUPPORT_PCGL_1P18
1061 if (buf[cur_addr_off + 8] == 0x15) {
1062 model_name_addr = ((u32) buf[cur_addr_off + 0] << 24) |
1063 ((u32) buf[cur_addr_off + 1] << 16) |
1064 ((u32) buf[cur_addr_off + 2] << 8) |
1065 buf[cur_addr_off + 3];
1066 model_name_size =
1067 ((u32) buf[cur_addr_off + 4] << 24) |
1068 ((u32) buf[cur_addr_off + 5] << 16) |
1069 ((u32) buf[cur_addr_off + 6] << 8) |
1070 buf[cur_addr_off + 7];
1071 RTS51X_DEBUGP("model_name_addr = 0x%x, model_name_size = 0x%x\n",
1072 model_name_addr, model_name_size);
1073 if (model_name_size != 48) {
1074 kfree(buf);
1075 TRACE_RET(chip, STATUS_FAIL);
1076 }
1077 if (model_name_addr < 0x1A0) {
1078 kfree(buf);
1079 TRACE_RET(chip, STATUS_FAIL);
1080 }
1081 if ((model_name_size + model_name_addr) > 0x8000) {
1082 kfree(buf);
1083 TRACE_RET(chip, STATUS_FAIL);
1084 }
1085
1086 found_model_name = 1;
1087 }
1088
1089 if (found_sys_info && found_model_name)
1090 break;
1091 #endif
1092 }
1093
1094 if (i == buf[4]) {
1095 kfree(buf);
1096 TRACE_RET(chip, STATUS_FAIL);
1097 }
1098
1099 class_code = buf[sys_info_addr + 0];
1100 device_type = buf[sys_info_addr + 56];
1101 sub_class = buf[sys_info_addr + 46];
1102 #ifdef SUPPORT_MSXC
1103 if (CHK_MSXC(ms_card)) {
1104 xc_total_blk = ((u32) buf[sys_info_addr + 6] << 24) |
1105 ((u32) buf[sys_info_addr + 7] << 16) |
1106 ((u32) buf[sys_info_addr + 8] << 8) |
1107 buf[sys_info_addr + 9];
1108 xc_blk_size = ((u32) buf[sys_info_addr + 32] << 24) |
1109 ((u32) buf[sys_info_addr + 33] << 16) |
1110 ((u32) buf[sys_info_addr + 34] << 8) |
1111 buf[sys_info_addr + 35];
1112 RTS51X_DEBUGP("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1113 xc_total_blk, xc_blk_size);
1114 } else {
1115 total_blk =
1116 ((u16) buf[sys_info_addr + 6] << 8) | buf[sys_info_addr +
1117 7];
1118 blk_size =
1119 ((u16) buf[sys_info_addr + 2] << 8) | buf[sys_info_addr +
1120 3];
1121 RTS51X_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk,
1122 blk_size);
1123 }
1124 #else
1125 total_blk =
1126 ((u16) buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1127 blk_size = ((u16) buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1128 RTS51X_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk,
1129 blk_size);
1130 #endif
1131
1132 RTS51X_DEBUGP("class_code = 0x%x, device_type = 0x%x,"
1133 "sub_class = 0x%x\n",
1134 class_code, device_type, sub_class);
1135
1136 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1137 #ifdef SUPPORT_PCGL_1P18
1138 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1139 #endif
1140
1141 kfree(buf);
1142
1143 /* Confirm System Information */
1144 #ifdef SUPPORT_MSXC
1145 if (CHK_MSXC(ms_card)) {
1146 if (class_code != 0x03)
1147 TRACE_RET(chip, STATUS_FAIL);
1148 } else {
1149 if (class_code != 0x02)
1150 TRACE_RET(chip, STATUS_FAIL);
1151 }
1152 #else
1153 if (class_code != 0x02)
1154 TRACE_RET(chip, STATUS_FAIL);
1155 #endif
1156
1157 if (device_type != 0x00) {
1158 if ((device_type == 0x01) || (device_type == 0x02)
1159 || (device_type == 0x03))
1160 chip->card_wp |= MS_CARD;
1161 else
1162 TRACE_RET(chip, STATUS_FAIL);
1163 }
1164 if (sub_class & 0xC0)
1165 TRACE_RET(chip, STATUS_FAIL);
1166
1167 RTS51X_DEBUGP("class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1168 class_code, device_type, sub_class);
1169
1170 #ifdef SUPPORT_MSXC
1171 if (CHK_MSXC(ms_card)) {
1172 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =
1173 xc_total_blk * xc_blk_size;
1174 } else {
1175 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =
1176 total_blk * blk_size;
1177 }
1178 #else
1179 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =
1180 total_blk * blk_size;
1181 #endif
1182
1183 return STATUS_SUCCESS;
1184 }
1185
1186 #ifdef SUPPORT_MAGIC_GATE
1187 int mg_set_tpc_para_sub(struct rts51x_chip *chip, int type, u8 mg_entry_num);
1188 #endif
1189
1190 static int reset_ms_pro(struct rts51x_chip *chip)
1191 {
1192 struct ms_info *ms_card = &(chip->ms_card);
1193 int retval;
1194 #ifdef XC_POWERCLASS
1195 u8 change_power_class = 2;
1196 #endif
1197
1198 #ifdef XC_POWERCLASS
1199 Retry:
1200 #endif
1201 retval = ms_pro_reset_flow(chip, 1);
1202 if (retval != STATUS_SUCCESS) {
1203 if (ms_card->switch_8bit_fail) {
1204 retval = ms_pro_reset_flow(chip, 0);
1205 if (retval != STATUS_SUCCESS)
1206 TRACE_RET(chip, retval);
1207 } else {
1208 TRACE_RET(chip, retval);
1209 }
1210 }
1211
1212 retval = ms_read_attribute_info(chip);
1213 if (retval != STATUS_SUCCESS)
1214 TRACE_RET(chip, retval);
1215 #ifdef XC_POWERCLASS
1216 if (CHK_HG8BIT(ms_card))
1217 change_power_class = 0;
1218
1219 if (change_power_class && CHK_MSXC(ms_card)) {
1220 u8 power_class_mode = (ms_card->raw_sys_info[46] & 0x18) >> 3;
1221 RTS51X_DEBUGP("power_class_mode = 0x%x", power_class_mode);
1222 if (change_power_class > power_class_mode)
1223 change_power_class = power_class_mode;
1224 if (change_power_class) {
1225 retval = msxc_change_power(chip, change_power_class);
1226 if (retval != STATUS_SUCCESS) {
1227 change_power_class--;
1228 goto Retry;
1229 }
1230 }
1231 }
1232 #endif
1233
1234 #ifdef SUPPORT_MAGIC_GATE
1235 retval = mg_set_tpc_para_sub(chip, 0, 0);
1236 if (retval != STATUS_SUCCESS)
1237 TRACE_RET(chip, retval);
1238 #endif
1239
1240 if (CHK_HG8BIT(ms_card))
1241 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1242 else
1243 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1244
1245 return STATUS_SUCCESS;
1246 }
1247
1248 static int ms_read_status_reg(struct rts51x_chip *chip)
1249 {
1250 int retval;
1251 u8 val[2];
1252
1253 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1254 if (retval != STATUS_SUCCESS)
1255 TRACE_RET(chip, retval);
1256
1257 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1258 if (retval != STATUS_SUCCESS)
1259 TRACE_RET(chip, retval);
1260 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1261 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1262 TRACE_RET(chip, STATUS_FAIL);
1263 }
1264
1265 return STATUS_SUCCESS;
1266 }
1267
1268 static int ms_check_boot_block(struct rts51x_chip *chip, u16 block_addr)
1269 {
1270 struct ms_info *ms_card = &(chip->ms_card);
1271 int retval;
1272 u8 extra[MS_EXTRA_SIZE], data[10], val = 0;
1273
1274 if (CHK_MS4BIT(ms_card)) {
1275 /* Parallel interface */
1276 data[0] = 0x88;
1277 } else {
1278 /* Serial interface */
1279 data[0] = 0x80;
1280 }
1281 /* Block Address */
1282 data[1] = 0;
1283 data[2] = (u8) (block_addr >> 8);
1284 data[3] = (u8) block_addr;
1285 /* Page Number
1286 * Extra data access mode */
1287 data[4] = 0x40;
1288 data[5] = 0;
1289
1290 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1291 BLOCK_READ, WAIT_INT, data, 6, &val);
1292 if (retval != STATUS_SUCCESS)
1293 TRACE_RET(chip, retval);
1294
1295 if (val & INT_REG_CMDNK) {
1296 ms_set_err_code(chip, MS_CMD_NK);
1297 TRACE_RET(chip, STATUS_FAIL);
1298 }
1299 if (val & INT_REG_CED) {
1300 if (val & INT_REG_ERR) {
1301 retval = ms_read_status_reg(chip);
1302 if (retval != STATUS_SUCCESS)
1303 TRACE_RET(chip, retval);
1304 retval =
1305 ms_set_rw_reg_addr(chip, OverwriteFlag,
1306 MS_EXTRA_SIZE, SystemParm, 6);
1307 if (retval != STATUS_SUCCESS)
1308 TRACE_RET(chip, retval);
1309 }
1310 }
1311
1312 retval =
1313 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, extra,
1314 MS_EXTRA_SIZE);
1315 if (retval != STATUS_SUCCESS)
1316 TRACE_RET(chip, retval);
1317
1318 if (!(extra[0] & BLOCK_OK) || (extra[1] & NOT_BOOT_BLOCK))
1319 TRACE_RET(chip, STATUS_FAIL);
1320
1321 return STATUS_SUCCESS;
1322 }
1323
1324 static int ms_read_extra_data(struct rts51x_chip *chip,
1325 u16 block_addr, u8 page_num, u8 *buf,
1326 int buf_len)
1327 {
1328 struct ms_info *ms_card = &(chip->ms_card);
1329 int retval;
1330 u8 val = 0, data[10];
1331
1332 if (CHK_MS4BIT(ms_card)) {
1333 /* Parallel interface */
1334 data[0] = 0x88;
1335 } else {
1336 /* Serial interface */
1337 data[0] = 0x80;
1338 }
1339 /* Block Address */
1340 data[1] = 0;
1341 data[2] = (u8) (block_addr >> 8);
1342 data[3] = (u8) block_addr;
1343 /* Page Number
1344 * Extra data access mode */
1345 data[4] = 0x40;
1346 data[5] = page_num;
1347
1348 #ifdef MS_SPEEDUP
1349 retval =
1350 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1351 BLOCK_READ, WAIT_INT, data, 6, &val);
1352 #else
1353 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1354 BLOCK_READ, WAIT_INT, data, 6, &val);
1355 #endif
1356 if (retval != STATUS_SUCCESS)
1357 TRACE_RET(chip, retval);
1358
1359 if (val & INT_REG_CMDNK) {
1360 ms_set_err_code(chip, MS_CMD_NK);
1361 TRACE_RET(chip, STATUS_FAIL);
1362 }
1363 if (val & INT_REG_CED) {
1364 if (val & INT_REG_ERR) {
1365 retval = ms_read_status_reg(chip);
1366 if (retval != STATUS_SUCCESS)
1367 TRACE_RET(chip, retval);
1368 retval =
1369 ms_set_rw_reg_addr(chip, OverwriteFlag,
1370 MS_EXTRA_SIZE, SystemParm, 6);
1371 if (retval != STATUS_SUCCESS)
1372 TRACE_RET(chip, retval);
1373 }
1374 }
1375
1376 retval =
1377 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data,
1378 MS_EXTRA_SIZE);
1379 if (retval != STATUS_SUCCESS)
1380 TRACE_RET(chip, retval);
1381
1382 if (buf && buf_len) {
1383 if (buf_len > MS_EXTRA_SIZE)
1384 buf_len = MS_EXTRA_SIZE;
1385 memcpy(buf, data, buf_len);
1386 }
1387
1388 return STATUS_SUCCESS;
1389 }
1390
1391 static int ms_write_extra_data(struct rts51x_chip *chip,
1392 u16 block_addr, u8 page_num, u8 *buf,
1393 int buf_len)
1394 {
1395 struct ms_info *ms_card = &(chip->ms_card);
1396 int retval, i;
1397 u8 val = 0, data[16];
1398
1399 if (!buf || (buf_len < MS_EXTRA_SIZE))
1400 TRACE_RET(chip, STATUS_FAIL);
1401 /* Write REG */
1402 if (CHK_MS4BIT(ms_card)) {
1403 /* Parallel interface */
1404 data[0] = 0x88;
1405 } else {
1406 /* Serial interface */
1407 data[0] = 0x80;
1408 }
1409 /* Block Address */
1410 data[1] = 0;
1411 data[2] = (u8) (block_addr >> 8);
1412 data[3] = (u8) block_addr;
1413 /* Page Number
1414 * Extra data access mode */
1415 data[4] = 0x40;
1416 data[5] = page_num;
1417
1418 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1419 data[i] = buf[i - 6];
1420
1421 #ifdef MS_SPEEDUP
1422 retval =
1423 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
1424 6 + MS_EXTRA_SIZE, BLOCK_WRITE, WAIT_INT, data, 16,
1425 &val);
1426 #else
1427 retval =
1428 ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
1429 6 + MS_EXTRA_SIZE, BLOCK_WRITE, WAIT_INT, data, 16,
1430 &val);
1431 #endif
1432 if (retval != STATUS_SUCCESS)
1433 TRACE_RET(chip, retval);
1434
1435 if (val & INT_REG_CMDNK) {
1436 ms_set_err_code(chip, MS_CMD_NK);
1437 TRACE_RET(chip, STATUS_FAIL);
1438 }
1439 if (val & INT_REG_CED) {
1440 if (val & INT_REG_ERR) {
1441 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1442 TRACE_RET(chip, STATUS_FAIL);
1443 }
1444 }
1445
1446 return STATUS_SUCCESS;
1447 }
1448
1449 static int ms_read_page(struct rts51x_chip *chip, u16 block_addr, u8 page_num)
1450 {
1451 struct ms_info *ms_card = &(chip->ms_card);
1452 int retval;
1453 u8 val = 0, data[6];
1454
1455 if (CHK_MS4BIT(ms_card)) {
1456 /* Parallel interface */
1457 data[0] = 0x88;
1458 } else {
1459 /* Serial interface */
1460 data[0] = 0x80;
1461 }
1462 /* Block Address */
1463 data[1] = 0;
1464 data[2] = (u8) (block_addr >> 8);
1465 data[3] = (u8) block_addr;
1466 /* Page Number
1467 * Single page access mode */
1468 data[4] = 0x20;
1469 data[5] = page_num;
1470
1471 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1472 BLOCK_READ, WAIT_INT, data, 6, &val);
1473 if (retval != STATUS_SUCCESS)
1474 TRACE_RET(chip, retval);
1475
1476 if (val & INT_REG_CMDNK) {
1477 ms_set_err_code(chip, MS_CMD_NK);
1478 TRACE_RET(chip, STATUS_FAIL);
1479 }
1480
1481 if (val & INT_REG_CED) {
1482 if (val & INT_REG_ERR) {
1483 if (!(val & INT_REG_BREQ)) {
1484 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1485 TRACE_RET(chip, STATUS_FAIL);
1486 }
1487 retval = ms_read_status_reg(chip);
1488 if (retval != STATUS_SUCCESS)
1489 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1490 } else {
1491 if (!(val & INT_REG_BREQ)) {
1492 ms_set_err_code(chip, MS_BREQ_ERROR);
1493 TRACE_RET(chip, STATUS_FAIL);
1494 }
1495 }
1496 }
1497
1498 retval =
1499 ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0,
1500 NO_WAIT_INT);
1501 if (retval != STATUS_SUCCESS)
1502 TRACE_RET(chip, retval);
1503 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))
1504 TRACE_RET(chip, STATUS_FAIL);
1505
1506 return STATUS_SUCCESS;
1507 }
1508
1509 static int ms_set_bad_block(struct rts51x_chip *chip, u16 phy_blk)
1510 {
1511 struct ms_info *ms_card = &(chip->ms_card);
1512 int retval;
1513 u8 val = 0, data[8], extra[MS_EXTRA_SIZE];
1514
1515 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1516 if (retval != STATUS_SUCCESS)
1517 TRACE_RET(chip, retval);
1518
1519 ms_set_err_code(chip, MS_NO_ERROR);
1520
1521 if (CHK_MS4BIT(ms_card)) {
1522 /* Parallel interface */
1523 data[0] = 0x88;
1524 } else {
1525 /* Serial interface */
1526 data[0] = 0x80;
1527 }
1528 /* Block Address */
1529 data[1] = 0;
1530 data[2] = (u8) (phy_blk >> 8);
1531 data[3] = (u8) phy_blk;
1532 data[4] = 0x80;
1533 data[5] = 0;
1534 data[6] = extra[0] & 0x7F;
1535 data[7] = 0xFF;
1536
1537 #ifdef MS_SPEEDUP
1538 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7,
1539 BLOCK_WRITE, WAIT_INT, data, 7, &val);
1540 #else
1541 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7,
1542 BLOCK_WRITE, WAIT_INT, data, 7, &val);
1543 #endif
1544 if (retval != STATUS_SUCCESS)
1545 TRACE_RET(chip, retval);
1546
1547 if (val & INT_REG_CMDNK) {
1548 ms_set_err_code(chip, MS_CMD_NK);
1549 TRACE_RET(chip, STATUS_FAIL);
1550 }
1551
1552 if (val & INT_REG_CED) {
1553 if (val & INT_REG_ERR) {
1554 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1555 TRACE_RET(chip, STATUS_FAIL);
1556 }
1557 }
1558
1559 return STATUS_SUCCESS;
1560 }
1561
1562 static int ms_erase_block(struct rts51x_chip *chip, u16 phy_blk)
1563 {
1564 struct ms_info *ms_card = &(chip->ms_card);
1565 int retval, i = 0;
1566 u8 val = 0, data[6];
1567
1568 retval =
1569 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
1570 6);
1571 if (retval != STATUS_SUCCESS)
1572 TRACE_RET(chip, retval);
1573
1574 ms_set_err_code(chip, MS_NO_ERROR);
1575
1576 if (CHK_MS4BIT(ms_card)) {
1577 /* Parallel interface */
1578 data[0] = 0x88;
1579 } else {
1580 /* Serial interface */
1581 data[0] = 0x80;
1582 }
1583 /* Block Address */
1584 data[1] = 0;
1585 data[2] = (u8) (phy_blk >> 8);
1586 data[3] = (u8) phy_blk;
1587 data[4] = 0;
1588 data[5] = 0;
1589
1590 ERASE_RTY:
1591 #ifdef MS_SPEEDUP
1592 retval =
1593 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1594 BLOCK_ERASE, WAIT_INT, data, 6, &val);
1595 #else
1596 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1597 BLOCK_ERASE, WAIT_INT, data, 6, &val);
1598 #endif
1599
1600 if (val & INT_REG_CMDNK) {
1601 if (i < 3) {
1602 i++;
1603 goto ERASE_RTY;
1604 }
1605 ms_set_err_code(chip, MS_CMD_NK);
1606 ms_set_bad_block(chip, phy_blk);
1607 TRACE_RET(chip, STATUS_FAIL);
1608 }
1609
1610 if (val & INT_REG_CED) {
1611 if (val & INT_REG_ERR) {
1612 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1613 TRACE_RET(chip, STATUS_FAIL);
1614 }
1615 }
1616
1617 return STATUS_SUCCESS;
1618 }
1619
1620 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1621 {
1622 if (!extra || (extra_len < MS_EXTRA_SIZE))
1623 return;
1624
1625 memset(extra, 0xFF, MS_EXTRA_SIZE);
1626
1627 if (type == setPS_NG)
1628 extra[0] = 0xB8;
1629 else
1630 extra[0] = 0x98;
1631
1632 extra[2] = (u8) (log_blk >> 8);
1633 extra[3] = (u8) log_blk;
1634 }
1635
1636 static int ms_init_page(struct rts51x_chip *chip, u16 phy_blk, u16 log_blk,
1637 u8 start_page, u8 end_page)
1638 {
1639 int retval;
1640 u8 extra[MS_EXTRA_SIZE], i;
1641
1642 memset(extra, 0xff, MS_EXTRA_SIZE);
1643
1644 extra[0] = 0xf8; /* Block, page OK, data erased */
1645 extra[1] = 0xff;
1646 extra[2] = (u8) (log_blk >> 8);
1647 extra[3] = (u8) log_blk;
1648
1649 for (i = start_page; i < end_page; i++) {
1650 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
1651 TRACE_RET(chip, STATUS_FAIL);
1652
1653 retval =
1654 ms_write_extra_data(chip, phy_blk, i, extra, MS_EXTRA_SIZE);
1655 if (retval != STATUS_SUCCESS)
1656 TRACE_RET(chip, retval);
1657 }
1658
1659 return STATUS_SUCCESS;
1660 }
1661
1662 static int ms_copy_page(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
1663 u16 log_blk, u8 start_page, u8 end_page)
1664 {
1665 struct ms_info *ms_card = &(chip->ms_card);
1666 int retval, rty_cnt, uncorrect_flag = 0;
1667 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1668
1669 RTS51X_DEBUGP("Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1670 old_blk, new_blk, log_blk);
1671 RTS51X_DEBUGP("start_page = %d, end_page = %d\n", start_page,
1672 end_page);
1673
1674 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1675 if (retval != STATUS_SUCCESS)
1676 TRACE_RET(chip, retval);
1677
1678 retval = ms_read_status_reg(chip);
1679 if (retval != STATUS_SUCCESS)
1680 TRACE_RET(chip, retval);
1681
1682 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
1683
1684 if (val & BUF_FULL) {
1685 /* Clear Buffer */
1686 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1687 if (retval != STATUS_SUCCESS)
1688 TRACE_RET(chip, retval);
1689 /* GET_INT Register */
1690 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1691 if (retval != STATUS_SUCCESS)
1692 TRACE_RET(chip, retval);
1693
1694 if (!(val & INT_REG_CED)) {
1695 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1696 TRACE_RET(chip, STATUS_FAIL);
1697 }
1698 }
1699
1700 for (i = start_page; i < end_page; i++) {
1701 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
1702 TRACE_RET(chip, STATUS_FAIL);
1703
1704 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1705
1706 retval =
1707 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1708 SystemParm, 6);
1709 if (retval != STATUS_SUCCESS)
1710 TRACE_RET(chip, retval);
1711 /* Write REG */
1712 ms_set_err_code(chip, MS_NO_ERROR);
1713
1714 if (CHK_MS4BIT(ms_card)) {
1715 /* Parallel interface */
1716 data[0] = 0x88;
1717 } else {
1718 /* Serial interface */
1719 data[0] = 0x80;
1720 }
1721 /* Block Address */
1722 data[1] = 0;
1723 data[2] = (u8) (old_blk >> 8);
1724 data[3] = (u8) old_blk;
1725 data[4] = 0x20;
1726 data[5] = i;
1727
1728 retval =
1729 ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1730 if (retval != STATUS_SUCCESS)
1731 TRACE_RET(chip, retval);
1732
1733 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1734 if (retval != STATUS_SUCCESS)
1735 TRACE_RET(chip, retval);
1736
1737 ms_set_err_code(chip, MS_NO_ERROR);
1738 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1739 if (retval != STATUS_SUCCESS)
1740 TRACE_RET(chip, retval);
1741
1742 if (val & INT_REG_CMDNK) {
1743 ms_set_err_code(chip, MS_CMD_NK);
1744 TRACE_RET(chip, STATUS_FAIL);
1745 }
1746
1747 if (val & INT_REG_CED) {
1748 if (val & INT_REG_ERR) {
1749 retval = ms_read_status_reg(chip);
1750 if (retval != STATUS_SUCCESS) {
1751 uncorrect_flag = 1;
1752 RTS51X_DEBUGP("Uncorrectable error\n");
1753 } else {
1754 uncorrect_flag = 0;
1755 }
1756
1757 retval =
1758 ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
1759 READ_PAGE_DATA, 0, NO_WAIT_INT);
1760 if (retval != STATUS_SUCCESS)
1761 TRACE_RET(chip, retval);
1762 if (uncorrect_flag) {
1763 ms_set_page_status(log_blk, setPS_NG,
1764 extra, MS_EXTRA_SIZE);
1765 if (i == 0)
1766 extra[0] &= 0xEF;
1767 ms_write_extra_data(chip, old_blk, i,
1768 extra,
1769 MS_EXTRA_SIZE);
1770 RTS51X_DEBUGP("page %d : extra[0] = 0x%x\n",
1771 i, extra[0]);
1772 MS_SET_BAD_BLOCK_FLG(ms_card);
1773
1774 ms_set_page_status(log_blk, setPS_Error,
1775 extra, MS_EXTRA_SIZE);
1776 ms_write_extra_data(chip, new_blk, i,
1777 extra, MS_EXTRA_SIZE);
1778 continue;
1779 }
1780
1781 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
1782 rty_cnt++) {
1783 retval =
1784 ms_transfer_tpc(chip,
1785 MS_TM_NORMAL_WRITE,
1786 WRITE_PAGE_DATA, 0,
1787 NO_WAIT_INT);
1788 if (retval == STATUS_SUCCESS)
1789 break;
1790 }
1791 if (rty_cnt == MS_MAX_RETRY_COUNT)
1792 TRACE_RET(chip, STATUS_FAIL);
1793 }
1794
1795 if (!(val & INT_REG_BREQ)) {
1796 ms_set_err_code(chip, MS_BREQ_ERROR);
1797 TRACE_RET(chip, STATUS_FAIL);
1798 }
1799 }
1800
1801 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1802 MS_EXTRA_SIZE, SystemParm,
1803 (6 + MS_EXTRA_SIZE));
1804
1805 /* Write REG */
1806 ms_set_err_code(chip, MS_NO_ERROR);
1807
1808 if (CHK_MS4BIT(ms_card)) {
1809 /* Parallel interface */
1810 data[0] = 0x88;
1811 } else {
1812 /* Serial interface */
1813 data[0] = 0x80;
1814 }
1815 /* Block Address */
1816 data[1] = 0;
1817 data[2] = (u8) (new_blk >> 8);
1818 data[3] = (u8) new_blk;
1819 data[4] = 0x20;
1820 data[5] = i;
1821
1822 /* for MS check procedure */
1823 if ((extra[0] & 0x60) != 0x60)
1824 data[6] = extra[0];
1825 else
1826 data[6] = 0xF8;
1827
1828 data[6 + 1] = 0xFF;
1829 data[6 + 2] = (u8) (log_blk >> 8);
1830 data[6 + 3] = (u8) log_blk;
1831
1832 for (j = 4; j <= MS_EXTRA_SIZE; j++)
1833 data[6 + j] = 0xFF;
1834
1835 retval =
1836 ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1837 NO_WAIT_INT, data, 16);
1838 if (retval != STATUS_SUCCESS)
1839 TRACE_RET(chip, retval);
1840
1841 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1842 if (retval != STATUS_SUCCESS)
1843 TRACE_RET(chip, retval);
1844 /* GET_INT Register */
1845 ms_set_err_code(chip, MS_NO_ERROR);
1846 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1847 if (retval != STATUS_SUCCESS)
1848 TRACE_RET(chip, retval);
1849
1850 if (val & INT_REG_CMDNK) {
1851 ms_set_err_code(chip, MS_CMD_NK);
1852 TRACE_RET(chip, STATUS_FAIL);
1853 }
1854
1855 if (val & INT_REG_CED) {
1856 if (val & INT_REG_ERR) {
1857 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1858 TRACE_RET(chip, STATUS_FAIL);
1859 }
1860 }
1861
1862 if (i == 0) {
1863 retval =
1864 ms_set_rw_reg_addr(chip, OverwriteFlag,
1865 MS_EXTRA_SIZE, SystemParm, 7);
1866 if (retval != STATUS_SUCCESS)
1867 TRACE_RET(chip, retval);
1868
1869 ms_set_err_code(chip, MS_NO_ERROR);
1870
1871 if (CHK_MS4BIT(ms_card)) {
1872 /* Parallel interface */
1873 data[0] = 0x88;
1874 } else {
1875 /* Serial interface */
1876 data[0] = 0x80;
1877 }
1878 /* Block Address */
1879 data[1] = 0;
1880 data[2] = (u8) (old_blk >> 8);
1881 data[3] = (u8) old_blk;
1882 data[4] = 0x80;
1883 data[5] = 0;
1884 data[6] = 0xEF;
1885 data[7] = 0xFF;
1886
1887 retval =
1888 ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
1889 data, 8);
1890 if (retval != STATUS_SUCCESS)
1891 TRACE_RET(chip, retval);
1892
1893 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1894 if (retval != STATUS_SUCCESS)
1895 TRACE_RET(chip, retval);
1896
1897 ms_set_err_code(chip, MS_NO_ERROR);
1898 retval =
1899 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
1900 1);
1901 if (retval != STATUS_SUCCESS)
1902 TRACE_RET(chip, retval);
1903
1904 if (val & INT_REG_CMDNK) {
1905 ms_set_err_code(chip, MS_CMD_NK);
1906 TRACE_RET(chip, STATUS_FAIL);
1907 }
1908
1909 if (val & INT_REG_CED) {
1910 if (val & INT_REG_ERR) {
1911 ms_set_err_code(chip,
1912 MS_FLASH_WRITE_ERROR);
1913 TRACE_RET(chip, STATUS_FAIL);
1914 }
1915 }
1916 }
1917 }
1918
1919 return STATUS_SUCCESS;
1920 }
1921
1922 #ifdef MS_SPEEDUP
1923 static int ms_auto_copy_page(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
1924 u16 log_blk, u8 start_page, u8 end_page)
1925 {
1926 struct ms_info *ms_card = &(chip->ms_card);
1927 int retval;
1928 u8 page_len, bus_width, val = 0;
1929 u8 extra[MS_EXTRA_SIZE];
1930
1931 RTS51X_DEBUGP("Auto copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1932 old_blk, new_blk, log_blk);
1933 RTS51X_DEBUGP("start_page = %d, end_page = %d\n", start_page,
1934 end_page);
1935
1936 page_len = end_page - start_page;
1937
1938 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1939 if (retval != STATUS_SUCCESS)
1940 TRACE_RET(chip, retval);
1941
1942 retval = ms_read_status_reg(chip);
1943 if (retval != STATUS_SUCCESS)
1944 TRACE_RET(chip, retval);
1945
1946 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
1947
1948 if (val & BUF_FULL) {
1949 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1950 if (retval != STATUS_SUCCESS)
1951 TRACE_RET(chip, retval);
1952
1953 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1954 if (retval != STATUS_SUCCESS)
1955 TRACE_RET(chip, retval);
1956
1957 if (!(val & INT_REG_CED)) {
1958 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1959 TRACE_RET(chip, STATUS_FAIL);
1960 }
1961 }
1962
1963 if (CHK_MS4BIT(ms_card)) {
1964 /* Parallel interface */
1965 bus_width = 0x88;
1966 } else {
1967 /* Serial interface */
1968 bus_width = 0x80;
1969 }
1970
1971 rts51x_init_cmd(chip);
1972
1973 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_OLD_BLOCK_0, 0xFF, (u8) old_blk);
1974 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_OLD_BLOCK_1, 0xFF,
1975 (u8) (old_blk >> 8));
1976 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_NEW_BLOCK_0, 0xFF, (u8) new_blk);
1977 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_NEW_BLOCK_1, 0xFF,
1978 (u8) (new_blk >> 8));
1979 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_LOG_BLOCK_0, 0xFF, (u8) log_blk);
1980 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_LOG_BLOCK_1, 0xFF,
1981 (u8) (log_blk >> 8));
1982 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_PAGE_START, 0xFF, start_page);
1983 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_PAGE_LENGTH, 0xFF, page_len);
1984 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BUS_WIDTH, 0xFF, bus_width);
1985
1986 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
1987 MS_TRANSFER_START | MS_TM_COPY_PAGE);
1988 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
1989 MS_TRANSFER_END);
1990
1991 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1992 if (retval != STATUS_SUCCESS) {
1993 rts51x_clear_ms_error(chip);
1994 TRACE_RET(chip, retval);
1995 }
1996
1997 retval = rts51x_get_rsp(chip, 1, 5000);
1998
1999 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
2000 rts51x_clear_ms_error(chip);
2001 if (retval == STATUS_TIMEDOUT)
2002 TRACE_RET(chip, retval);
2003 TRACE_GOTO(chip, Fail);
2004 }
2005
2006 return STATUS_SUCCESS;
2007
2008 Fail:
2009 retval = ms_erase_block(chip, new_blk);
2010 if (retval != STATUS_SUCCESS)
2011 TRACE_RET(chip, retval);
2012
2013 retval =
2014 ms_copy_page(chip, old_blk, new_blk, log_blk, start_page, end_page);
2015 if (retval != STATUS_SUCCESS)
2016 TRACE_RET(chip, retval);
2017
2018 return STATUS_SUCCESS;
2019 }
2020 #endif
2021
2022 static int reset_ms(struct rts51x_chip *chip)
2023 {
2024 struct ms_info *ms_card = &(chip->ms_card);
2025 int retval;
2026 u16 i, reg_addr, block_size;
2027 u8 val, j, *ptr;
2028 #ifndef SUPPORT_MAGIC_GATE
2029 u16 eblock_cnt;
2030 #endif
2031
2032 retval = ms_prepare_reset(chip);
2033 if (retval != STATUS_SUCCESS)
2034 TRACE_RET(chip, retval);
2035
2036 ms_card->ms_type |= TYPE_MS;
2037
2038 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
2039 if (retval != STATUS_SUCCESS)
2040 TRACE_RET(chip, retval);
2041
2042 retval = ms_read_status_reg(chip);
2043 if (retval != STATUS_SUCCESS)
2044 TRACE_RET(chip, retval);
2045
2046 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
2047 if (val & WRT_PRTCT)
2048 chip->card_wp |= MS_CARD;
2049 else
2050 chip->card_wp &= ~MS_CARD;
2051
2052 i = 0;
2053
2054 RE_SEARCH:
2055 /* Search For Boot Block */
2056 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
2057 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
2058 TRACE_RET(chip, STATUS_FAIL);
2059
2060 retval = ms_check_boot_block(chip, i);
2061 if (retval != STATUS_SUCCESS) {
2062 i++;
2063 continue;
2064 }
2065
2066 ms_card->boot_block = i;
2067 break;
2068 }
2069
2070 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
2071 RTS51X_DEBUGP("No boot block found!");
2072 TRACE_RET(chip, STATUS_FAIL);
2073 }
2074 for (j = 0; j < 3; j++) {
2075 retval = ms_read_page(chip, ms_card->boot_block, j);
2076 if (retval != STATUS_SUCCESS) {
2077 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
2078 i = ms_card->boot_block + 1;
2079 ms_set_err_code(chip, MS_NO_ERROR);
2080 goto RE_SEARCH;
2081 }
2082 }
2083 }
2084
2085 /* Read boot block contents */
2086 retval = ms_read_page(chip, ms_card->boot_block, 0);
2087 if (retval != STATUS_SUCCESS)
2088 TRACE_RET(chip, retval);
2089 /* Read MS system information as sys_info */
2090 retval =
2091 rts51x_seq_read_register(chip, PPBUF_BASE2 + 0x1A0, 96,
2092 ms_card->raw_sys_info);
2093 if (retval != STATUS_SUCCESS)
2094 TRACE_RET(chip, retval);
2095 /* Read useful block contents */
2096 rts51x_init_cmd(chip);
2097
2098 rts51x_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
2099 rts51x_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
2100
2101 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
2102 reg_addr++) {
2103 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2104 }
2105
2106 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
2107 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2108
2109 rts51x_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
2110 rts51x_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
2111
2112 retval = rts51x_send_cmd(chip, MODE_CR, 100);
2113 if (retval != STATUS_SUCCESS)
2114 TRACE_RET(chip, retval);
2115
2116 retval = rts51x_get_rsp(chip, 16, 100);
2117
2118 if (retval != STATUS_SUCCESS)
2119 TRACE_RET(chip, retval);
2120
2121 ptr = rts51x_get_rsp_data(chip);
2122
2123 RTS51X_DEBUGP("Boot block data:\n");
2124 RTS51X_DUMP(ptr, 16);
2125
2126 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
2127 i = ms_card->boot_block + 1;
2128 goto RE_SEARCH;
2129 }
2130 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
2131 i = ms_card->boot_block + 1;
2132 goto RE_SEARCH;
2133 }
2134 if ((ptr[14] == 1) || (ptr[14] == 3))
2135 chip->card_wp |= MS_CARD;
2136 block_size = ((u16) ptr[6] << 8) | ptr[7];
2137 if (block_size == 0x0010) {
2138 ms_card->block_shift = 5;
2139 ms_card->page_off = 0x1F;
2140 } else if (block_size == 0x0008) {
2141 ms_card->block_shift = 4;
2142 ms_card->page_off = 0x0F;
2143 }
2144 ms_card->total_block = ((u16) ptr[8] << 8) | ptr[9];
2145
2146 #ifdef SUPPORT_MAGIC_GATE
2147 j = ptr[10];
2148
2149 if (ms_card->block_shift == 4) {
2150 if (j < 2)
2151 ms_card->capacity = 0x1EE0;
2152 else
2153 ms_card->capacity = 0x3DE0;
2154 } else {
2155 if (j < 5)
2156 ms_card->capacity = 0x7BC0;
2157 else if (j < 0xA)
2158 ms_card->capacity = 0xF7C0;
2159 else if (j < 0x11)
2160 ms_card->capacity = 0x1EF80;
2161 else
2162 ms_card->capacity = 0x3DF00;
2163 }
2164 #else
2165 eblock_cnt = ((u16) ptr[10] << 8) | ptr[11];
2166
2167 ms_card->capacity = ((u32) eblock_cnt - 2) << ms_card->block_shift;
2168 #endif
2169
2170 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
2171
2172 if (ptr[15]) {
2173 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
2174 if (retval != STATUS_SUCCESS)
2175 TRACE_RET(chip, STATUS_FAIL);
2176 RTS51X_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
2177 RTS51X_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
2178
2179 retval =
2180 ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,
2181 NO_WAIT_INT);
2182 if (retval != STATUS_SUCCESS)
2183 TRACE_RET(chip, STATUS_FAIL);
2184 RTS51X_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
2185 MS_BUS_WIDTH_4 | PUSH_TIME_ODD |
2186 MS_NO_CHECK_INT);
2187
2188 ms_card->ms_type |= MS_4BIT;
2189 }
2190
2191 if (CHK_MS4BIT(ms_card))
2192 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2193 else
2194 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2195
2196 return STATUS_SUCCESS;
2197 }
2198
2199 static int ms_init_l2p_tbl(struct rts51x_chip *chip)
2200 {
2201 struct ms_info *ms_card = &(chip->ms_card);
2202 int size, i, seg_no, retval;
2203 u16 defect_block, reg_addr;
2204 u8 val1, val2;
2205
2206 ms_card->segment_cnt = ms_card->total_block >> 9;
2207 RTS51X_DEBUGP("ms_card->segment_cnt = %d\n", ms_card->segment_cnt);
2208
2209 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2210 ms_card->segment = vmalloc(size);
2211 if (ms_card->segment == NULL)
2212 TRACE_RET(chip, STATUS_FAIL);
2213 memset(ms_card->segment, 0, size);
2214
2215 retval = ms_read_page(chip, ms_card->boot_block, 1);
2216 if (retval != STATUS_SUCCESS)
2217 TRACE_GOTO(chip, INIT_FAIL);
2218
2219 reg_addr = PPBUF_BASE2;
2220 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2221 retval = rts51x_read_register(chip, reg_addr++, &val1);
2222 if (retval != STATUS_SUCCESS)
2223 TRACE_GOTO(chip, INIT_FAIL);
2224 retval = rts51x_read_register(chip, reg_addr++, &val2);
2225 if (retval != STATUS_SUCCESS)
2226 TRACE_GOTO(chip, INIT_FAIL);
2227
2228 defect_block = ((u16) val1 << 8) | val2;
2229 if (defect_block == 0xFFFF)
2230 break;
2231 seg_no = defect_block / 512;
2232 ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].
2233 disable_count++] =
2234 defect_block;
2235 }
2236
2237 for (i = 0; i < ms_card->segment_cnt; i++) {
2238 ms_card->segment[i].build_flag = 0;
2239 ms_card->segment[i].l2p_table = NULL;
2240 ms_card->segment[i].free_table = NULL;
2241 ms_card->segment[i].get_index = 0;
2242 ms_card->segment[i].set_index = 0;
2243 ms_card->segment[i].unused_blk_cnt = 0;
2244
2245 RTS51X_DEBUGP("defective block count of segment %d is %d\n",
2246 i, ms_card->segment[i].disable_count);
2247 }
2248
2249 return STATUS_SUCCESS;
2250
2251 INIT_FAIL:
2252 if (ms_card->segment) {
2253 vfree(ms_card->segment);
2254 ms_card->segment = NULL;
2255 }
2256
2257 return STATUS_FAIL;
2258 }
2259
2260 static u16 ms_get_l2p_tbl(struct rts51x_chip *chip, int seg_no, u16 log_off)
2261 {
2262 struct ms_info *ms_card = &(chip->ms_card);
2263 struct zone_entry *segment;
2264
2265 if (ms_card->segment == NULL)
2266 return 0xFFFF;
2267
2268 segment = &(ms_card->segment[seg_no]);
2269
2270 if (segment->l2p_table)
2271 return segment->l2p_table[log_off];
2272
2273 return 0xFFFF;
2274 }
2275
2276 static void ms_set_l2p_tbl(struct rts51x_chip *chip, int seg_no, u16 log_off,
2277 u16 phy_blk)
2278 {
2279 struct ms_info *ms_card = &(chip->ms_card);
2280 struct zone_entry *segment;
2281
2282 if (ms_card->segment == NULL)
2283 return;
2284
2285 segment = &(ms_card->segment[seg_no]);
2286 if (segment->l2p_table)
2287 segment->l2p_table[log_off] = phy_blk;
2288 }
2289
2290 static void ms_set_unused_block(struct rts51x_chip *chip, u16 phy_blk)
2291 {
2292 struct ms_info *ms_card = &(chip->ms_card);
2293 struct zone_entry *segment;
2294 int seg_no;
2295
2296 seg_no = (int)phy_blk >> 9;
2297 segment = &(ms_card->segment[seg_no]);
2298
2299 segment->free_table[segment->set_index++] = phy_blk;
2300 if (segment->set_index >= MS_FREE_TABLE_CNT)
2301 segment->set_index = 0;
2302 segment->unused_blk_cnt++;
2303 }
2304
2305 static u16 ms_get_unused_block(struct rts51x_chip *chip, int seg_no)
2306 {
2307 struct ms_info *ms_card = &(chip->ms_card);
2308 struct zone_entry *segment;
2309 u16 phy_blk;
2310
2311 segment = &(ms_card->segment[seg_no]);
2312
2313 if (segment->unused_blk_cnt <= 0)
2314 return 0xFFFF;
2315
2316 phy_blk = segment->free_table[segment->get_index];
2317 segment->free_table[segment->get_index++] = 0xFFFF;
2318 if (segment->get_index >= MS_FREE_TABLE_CNT)
2319 segment->get_index = 0;
2320 segment->unused_blk_cnt--;
2321
2322 return phy_blk;
2323 }
2324
2325 static const unsigned short ms_start_idx[] = {
2326 0, 494, 990, 1486, 1982, 2478, 2974, 3470,
2327 3966, 4462, 4958, 5454, 5950, 6446, 6942, 7438, 7934
2328 };
2329
2330 static int ms_arbitrate_l2p(struct rts51x_chip *chip, u16 phy_blk, u16 log_off,
2331 u8 us1, u8 us2)
2332 {
2333 struct ms_info *ms_card = &(chip->ms_card);
2334 struct zone_entry *segment;
2335 int seg_no;
2336 u16 tmp_blk;
2337
2338 seg_no = (int)phy_blk >> 9;
2339 segment = &(ms_card->segment[seg_no]);
2340 tmp_blk = segment->l2p_table[log_off];
2341
2342 if (us1 != us2) {
2343 if (us1 == 0) {
2344 if (!(chip->card_wp & MS_CARD))
2345 ms_erase_block(chip, tmp_blk);
2346 ms_set_unused_block(chip, tmp_blk);
2347 segment->l2p_table[log_off] = phy_blk;
2348 } else {
2349 if (!(chip->card_wp & MS_CARD))
2350 ms_erase_block(chip, phy_blk);
2351 ms_set_unused_block(chip, phy_blk);
2352 }
2353 } else {
2354 if (phy_blk < tmp_blk) {
2355 if (!(chip->card_wp & MS_CARD))
2356 ms_erase_block(chip, phy_blk);
2357 ms_set_unused_block(chip, phy_blk);
2358 } else {
2359 if (!(chip->card_wp & MS_CARD))
2360 ms_erase_block(chip, tmp_blk);
2361 ms_set_unused_block(chip, tmp_blk);
2362 segment->l2p_table[log_off] = phy_blk;
2363 }
2364 }
2365
2366 return STATUS_SUCCESS;
2367 }
2368
2369 static int ms_build_l2p_tbl(struct rts51x_chip *chip, int seg_no)
2370 {
2371 struct ms_info *ms_card = &(chip->ms_card);
2372 struct zone_entry *segment;
2373 int retval, table_size, disable_cnt, defect_flag, i;
2374 u16 start, end, phy_blk, log_blk, tmp_blk;
2375 u8 extra[MS_EXTRA_SIZE], us1, us2;
2376
2377 RTS51X_DEBUGP("ms_build_l2p_tbl: %d\n", seg_no);
2378
2379 if (ms_card->segment == NULL) {
2380 retval = ms_init_l2p_tbl(chip);
2381 if (retval != STATUS_SUCCESS)
2382 TRACE_RET(chip, retval);
2383 }
2384
2385 if (ms_card->segment[seg_no].build_flag) {
2386 RTS51X_DEBUGP("l2p table of segment %d has been built\n",
2387 seg_no);
2388 return STATUS_SUCCESS;
2389 }
2390
2391 if (seg_no == 0)
2392 table_size = 494;
2393 else
2394 table_size = 496;
2395
2396 segment = &(ms_card->segment[seg_no]);
2397
2398 if (segment->l2p_table == NULL) {
2399 segment->l2p_table = vmalloc(table_size * 2);
2400 if (segment->l2p_table == NULL)
2401 TRACE_GOTO(chip, BUILD_FAIL);
2402 }
2403 memset((u8 *) (segment->l2p_table), 0xff, table_size * 2);
2404
2405 if (segment->free_table == NULL) {
2406 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2407 if (segment->free_table == NULL)
2408 TRACE_GOTO(chip, BUILD_FAIL);
2409 }
2410 memset((u8 *) (segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2411
2412 start = (u16) seg_no << 9;
2413 end = (u16) (seg_no + 1) << 9;
2414
2415 disable_cnt = segment->disable_count;
2416
2417 segment->get_index = segment->set_index = 0;
2418 segment->unused_blk_cnt = 0;
2419
2420 for (phy_blk = start; phy_blk < end; phy_blk++) {
2421 if (disable_cnt) {
2422 defect_flag = 0;
2423 for (i = 0; i < segment->disable_count; i++) {
2424 if (phy_blk == segment->defect_list[i]) {
2425 defect_flag = 1;
2426 break;
2427 }
2428 }
2429 if (defect_flag) {
2430 disable_cnt--;
2431 continue;
2432 }
2433 }
2434
2435 retval =
2436 ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
2437 if (retval != STATUS_SUCCESS) {
2438 RTS51X_DEBUGP("read extra data fail\n");
2439 ms_set_bad_block(chip, phy_blk);
2440 continue;
2441 }
2442
2443 if (seg_no == ms_card->segment_cnt - 1) {
2444 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2445 if (!(chip->card_wp & MS_CARD)) {
2446 retval = ms_erase_block(chip, phy_blk);
2447 if (retval != STATUS_SUCCESS)
2448 continue;
2449 extra[2] = 0xff;
2450 extra[3] = 0xff;
2451 }
2452 }
2453 }
2454
2455 if (!(extra[0] & BLOCK_OK))
2456 continue;
2457 if (!(extra[1] & NOT_BOOT_BLOCK))
2458 continue;
2459 if ((extra[0] & PAGE_OK) != PAGE_OK)
2460 continue;
2461
2462 log_blk = ((u16) extra[2] << 8) | extra[3];
2463
2464 if (log_blk == 0xFFFF) {
2465 if (!(chip->card_wp & MS_CARD)) {
2466 retval = ms_erase_block(chip, phy_blk);
2467 if (retval != STATUS_SUCCESS)
2468 continue;
2469 }
2470 ms_set_unused_block(chip, phy_blk);
2471 continue;
2472 }
2473
2474 if ((log_blk < ms_start_idx[seg_no]) ||
2475 (log_blk >= ms_start_idx[seg_no + 1])) {
2476 if (!(chip->card_wp & MS_CARD)) {
2477 retval = ms_erase_block(chip, phy_blk);
2478 if (retval != STATUS_SUCCESS)
2479 continue;
2480 }
2481 ms_set_unused_block(chip, phy_blk);
2482 continue;
2483 }
2484
2485 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] ==
2486 0xFFFF) {
2487 segment->l2p_table[log_blk - ms_start_idx[seg_no]] =
2488 phy_blk;
2489 continue;
2490 }
2491
2492 us1 = extra[0] & 0x10;
2493 tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
2494 retval =
2495 ms_read_extra_data(chip, tmp_blk, 0, extra, MS_EXTRA_SIZE);
2496 if (retval != STATUS_SUCCESS)
2497 continue;
2498 us2 = extra[0] & 0x10;
2499
2500 (void)ms_arbitrate_l2p(chip, phy_blk,
2501 log_blk - ms_start_idx[seg_no], us1,
2502 us2);
2503 continue;
2504 }
2505
2506 segment->build_flag = 1;
2507
2508 RTS51X_DEBUGP("unused block count: %d\n", segment->unused_blk_cnt);
2509
2510 if (seg_no == ms_card->segment_cnt - 1) {
2511 if (segment->unused_blk_cnt < 2)
2512 chip->card_wp |= MS_CARD;
2513 } else {
2514 if (segment->unused_blk_cnt < 1)
2515 chip->card_wp |= MS_CARD;
2516 }
2517
2518 if (chip->card_wp & MS_CARD)
2519 return STATUS_SUCCESS;
2520
2521 for (log_blk = ms_start_idx[seg_no]; log_blk < ms_start_idx[seg_no + 1];
2522 log_blk++) {
2523 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] ==
2524 0xFFFF) {
2525 phy_blk = ms_get_unused_block(chip, seg_no);
2526 if (phy_blk == 0xFFFF) {
2527 chip->card_wp |= MS_CARD;
2528 return STATUS_SUCCESS;
2529 }
2530 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2531 if (retval != STATUS_SUCCESS)
2532 TRACE_GOTO(chip, BUILD_FAIL);
2533 segment->l2p_table[log_blk - ms_start_idx[seg_no]] =
2534 phy_blk;
2535 if (seg_no == ms_card->segment_cnt - 1) {
2536 if (segment->unused_blk_cnt < 2) {
2537 chip->card_wp |= MS_CARD;
2538 return STATUS_SUCCESS;
2539 }
2540 } else {
2541 if (segment->unused_blk_cnt < 1) {
2542 chip->card_wp |= MS_CARD;
2543 return STATUS_SUCCESS;
2544 }
2545 }
2546 }
2547 }
2548
2549 if (seg_no == 0) {
2550 for (log_blk = 0; log_blk < 494; log_blk++) {
2551 tmp_blk = segment->l2p_table[log_blk];
2552 if (tmp_blk < ms_card->boot_block) {
2553 RTS51X_DEBUGP("Boot block is not the first normal block.\n");
2554
2555 if (chip->card_wp & MS_CARD)
2556 break;
2557
2558 phy_blk = ms_get_unused_block(chip, 0);
2559 #ifdef MS_SPEEDUP
2560 retval =
2561 ms_auto_copy_page(chip, tmp_blk, phy_blk,
2562 log_blk, 0,
2563 ms_card->page_off + 1);
2564 #else
2565 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2566 log_blk, 0,
2567 ms_card->page_off + 1);
2568 #endif
2569 if (retval != STATUS_SUCCESS)
2570 TRACE_RET(chip, retval);
2571
2572 segment->l2p_table[log_blk] = phy_blk;
2573
2574 retval = ms_set_bad_block(chip, tmp_blk);
2575 if (retval != STATUS_SUCCESS)
2576 TRACE_RET(chip, retval);
2577 }
2578 }
2579 }
2580
2581 return STATUS_SUCCESS;
2582
2583 BUILD_FAIL:
2584 segment->build_flag = 0;
2585 if (segment->l2p_table) {
2586 vfree(segment->l2p_table);
2587 segment->l2p_table = NULL;
2588 }
2589 if (segment->free_table) {
2590 vfree(segment->free_table);
2591 segment->free_table = NULL;
2592 }
2593
2594 return STATUS_FAIL;
2595 }
2596
2597 int rts51x_reset_ms_card(struct rts51x_chip *chip)
2598 {
2599 struct ms_info *ms_card = &(chip->ms_card);
2600 int retval;
2601
2602 memset(ms_card, 0, sizeof(struct ms_info));
2603
2604 rts51x_enable_card_clock(chip, MS_CARD);
2605
2606 retval = rts51x_select_card(chip, MS_CARD);
2607 if (retval != STATUS_SUCCESS)
2608 TRACE_RET(chip, retval);
2609
2610 ms_card->ms_type = 0;
2611 ms_card->last_rw_int = 0;
2612
2613 retval = reset_ms_pro(chip);
2614 if (retval != STATUS_SUCCESS) {
2615 if (ms_card->check_ms_flow) {
2616 retval = reset_ms(chip);
2617 if (retval != STATUS_SUCCESS) {
2618 if (chip->option.reset_or_rw_fail_set_pad_drive) {
2619 rts51x_write_register(chip,
2620 CARD_DRIVE_SEL, SD20_DRIVE_MASK,
2621 DRIVE_8mA);
2622 }
2623 TRACE_RET(chip, retval);
2624 }
2625 } else {
2626 if (chip->option.reset_or_rw_fail_set_pad_drive) {
2627 rts51x_write_register(chip, CARD_DRIVE_SEL,
2628 SD20_DRIVE_MASK,
2629 DRIVE_8mA);
2630 }
2631 TRACE_RET(chip, retval);
2632 }
2633 }
2634
2635 retval = ms_set_init_para(chip);
2636 if (retval != STATUS_SUCCESS)
2637 TRACE_RET(chip, retval);
2638
2639 if (!CHK_MSPRO(ms_card)) {
2640 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2641 if (retval != STATUS_SUCCESS)
2642 TRACE_RET(chip, retval);
2643 }
2644
2645 RTS51X_DEBUGP("ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2646
2647 return STATUS_SUCCESS;
2648 }
2649
2650 static int mspro_set_rw_cmd(struct rts51x_chip *chip, u32 start_sec,
2651 u16 sec_cnt, u8 cmd)
2652 {
2653 int retval, i;
2654 u8 data[8];
2655
2656 data[0] = cmd;
2657 data[1] = (u8) (sec_cnt >> 8);
2658 data[2] = (u8) sec_cnt;
2659 data[3] = (u8) (start_sec >> 24);
2660 data[4] = (u8) (start_sec >> 16);
2661 data[5] = (u8) (start_sec >> 8);
2662 data[6] = (u8) start_sec;
2663 data[7] = 0;
2664
2665 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2666 retval =
2667 ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);
2668 if (retval == STATUS_SUCCESS)
2669 break;
2670 }
2671 if (i == MS_MAX_RETRY_COUNT)
2672 TRACE_RET(chip, STATUS_FAIL);
2673
2674 return STATUS_SUCCESS;
2675 }
2676
2677 static void mspro_stop_seq_mode(struct rts51x_chip *chip)
2678 {
2679 struct ms_info *ms_card = &(chip->ms_card);
2680 int retval;
2681
2682 if (ms_card->seq_mode) {
2683 retval = ms_switch_clock(chip);
2684 if (retval != STATUS_SUCCESS)
2685 return;
2686
2687 ms_card->seq_mode = 0;
2688 ms_card->total_sec_cnt = 0;
2689 ms_card->last_rw_int = 0;
2690 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2691
2692 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
2693 FIFO_FLUSH);
2694 }
2695 }
2696
2697 static inline int ms_auto_tune_clock(struct rts51x_chip *chip)
2698 {
2699 struct ms_info *ms_card = &(chip->ms_card);
2700 int retval;
2701
2702 if (chip->asic_code) {
2703 if (ms_card->ms_clock > 30)
2704 ms_card->ms_clock -= 20;
2705 } else {
2706 if (ms_card->ms_clock == CLK_80)
2707 ms_card->ms_clock = CLK_60;
2708 else if (ms_card->ms_clock == CLK_60)
2709 ms_card->ms_clock = CLK_40;
2710 }
2711
2712 retval = ms_switch_clock(chip);
2713 if (retval != STATUS_SUCCESS)
2714 TRACE_RET(chip, retval);
2715
2716 return STATUS_SUCCESS;
2717 }
2718
2719 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2720 struct rts51x_chip *chip, u32 start_sector,
2721 u16 sector_cnt)
2722 {
2723 struct ms_info *ms_card = &(chip->ms_card);
2724 int retval, mode_2k = 0;
2725 u16 count;
2726 u8 val, trans_mode, rw_tpc, rw_cmd;
2727
2728 ms_set_err_code(chip, MS_NO_ERROR);
2729
2730 ms_card->counter = 0;
2731
2732 if (CHK_MSHG(ms_card)) {
2733 if ((start_sector % 4) || (sector_cnt % 4)) {
2734 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2735 rw_tpc = PRO_READ_LONG_DATA;
2736 rw_cmd = PRO_READ_DATA;
2737 } else {
2738 rw_tpc = PRO_WRITE_LONG_DATA;
2739 rw_cmd = PRO_WRITE_DATA;
2740 }
2741 } else {
2742 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2743 rw_tpc = PRO_READ_QUAD_DATA;
2744 rw_cmd = PRO_READ_2K_DATA;
2745 } else {
2746 rw_tpc = PRO_WRITE_QUAD_DATA;
2747 rw_cmd = PRO_WRITE_2K_DATA;
2748 }
2749 mode_2k = 1;
2750 }
2751 } else {
2752 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2753 rw_tpc = PRO_READ_LONG_DATA;
2754 rw_cmd = PRO_READ_DATA;
2755 } else {
2756 rw_tpc = PRO_WRITE_LONG_DATA;
2757 rw_cmd = PRO_WRITE_DATA;
2758 }
2759 }
2760
2761 retval = ms_switch_clock(chip);
2762 if (retval != STATUS_SUCCESS)
2763 TRACE_RET(chip, retval);
2764
2765 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2766 trans_mode = MS_TM_AUTO_READ;
2767 else
2768 trans_mode = MS_TM_AUTO_WRITE;
2769
2770 val = ms_card->last_rw_int;
2771
2772 if (ms_card->seq_mode) {
2773 if ((ms_card->pre_dir != srb->sc_data_direction)
2774 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) !=
2775 start_sector)
2776 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
2777 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
2778 || !(val & MS_INT_BREQ)
2779 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2780 ms_card->seq_mode = 0;
2781 ms_card->total_sec_cnt = 0;
2782 ms_card->last_rw_int = 0;
2783 if (val & MS_INT_BREQ) {
2784 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2785 if (retval != STATUS_SUCCESS)
2786 TRACE_RET(chip, retval);
2787
2788 rts51x_ep0_write_register(chip, MC_FIFO_CTL,
2789 FIFO_FLUSH, FIFO_FLUSH);
2790 }
2791 }
2792 }
2793
2794 if (!ms_card->seq_mode) {
2795 ms_card->total_sec_cnt = 0;
2796 if (sector_cnt >= 0x80) {
2797 if ((ms_card->capacity - start_sector) > 0xFE00)
2798 count = 0xFE00;
2799 else
2800 count =
2801 (u16) (ms_card->capacity - start_sector);
2802 if (count > sector_cnt) {
2803 if (mode_2k)
2804 ms_card->seq_mode |= MODE_2K_SEQ;
2805 else
2806 ms_card->seq_mode |= MODE_512_SEQ;
2807 }
2808 } else {
2809 count = sector_cnt;
2810 }
2811 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2812 if (retval != STATUS_SUCCESS) {
2813 ms_card->seq_mode = 0;
2814 TRACE_RET(chip, retval);
2815 }
2816 }
2817
2818 retval =
2819 ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, WAIT_INT,
2820 mode_2k, scsi_sg_count(srb), scsi_sglist(srb),
2821 scsi_bufflen(srb));
2822 if (retval != STATUS_SUCCESS) {
2823 ms_card->seq_mode = 0;
2824 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
2825 rts51x_clear_ms_error(chip);
2826 if (val & MS_INT_BREQ)
2827 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2828 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2829 RTS51X_DEBUGP("MSPro CRC error, tune clock!\n");
2830 ms_auto_tune_clock(chip);
2831 }
2832
2833 TRACE_RET(chip, retval);
2834 }
2835
2836 ms_card->pre_sec_addr = start_sector;
2837 ms_card->pre_sec_cnt = sector_cnt;
2838 ms_card->pre_dir = srb->sc_data_direction;
2839 ms_card->total_sec_cnt += sector_cnt;
2840
2841 return STATUS_SUCCESS;
2842 }
2843
2844 static int mspro_read_format_progress(struct rts51x_chip *chip,
2845 const int short_data_len)
2846 {
2847 struct ms_info *ms_card = &(chip->ms_card);
2848 int retval, i;
2849 u32 total_progress, cur_progress;
2850 u8 cnt, tmp;
2851 u8 data[8];
2852
2853 ms_card->format_status = FORMAT_FAIL;
2854
2855 retval = ms_switch_clock(chip);
2856 if (retval != STATUS_SUCCESS)
2857 TRACE_RET(chip, retval);
2858
2859 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);
2860
2861 if ((tmp & (MS_INT_CED | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
2862 ms_card->format_status = FORMAT_SUCCESS;
2863 ms_card->pro_under_formatting = 0;
2864 return STATUS_SUCCESS;
2865 }
2866 if (!
2867 ((tmp & (MS_INT_BREQ | MS_INT_CED | MS_INT_CMDNK | MS_INT_ERR)) ==
2868 MS_INT_BREQ)) {
2869 ms_card->pro_under_formatting = 0;
2870 TRACE_RET(chip, STATUS_FAIL);
2871 }
2872
2873 if (short_data_len >= 256)
2874 cnt = 0;
2875 else
2876 cnt = (u8) short_data_len;
2877
2878 retval =
2879 ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, data, 8);
2880 if (retval != STATUS_SUCCESS)
2881 TRACE_RET(chip, retval);
2882
2883 total_progress =
2884 (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
2885 cur_progress =
2886 (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
2887
2888 RTS51X_DEBUGP("total_progress = %d, cur_progress = %d\n",
2889 total_progress, cur_progress);
2890
2891 if (total_progress == 0) {
2892 ms_card->progress = 0;
2893 } else {
2894 u64 ulltmp = (u64) cur_progress * (u64) 65535;
2895 do_div(ulltmp, total_progress);
2896 ms_card->progress = (u16) ulltmp;
2897 }
2898 RTS51X_DEBUGP("progress = %d\n", ms_card->progress);
2899
2900 for (i = 0; i < 2500; i++) {
2901 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);
2902 if (tmp &
2903 (MS_INT_CED | MS_INT_CMDNK | MS_INT_BREQ | MS_INT_ERR))
2904 break;
2905
2906 wait_timeout(1);
2907 }
2908
2909 if (i == 2500)
2910 TRACE_RET(chip, STATUS_FAIL);
2911
2912 RTS51X_DEBUGP("MSPro format tmp:%d\n", tmp);
2913
2914 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
2915 TRACE_RET(chip, STATUS_FAIL);
2916 if (tmp & MS_INT_CED) {
2917 ms_card->format_status = FORMAT_SUCCESS;
2918 ms_card->pro_under_formatting = 0;
2919 } else if (tmp & MS_INT_BREQ) {
2920 ms_card->format_status = FORMAT_IN_PROGRESS;
2921 } else {
2922 ms_card->format_status = FORMAT_FAIL;
2923 ms_card->pro_under_formatting = 0;
2924 TRACE_RET(chip, STATUS_FAIL);
2925 }
2926
2927 RTS51X_DEBUGP("MSPro format format_status:%d\n",
2928 ms_card->format_status);
2929
2930 return STATUS_SUCCESS;
2931 }
2932
2933 void rts51x_mspro_polling_format_status(struct rts51x_chip *chip)
2934 {
2935 struct ms_info *ms_card = &(chip->ms_card);
2936 int i;
2937
2938 if (ms_card->pro_under_formatting) {
2939 for (i = 0; i < 65535; i++) {
2940 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
2941 if (ms_card->format_status != FORMAT_IN_PROGRESS)
2942 break;
2943 }
2944 }
2945
2946 return;
2947 }
2948
2949 void rts51x_mspro_format_sense(struct rts51x_chip *chip, unsigned int lun)
2950 {
2951 struct ms_info *ms_card = &(chip->ms_card);
2952
2953 if (CHK_FORMAT_STATUS(ms_card, FORMAT_SUCCESS)) {
2954 rts51x_set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
2955 ms_card->pro_under_formatting = 0;
2956 ms_card->progress = 0;
2957 } else if (CHK_FORMAT_STATUS(ms_card, FORMAT_IN_PROGRESS)) {
2958 rts51x_set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04,
2959 0, (u16) (ms_card->progress));
2960 } else {
2961 rts51x_set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED);
2962 ms_card->pro_under_formatting = 0;
2963 ms_card->progress = 0;
2964 }
2965 }
2966
2967 int rts51x_mspro_format(struct scsi_cmnd *srb, struct rts51x_chip *chip,
2968 int short_data_len, int quick_format)
2969 {
2970 struct ms_info *ms_card = &(chip->ms_card);
2971 int retval, i;
2972 u8 buf[8], tmp;
2973 u16 para;
2974
2975 retval = ms_switch_clock(chip);
2976 if (retval != STATUS_SUCCESS)
2977 TRACE_RET(chip, retval);
2978
2979 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
2980 if (retval != STATUS_SUCCESS)
2981 TRACE_RET(chip, retval);
2982
2983 memset(buf, 0, 2);
2984 switch (short_data_len) {
2985 case 32:
2986 buf[0] = 0;
2987 break;
2988 case 64:
2989 buf[0] = 1;
2990 break;
2991 case 128:
2992 buf[0] = 2;
2993 break;
2994 case 256:
2995 default:
2996 buf[0] = 3;
2997 break;
2998 }
2999
3000 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3001 retval =
3002 ms_write_bytes(chip, PRO_WRITE_REG, 1, NO_WAIT_INT, buf, 2);
3003 if (retval == STATUS_SUCCESS)
3004 break;
3005 }
3006 if (i == MS_MAX_RETRY_COUNT)
3007 TRACE_RET(chip, STATUS_FAIL);
3008 /* Format command */
3009 if (quick_format)
3010 para = 0x0000;
3011 else
3012 para = 0x0001;
3013 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
3014 if (retval != STATUS_SUCCESS)
3015 TRACE_RET(chip, retval);
3016 /* Check INT */
3017 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);
3018 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
3019 TRACE_RET(chip, STATUS_FAIL);
3020
3021 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
3022 ms_card->pro_under_formatting = 1;
3023 ms_card->progress = 0;
3024 ms_card->format_status = FORMAT_IN_PROGRESS;
3025 return STATUS_SUCCESS;
3026 }
3027
3028 if (tmp & MS_INT_CED) {
3029 ms_card->pro_under_formatting = 0;
3030 ms_card->progress = 0;
3031 ms_card->format_status = FORMAT_SUCCESS;
3032 rts51x_set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
3033 return STATUS_SUCCESS;
3034 }
3035
3036 TRACE_RET(chip, STATUS_FAIL);
3037 }
3038
3039 #ifdef MS_SPEEDUP
3040 static int ms_read_multiple_pages(struct rts51x_chip *chip, u16 phy_blk,
3041 u16 log_blk, u8 start_page, u8 end_page,
3042 u8 *buf, void **ptr, unsigned int *offset)
3043 {
3044 struct ms_info *ms_card = &(chip->ms_card);
3045 int retval;
3046 int send_blkend;
3047 u8 extra[MS_EXTRA_SIZE], val1, val2, data[6];
3048 u8 page_cnt = end_page - start_page, page_addr, sec_cnt;
3049
3050 if (end_page != (ms_card->page_off + 1))
3051 send_blkend = 1;
3052 else
3053 send_blkend = 0;
3054
3055 retval =
3056 ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);
3057 if (retval == STATUS_SUCCESS) {
3058 if ((extra[1] & 0x30) != 0x30) {
3059 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3060 TRACE_RET(chip, STATUS_FAIL);
3061 }
3062 }
3063
3064 if (CHK_MS4BIT(ms_card)) {
3065 /* Parallel interface */
3066 data[0] = 0x88;
3067 } else {
3068 /* Serial interface */
3069 data[0] = 0x80;
3070 }
3071 /* Block Address */
3072 data[1] = 0;
3073 data[2] = (u8) (phy_blk >> 8);
3074 data[3] = (u8) phy_blk;
3075 /* Page Number
3076 * Extra data access mode */
3077 data[4] = 0;
3078 data[5] = start_page;
3079
3080 retval =
3081 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
3082 BLOCK_READ, WAIT_INT, data, 6, &val1);
3083 if (retval != STATUS_SUCCESS)
3084 TRACE_RET(chip, retval);
3085
3086 rts51x_init_cmd(chip);
3087
3088 if (send_blkend)
3089 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND,
3090 SET_BLKEND);
3091 else
3092 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND, 0);
3093 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, WAIT_INT,
3094 NO_WAIT_INT);
3095 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
3096 (u8) page_cnt);
3097 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, 0);
3098 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
3099
3100 rts51x_trans_dma_enable(DMA_FROM_DEVICE, chip, 512 * page_cnt, DMA_512);
3101
3102 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3103 MS_TRANSFER_START | MS_TM_MULTI_READ);
3104 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
3105 MS_TRANSFER_END);
3106
3107 retval = rts51x_send_cmd(chip, MODE_CDIR | STAGE_MS_STATUS, 100);
3108 if (retval != STATUS_SUCCESS)
3109 TRACE_RET(chip, retval);
3110
3111 retval =
3112 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,
3113 ptr, offset, 512 * page_cnt,
3114 scsi_sg_count(chip->srb), NULL, 2000);
3115 if (retval != STATUS_SUCCESS) {
3116 rts51x_clear_ms_error(chip);
3117 if (retval == STATUS_TIMEDOUT)
3118 TRACE_RET(chip, retval);
3119 TRACE_GOTO(chip, Fail);
3120 }
3121 retval = rts51x_get_rsp(chip, 3, 200);
3122 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3123 rts51x_clear_ms_error(chip);
3124 if (retval == STATUS_TIMEDOUT)
3125 TRACE_RET(chip, retval);
3126 TRACE_GOTO(chip, Fail);
3127 }
3128
3129 return STATUS_SUCCESS;
3130
3131 Fail:
3132 rts51x_init_cmd(chip);
3133
3134 rts51x_add_cmd(chip, READ_REG_CMD, MS_SECTOR_CNT_L, 0, 0);
3135
3136 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);
3137 if (retval != STATUS_SUCCESS)
3138 TRACE_RET(chip, retval);
3139
3140 retval = rts51x_get_rsp(chip, 3, 200);
3141
3142 if (CHECK_MS_TRANS_FAIL(chip, retval))
3143 TRACE_RET(chip, STATUS_FAIL);
3144
3145 sec_cnt = chip->rsp_buf[0];
3146 RTS51X_DEBUGP("%d pages need be transferred, %d pages remained\n",
3147 (int)page_cnt, (int)sec_cnt);
3148 page_addr = start_page + (page_cnt - sec_cnt);
3149
3150 if (CHK_MS4BIT(ms_card)) {
3151 val1 = chip->rsp_buf[1];
3152 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%x\n", val1);
3153 } else {
3154 val1 = 0;
3155 }
3156
3157 val2 = chip->rsp_buf[2];
3158 RTS51X_DEBUGP("GET_INT: 0x%x\n", val2);
3159
3160 if ((val1 & INT_CMDNK) || (val2 & INT_REG_CMDNK)) {
3161 ms_set_err_code(chip, MS_CMD_NK);
3162 TRACE_RET(chip, STATUS_FAIL);
3163 }
3164
3165 if ((val1 & INT_ERR) || (val2 & INT_REG_ERR)) {
3166 if ((val1 & INT_BREQ) || (val2 & INT_REG_BREQ)) {
3167 retval = ms_read_status_reg(chip);
3168 if (retval != STATUS_SUCCESS) {
3169 if (!(chip->card_wp & MS_CARD)) {
3170 reset_ms(chip);
3171 ms_set_page_status(log_blk, setPS_NG,
3172 extra, MS_EXTRA_SIZE);
3173 ms_write_extra_data(chip, phy_blk,
3174 page_addr, extra,
3175 MS_EXTRA_SIZE);
3176 }
3177 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3178 TRACE_RET(chip, STATUS_FAIL);
3179 }
3180 } else {
3181 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3182 TRACE_RET(chip, STATUS_FAIL);
3183 }
3184 } else {
3185 if (CHK_MS4BIT(ms_card)) {
3186 if (!(val1 & INT_BREQ) && !(val2 & INT_REG_BREQ)) {
3187 ms_set_err_code(chip, MS_BREQ_ERROR);
3188 TRACE_RET(chip, STATUS_FAIL);
3189 }
3190 } else {
3191 if (!(val2 & INT_REG_BREQ)) {
3192 ms_set_err_code(chip, MS_BREQ_ERROR);
3193 TRACE_RET(chip, STATUS_FAIL);
3194 }
3195 }
3196 }
3197
3198 TRACE_RET(chip, STATUS_FAIL);
3199 }
3200
3201 static int ms_write_multiple_pages(struct rts51x_chip *chip, u16 old_blk,
3202 u16 new_blk, u16 log_blk, u8 start_page,
3203 u8 end_page, u8 *buf, void **ptr,
3204 unsigned int *offset)
3205 {
3206 struct ms_info *ms_card = &(chip->ms_card);
3207 int retval, i;
3208 int send_blkend;
3209 u8 val, data[16];
3210 u8 page_cnt = end_page - start_page;
3211
3212 if ((end_page == (ms_card->page_off + 1)) || (page_cnt == 1))
3213 send_blkend = 0;
3214 else
3215 send_blkend = 1;
3216
3217 if (!start_page) {
3218 if (CHK_MS4BIT(ms_card)) {
3219 /* Parallel interface */
3220 data[0] = 0x88;
3221 } else {
3222 /* Serial interface */
3223 data[0] = 0x80;
3224 }
3225 /* Block Address */
3226 data[1] = 0;
3227 data[2] = (u8) (old_blk >> 8);
3228 data[3] = (u8) old_blk;
3229 data[4] = 0x80;
3230 data[5] = 0;
3231 data[6] = 0xEF;
3232 data[7] = 0xFF;
3233
3234 retval =
3235 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE,
3236 SystemParm, 7, BLOCK_WRITE, WAIT_INT, data,
3237 7, &val);
3238 if (retval != STATUS_SUCCESS)
3239 TRACE_RET(chip, retval);
3240 }
3241
3242 retval =
3243 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3244 (6 + MS_EXTRA_SIZE));
3245 if (retval != STATUS_SUCCESS)
3246 TRACE_RET(chip, retval);
3247
3248 ms_set_err_code(chip, MS_NO_ERROR);
3249
3250 if (CHK_MS4BIT(ms_card)) {
3251 /* Parallel interface */
3252 data[0] = 0x88;
3253 } else {
3254 /* Serial interface */
3255 data[0] = 0x80;
3256 }
3257 /* Block Address */
3258 data[1] = 0;
3259 data[2] = (u8) (new_blk >> 8);
3260 data[3] = (u8) new_blk;
3261 /* Page Number
3262 * Extra data access mode */
3263 if (page_cnt == 1) {
3264 /* Single page access mode */
3265 data[4] = 0x20;
3266 } else {
3267 /* Block access mode */
3268 data[4] = 0;
3269 }
3270 data[5] = start_page;
3271 data[6] = 0xF8;
3272 data[7] = 0xFF;
3273 data[8] = (u8) (log_blk >> 8);
3274 data[9] = (u8) log_blk;
3275
3276 for (i = 0x0A; i < 0x10; i++) {
3277 /* ECC */
3278 data[i] = 0xFF;
3279 }
3280
3281 retval =
3282 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3283 (6 + MS_EXTRA_SIZE), BLOCK_WRITE, WAIT_INT, data,
3284 16, &val);
3285 if (retval != STATUS_SUCCESS)
3286 TRACE_RET(chip, retval);
3287
3288 rts51x_init_cmd(chip);
3289
3290 if (send_blkend)
3291 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND,
3292 SET_BLKEND);
3293 else
3294 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND, 0);
3295 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, WAIT_INT,
3296 NO_WAIT_INT);
3297 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
3298 (u8) page_cnt);
3299 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, 0);
3300 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, WRITE_PAGE_DATA);
3301 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3302 RING_BUFFER);
3303
3304 rts51x_trans_dma_enable(DMA_TO_DEVICE, chip, 512 * page_cnt, DMA_512);
3305
3306 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3307 MS_TRANSFER_START | MS_TM_MULTI_WRITE);
3308 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
3309 MS_TRANSFER_END);
3310
3311 retval = rts51x_send_cmd(chip, MODE_CDOR | STAGE_MS_STATUS, 100);
3312 if (retval != STATUS_SUCCESS)
3313 TRACE_RET(chip, retval);
3314
3315 retval =
3316 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,
3317 ptr, offset, 512 * page_cnt,
3318 scsi_sg_count(chip->srb), NULL, 2000);
3319 if (retval != STATUS_SUCCESS) {
3320 rts51x_clear_ms_error(chip);
3321 TRACE_RET(chip, retval);
3322 }
3323
3324 retval = rts51x_get_rsp(chip, 3, 2000);
3325
3326
3327 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3328 rts51x_clear_ms_error(chip);
3329 TRACE_RET(chip, STATUS_FAIL);
3330 }
3331
3332 return STATUS_SUCCESS;
3333 }
3334
3335 #else
3336
3337 static int ms_read_multiple_pages(struct rts51x_chip *chip, u16 phy_blk,
3338 u16 log_blk, u8 start_page, u8 end_page,
3339 u8 *buf, void **ptr, unsigned int *offset)
3340 {
3341 struct ms_info *ms_card = &(chip->ms_card);
3342 int retval, i;
3343 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
3344
3345 retval =
3346 ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);
3347 if (retval == STATUS_SUCCESS) {
3348 if ((extra[1] & 0x30) != 0x30) {
3349 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3350 TRACE_RET(chip, STATUS_FAIL);
3351 }
3352 }
3353
3354 retval =
3355 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3356 6);
3357 if (retval != STATUS_SUCCESS)
3358 TRACE_RET(chip, retval);
3359 /* Write REG */
3360 if (CHK_MS4BIT(ms_card)) {
3361 /* Parallel interface */
3362 data[0] = 0x88;
3363 } else {
3364 /* Serial interface */
3365 data[0] = 0x80;
3366 }
3367 /* Block Address */
3368 data[1] = 0;
3369 data[2] = (u8) (phy_blk >> 8);
3370 data[3] = (u8) phy_blk;
3371 /* Page Number
3372 * Extra data access mode */
3373 data[4] = 0;
3374 data[5] = start_page;
3375
3376 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3377 retval =
3378 ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
3379 if (retval == STATUS_SUCCESS)
3380 break;
3381 }
3382 if (i == MS_MAX_RETRY_COUNT)
3383 TRACE_RET(chip, STATUS_FAIL);
3384
3385 ms_set_err_code(chip, MS_NO_ERROR);
3386
3387 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
3388 if (retval != STATUS_SUCCESS)
3389 TRACE_RET(chip, retval);
3390
3391 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3392 ms_set_err_code(chip, MS_NO_ERROR);
3393
3394 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3395 ms_set_err_code(chip, MS_NO_CARD);
3396 chip->card_exist &= ~MS_CARD;
3397 chip->card_ready &= ~MS_CARD;
3398 TRACE_RET(chip, STATUS_FAIL);
3399 }
3400 /* GET_INT Register */
3401 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3402 if (retval != STATUS_SUCCESS)
3403 TRACE_RET(chip, retval);
3404 if (val & INT_REG_CMDNK) {
3405 ms_set_err_code(chip, MS_CMD_NK);
3406 TRACE_RET(chip, STATUS_FAIL);
3407 }
3408 if (val & INT_REG_ERR) {
3409 if (val & INT_REG_BREQ) {
3410 retval = ms_read_status_reg(chip);
3411 if (retval != STATUS_SUCCESS) {
3412 if (!(chip->card_wp & MS_CARD)) {
3413 reset_ms(chip);
3414 ms_set_page_status(log_blk,
3415 setPS_NG, extra,
3416 MS_EXTRA_SIZE);
3417 ms_write_extra_data(chip,
3418 phy_blk, page_addr,
3419 extra, MS_EXTRA_SIZE);
3420 }
3421 ms_set_err_code(chip,
3422 MS_FLASH_READ_ERROR);
3423 TRACE_RET(chip, STATUS_FAIL);
3424 }
3425 } else {
3426 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3427 TRACE_RET(chip, STATUS_FAIL);
3428 }
3429 } else {
3430 if (!(val & INT_REG_BREQ)) {
3431 ms_set_err_code(chip, MS_BREQ_ERROR);
3432 TRACE_RET(chip, STATUS_FAIL);
3433 }
3434 }
3435
3436 if (page_addr == (end_page - 1)) {
3437 if (!(val & INT_REG_CED)) {
3438 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3439 if (retval != STATUS_SUCCESS)
3440 TRACE_RET(chip, retval);
3441 }
3442 retval =
3443 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
3444 1);
3445 if (retval != STATUS_SUCCESS)
3446 TRACE_RET(chip, retval);
3447 if (!(val & INT_REG_CED)) {
3448 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3449 TRACE_RET(chip, STATUS_FAIL);
3450 }
3451
3452 trans_cfg = NO_WAIT_INT;
3453 } else {
3454 trans_cfg = WAIT_INT;
3455 }
3456
3457 rts51x_init_cmd(chip);
3458
3459 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF,
3460 READ_PAGE_DATA);
3461 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
3462 trans_cfg);
3463
3464 rts51x_trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
3465
3466 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3467 MS_TRANSFER_START | MS_TM_NORMAL_READ);
3468 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3469 MS_TRANSFER_END, MS_TRANSFER_END);
3470
3471 retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
3472 if (retval != STATUS_SUCCESS)
3473 TRACE_RET(chip, retval);
3474
3475 retval =
3476 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip),
3477 (void *)buf, ptr, offset, 512,
3478 scsi_sg_count(chip->srb), NULL,
3479 2000);
3480 if (retval != STATUS_SUCCESS) {
3481 if (retval == STATUS_TIMEDOUT) {
3482 ms_set_err_code(chip, MS_TO_ERROR);
3483 rts51x_clear_ms_error(chip);
3484 TRACE_RET(chip, retval);
3485 }
3486
3487 retval =
3488 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
3489 if (retval != STATUS_SUCCESS) {
3490 ms_set_err_code(chip, MS_TO_ERROR);
3491 rts51x_clear_ms_error(chip);
3492 TRACE_RET(chip, STATUS_FAIL);
3493 }
3494 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3495 ms_set_err_code(chip, MS_CRC16_ERROR);
3496 rts51x_clear_ms_error(chip);
3497 TRACE_RET(chip, STATUS_FAIL);
3498 }
3499 }
3500
3501 retval = rts51x_get_rsp(chip, 1, 2000);
3502 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3503 if (retval == STATUS_TIMEDOUT) {
3504 ms_set_err_code(chip, MS_TO_ERROR);
3505 rts51x_clear_ms_error(chip);
3506 TRACE_RET(chip, retval);
3507 }
3508
3509 retval =
3510 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
3511 if (retval != STATUS_SUCCESS) {
3512 ms_set_err_code(chip, MS_TO_ERROR);
3513 rts51x_clear_ms_error(chip);
3514 TRACE_RET(chip, retval);
3515 }
3516 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3517 ms_set_err_code(chip, MS_CRC16_ERROR);
3518 rts51x_clear_ms_error(chip);
3519 TRACE_RET(chip, STATUS_FAIL);
3520 }
3521 }
3522 }
3523
3524 return STATUS_SUCCESS;
3525 }
3526
3527 static int ms_write_multiple_pages(struct rts51x_chip *chip, u16 old_blk,
3528 u16 new_blk, u16 log_blk, u8 start_page,
3529 u8 end_page, u8 *buf, void **ptr,
3530 unsigned int *offset)
3531 {
3532 struct ms_info *ms_card = &(chip->ms_card);
3533 int retval, i;
3534 u8 page_addr, val, data[16];
3535
3536 if (!start_page) {
3537 retval =
3538 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3539 SystemParm, 7);
3540 if (retval != STATUS_SUCCESS)
3541 TRACE_RET(chip, retval);
3542
3543 if (CHK_MS4BIT(ms_card)) {
3544 /* Parallel interface */
3545 data[0] = 0x88;
3546 } else {
3547 /* Serial interface */
3548 data[0] = 0x80;
3549 }
3550 /* Block Address */
3551 data[1] = 0;
3552 data[2] = (u8) (old_blk >> 8);
3553 data[3] = (u8) old_blk;
3554 data[4] = 0x80;
3555 data[5] = 0;
3556 data[6] = 0xEF;
3557 data[7] = 0xFF;
3558
3559 retval =
3560 ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);
3561 if (retval != STATUS_SUCCESS)
3562 TRACE_RET(chip, retval);
3563
3564 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3565 if (retval != STATUS_SUCCESS)
3566 TRACE_RET(chip, retval);
3567 /* GET_INT Register */
3568 ms_set_err_code(chip, MS_NO_ERROR);
3569 retval =
3570 ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3571 NO_WAIT_INT);
3572 if (retval != STATUS_SUCCESS)
3573 TRACE_RET(chip, retval);
3574 }
3575
3576 retval =
3577 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3578 (6 + MS_EXTRA_SIZE));
3579 if (retval != STATUS_SUCCESS)
3580 TRACE_RET(chip, retval);
3581
3582 ms_set_err_code(chip, MS_NO_ERROR);
3583
3584 if (CHK_MS4BIT(ms_card)) {
3585 /* Parallel interface */
3586 data[0] = 0x88;
3587 } else {
3588 /* Serial interface */
3589 data[0] = 0x80;
3590 }
3591 /* Block Address */
3592 data[1] = 0;
3593 data[2] = (u8) (new_blk >> 8);
3594 data[3] = (u8) new_blk;
3595 /* Page Number
3596 * Extra data access mode */
3597 if ((end_page - start_page) == 1) {
3598 /* Single page access mode */
3599 data[4] = 0x20;
3600 } else {
3601 /* Block access mode */
3602 data[4] = 0;
3603 }
3604 data[5] = start_page;
3605 data[6] = 0xF8;
3606 data[7] = 0xFF;
3607 data[8] = (u8) (log_blk >> 8);
3608 data[9] = (u8) log_blk;
3609
3610 for (i = 0x0A; i < 0x10; i++) {
3611 /* ECC */
3612 data[i] = 0xFF;
3613 }
3614
3615 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3616 retval =
3617 ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3618 NO_WAIT_INT, data, 16);
3619 if (retval == STATUS_SUCCESS)
3620 break;
3621 }
3622 if (i == MS_MAX_RETRY_COUNT)
3623 TRACE_RET(chip, STATUS_FAIL);
3624
3625 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3626 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3627 if (retval == STATUS_SUCCESS)
3628 break;
3629 }
3630 if (i == MS_MAX_RETRY_COUNT)
3631 TRACE_RET(chip, STATUS_FAIL);
3632 /* GET_INT Register */
3633 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3634 if (retval != STATUS_SUCCESS)
3635 TRACE_RET(chip, retval);
3636
3637 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3638 ms_set_err_code(chip, MS_NO_ERROR);
3639
3640 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3641 ms_set_err_code(chip, MS_NO_CARD);
3642 TRACE_RET(chip, STATUS_FAIL);
3643 }
3644
3645 if (val & INT_REG_CMDNK) {
3646 ms_set_err_code(chip, MS_CMD_NK);
3647 TRACE_RET(chip, STATUS_FAIL);
3648 }
3649 if (val & INT_REG_ERR) {
3650 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3651 TRACE_RET(chip, STATUS_FAIL);
3652 }
3653 if (!(val & INT_REG_BREQ)) {
3654 ms_set_err_code(chip, MS_BREQ_ERROR);
3655 TRACE_RET(chip, STATUS_FAIL);
3656 }
3657
3658 udelay(30);
3659
3660 rts51x_init_cmd(chip);
3661
3662 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF,
3663 WRITE_PAGE_DATA);
3664 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
3665 WAIT_INT);
3666
3667 rts51x_trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3668
3669 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3670 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3671 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3672 MS_TRANSFER_END, MS_TRANSFER_END);
3673
3674 retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
3675 if (retval != STATUS_SUCCESS)
3676 TRACE_RET(chip, retval);
3677
3678 retval =
3679 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip),
3680 (void *)buf, ptr, offset, 512,
3681 scsi_sg_count(chip->srb), NULL,
3682 2000);
3683 if (retval != STATUS_SUCCESS) {
3684 ms_set_err_code(chip, MS_TO_ERROR);
3685 rts51x_clear_ms_error(chip);
3686
3687 if (retval == STATUS_TIMEDOUT)
3688 TRACE_RET(chip, STATUS_TIMEDOUT);
3689 else
3690 TRACE_RET(chip, STATUS_FAIL);
3691 }
3692
3693 retval = rts51x_get_rsp(chip, 1, 2000);
3694 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3695 ms_set_err_code(chip, MS_TO_ERROR);
3696 rts51x_clear_ms_error(chip);
3697
3698 if (retval == STATUS_TIMEDOUT)
3699 TRACE_RET(chip, STATUS_TIMEDOUT);
3700 else
3701 TRACE_RET(chip, STATUS_FAIL);
3702 }
3703 /* GET_INT Register */
3704 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3705 if (retval != STATUS_SUCCESS)
3706 TRACE_RET(chip, retval);
3707
3708 if ((end_page - start_page) == 1) {
3709 if (!(val & INT_REG_CED)) {
3710 /* Command can not be executed */
3711 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3712 TRACE_RET(chip, STATUS_FAIL);
3713 }
3714 } else {
3715 if (page_addr == (end_page - 1)) {
3716 if (!(val & INT_REG_CED)) {
3717 retval =
3718 ms_send_cmd(chip, BLOCK_END,
3719 WAIT_INT);
3720 if (retval != STATUS_SUCCESS)
3721 TRACE_RET(chip, retval);
3722 }
3723 /* GET_INT Register */
3724 retval =
3725 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
3726 &val, 1);
3727 if (retval != STATUS_SUCCESS)
3728 TRACE_RET(chip, retval);
3729 }
3730
3731 if ((page_addr == (end_page - 1))
3732 || (page_addr == ms_card->page_off)) {
3733 if (!(val & INT_REG_CED)) {
3734 ms_set_err_code(chip,
3735 MS_FLASH_WRITE_ERROR);
3736 TRACE_RET(chip, STATUS_FAIL);
3737 }
3738 }
3739 }
3740 }
3741
3742 return STATUS_SUCCESS;
3743 }
3744 #endif
3745
3746 static int ms_finish_write(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
3747 u16 log_blk, u8 page_off)
3748 {
3749 struct ms_info *ms_card = &(chip->ms_card);
3750 int retval, seg_no;
3751
3752 #ifdef MS_SPEEDUP
3753 retval = ms_auto_copy_page(chip, old_blk, new_blk, log_blk,
3754 page_off, ms_card->page_off + 1);
3755 #else
3756 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3757 page_off, ms_card->page_off + 1);
3758 #endif
3759 if (retval != STATUS_SUCCESS)
3760 TRACE_RET(chip, retval);
3761
3762 seg_no = old_blk >> 9;
3763
3764 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3765 MS_CLR_BAD_BLOCK_FLG(ms_card);
3766 ms_set_bad_block(chip, old_blk);
3767 } else {
3768 retval = ms_erase_block(chip, old_blk);
3769 if (retval == STATUS_SUCCESS)
3770 ms_set_unused_block(chip, old_blk);
3771 }
3772
3773 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3774
3775 return STATUS_SUCCESS;
3776 }
3777
3778 static int ms_prepare_write(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
3779 u16 log_blk, u8 start_page)
3780 {
3781 int retval;
3782
3783 if (start_page) {
3784 #ifdef MS_SPEEDUP
3785 retval =
3786 ms_auto_copy_page(chip, old_blk, new_blk, log_blk, 0,
3787 start_page);
3788 #else
3789 retval =
3790 ms_copy_page(chip, old_blk, new_blk, log_blk, 0,
3791 start_page);
3792 #endif
3793 if (retval != STATUS_SUCCESS)
3794 TRACE_RET(chip, retval);
3795 }
3796
3797 return STATUS_SUCCESS;
3798 }
3799
3800 int rts51x_ms_delay_write(struct rts51x_chip *chip)
3801 {
3802 struct ms_info *ms_card = &(chip->ms_card);
3803 struct rts51x_ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3804 int retval;
3805
3806 if (delay_write->delay_write_flag) {
3807 retval = ms_set_init_para(chip);
3808 if (retval != STATUS_SUCCESS)
3809 TRACE_RET(chip, retval);
3810
3811 delay_write->delay_write_flag = 0;
3812 retval = ms_finish_write(chip,
3813 delay_write->old_phyblock,
3814 delay_write->new_phyblock,
3815 delay_write->logblock,
3816 delay_write->pageoff);
3817 if (retval != STATUS_SUCCESS)
3818 TRACE_RET(chip, retval);
3819 }
3820
3821 return STATUS_SUCCESS;
3822 }
3823
3824 static inline void rts51x_ms_rw_fail(struct scsi_cmnd *srb, struct rts51x_chip *chip)
3825 {
3826 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3827 rts51x_set_sense_type(chip, SCSI_LUN(srb),
3828 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3829 else
3830 rts51x_set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3831 }
3832
3833 static int rts51x_ms_rw_multi_sector(struct scsi_cmnd *srb, struct rts51x_chip *chip,
3834 u32 start_sector, u16 sector_cnt)
3835 {
3836 struct ms_info *ms_card = &(chip->ms_card);
3837 unsigned int lun = SCSI_LUN(srb);
3838 int retval, seg_no;
3839 unsigned int offset = 0;
3840 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3841 u8 start_page, end_page = 0, page_cnt;
3842 u8 *buf;
3843 void *ptr = NULL;
3844 struct rts51x_ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3845
3846 ms_set_err_code(chip, MS_NO_ERROR);
3847
3848 ms_card->counter = 0;
3849
3850 buf = (u8 *) scsi_sglist(srb);
3851
3852 retval = ms_switch_clock(chip);
3853 if (retval != STATUS_SUCCESS) {
3854 rts51x_ms_rw_fail(srb, chip);
3855 TRACE_RET(chip, retval);
3856 }
3857
3858 log_blk = (u16) (start_sector >> ms_card->block_shift);
3859 start_page = (u8) (start_sector & ms_card->page_off);
3860
3861 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3862 if (log_blk < ms_start_idx[seg_no + 1])
3863 break;
3864 }
3865
3866 if (ms_card->segment[seg_no].build_flag == 0) {
3867 retval = ms_build_l2p_tbl(chip, seg_no);
3868 if (retval != STATUS_SUCCESS) {
3869 chip->card_fail |= MS_CARD;
3870 rts51x_set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3871 TRACE_RET(chip, retval);
3872 }
3873 }
3874
3875 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3876 if (delay_write->delay_write_flag &&
3877 (delay_write->logblock == log_blk) &&
3878 (start_page > delay_write->pageoff)) {
3879 delay_write->delay_write_flag = 0;
3880 #ifdef MS_SPEEDUP
3881 retval = ms_auto_copy_page(chip,
3882 delay_write->old_phyblock,
3883 delay_write->new_phyblock,
3884 log_blk,
3885 delay_write->pageoff,
3886 start_page);
3887 #else
3888 retval = ms_copy_page(chip,
3889 delay_write->old_phyblock,
3890 delay_write->new_phyblock,
3891 log_blk, delay_write->pageoff,
3892 start_page);
3893 #endif
3894 if (retval != STATUS_SUCCESS) {
3895 rts51x_set_sense_type(chip, lun,
3896 SENSE_TYPE_MEDIA_WRITE_ERR);
3897 TRACE_RET(chip, retval);
3898 }
3899 old_blk = delay_write->old_phyblock;
3900 new_blk = delay_write->new_phyblock;
3901 } else if (delay_write->delay_write_flag &&
3902 (delay_write->logblock == log_blk) &&
3903 (start_page == delay_write->pageoff)) {
3904 delay_write->delay_write_flag = 0;
3905 old_blk = delay_write->old_phyblock;
3906 new_blk = delay_write->new_phyblock;
3907 } else {
3908 retval = rts51x_ms_delay_write(chip);
3909 if (retval != STATUS_SUCCESS) {
3910 rts51x_set_sense_type(chip, lun,
3911 SENSE_TYPE_MEDIA_WRITE_ERR);
3912 TRACE_RET(chip, retval);
3913 }
3914 old_blk =
3915 ms_get_l2p_tbl(chip, seg_no,
3916 log_blk - ms_start_idx[seg_no]);
3917 new_blk = ms_get_unused_block(chip, seg_no);
3918 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3919 rts51x_set_sense_type(chip, lun,
3920 SENSE_TYPE_MEDIA_WRITE_ERR);
3921 TRACE_RET(chip, STATUS_FAIL);
3922 }
3923
3924 retval =
3925 ms_prepare_write(chip, old_blk, new_blk, log_blk,
3926 start_page);
3927 if (retval != STATUS_SUCCESS) {
3928 if (monitor_card_cd(chip, MS_CARD) ==
3929 CD_NOT_EXIST) {
3930 rts51x_set_sense_type(chip, lun,
3931 SENSE_TYPE_MEDIA_NOT_PRESENT);
3932 TRACE_RET(chip, STATUS_FAIL);
3933 }
3934
3935 rts51x_set_sense_type(chip, lun,
3936 SENSE_TYPE_MEDIA_WRITE_ERR);
3937 TRACE_RET(chip, retval);
3938 }
3939 }
3940 } else {
3941 retval = rts51x_ms_delay_write(chip);
3942 if (retval != STATUS_SUCCESS) {
3943 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3944 rts51x_set_sense_type(chip, lun,
3945 SENSE_TYPE_MEDIA_NOT_PRESENT);
3946 TRACE_RET(chip, STATUS_FAIL);
3947 }
3948
3949 rts51x_set_sense_type(chip, lun,
3950 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3951 TRACE_RET(chip, retval);
3952 }
3953 old_blk =
3954 ms_get_l2p_tbl(chip, seg_no,
3955 log_blk - ms_start_idx[seg_no]);
3956 if (old_blk == 0xFFFF) {
3957 rts51x_set_sense_type(chip, lun,
3958 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3959 TRACE_RET(chip, STATUS_FAIL);
3960 }
3961 }
3962
3963 RTS51X_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no,
3964 old_blk, new_blk);
3965
3966 while (total_sec_cnt) {
3967 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3968 end_page = ms_card->page_off + 1;
3969 else
3970 end_page = start_page + (u8) total_sec_cnt;
3971 page_cnt = end_page - start_page;
3972
3973 RTS51X_DEBUGP("start_page = %d, end_page = %d, page_cnt = %d\n",
3974 start_page, end_page, page_cnt);
3975
3976 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3977 retval = ms_read_multiple_pages(chip,
3978 old_blk, log_blk,
3979 start_page, end_page,
3980 buf, &ptr, &offset);
3981 else
3982 retval = ms_write_multiple_pages(chip, old_blk,
3983 new_blk, log_blk,
3984 start_page, end_page,
3985 buf, &ptr, &offset);
3986
3987 if (retval != STATUS_SUCCESS) {
3988 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3989 rts51x_set_sense_type(chip, lun,
3990 SENSE_TYPE_MEDIA_NOT_PRESENT);
3991 TRACE_RET(chip, STATUS_FAIL);
3992 }
3993
3994 rts51x_ms_rw_fail(srb, chip);
3995 TRACE_RET(chip, retval);
3996 }
3997 /* Update L2P table if need */
3998 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3999 if (end_page == (ms_card->page_off + 1)) {
4000 retval = ms_erase_block(chip, old_blk);
4001 if (retval == STATUS_SUCCESS)
4002 ms_set_unused_block(chip, old_blk);
4003 ms_set_l2p_tbl(chip, seg_no,
4004 log_blk - ms_start_idx[seg_no],
4005 new_blk);
4006 }
4007 }
4008
4009 total_sec_cnt -= page_cnt;
4010
4011 if (total_sec_cnt == 0)
4012 break;
4013
4014 log_blk++;
4015
4016 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
4017 seg_no++) {
4018 if (log_blk < ms_start_idx[seg_no + 1])
4019 break;
4020 }
4021
4022 if (ms_card->segment[seg_no].build_flag == 0) {
4023 retval = ms_build_l2p_tbl(chip, seg_no);
4024 if (retval != STATUS_SUCCESS) {
4025 chip->card_fail |= MS_CARD;
4026 rts51x_set_sense_type(chip, lun,
4027 SENSE_TYPE_MEDIA_NOT_PRESENT);
4028 TRACE_RET(chip, retval);
4029 }
4030 }
4031
4032 old_blk =
4033 ms_get_l2p_tbl(chip, seg_no,
4034 log_blk - ms_start_idx[seg_no]);
4035 if (old_blk == 0xFFFF) {
4036 rts51x_ms_rw_fail(srb, chip);
4037 TRACE_RET(chip, STATUS_FAIL);
4038 }
4039
4040 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4041 new_blk = ms_get_unused_block(chip, seg_no);
4042 if (new_blk == 0xFFFF) {
4043 rts51x_ms_rw_fail(srb, chip);
4044 TRACE_RET(chip, STATUS_FAIL);
4045 }
4046 }
4047
4048 RTS51X_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
4049 seg_no, old_blk, new_blk);
4050
4051 start_page = 0;
4052 }
4053
4054 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4055 if (end_page < (ms_card->page_off + 1)) {
4056 delay_write->delay_write_flag = 1;
4057 delay_write->old_phyblock = old_blk;
4058 delay_write->new_phyblock = new_blk;
4059 delay_write->logblock = log_blk;
4060 delay_write->pageoff = end_page;
4061 }
4062 }
4063
4064 scsi_set_resid(srb, 0);
4065
4066 return STATUS_SUCCESS;
4067 }
4068
4069 int rts51x_ms_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
4070 u16 sector_cnt)
4071 {
4072 struct ms_info *ms_card = &(chip->ms_card);
4073 int retval;
4074
4075 if (CHK_MSPRO(ms_card))
4076 retval =
4077 mspro_rw_multi_sector(srb, chip, start_sector, sector_cnt);
4078 else
4079 retval =
4080 rts51x_ms_rw_multi_sector(srb, chip, start_sector, sector_cnt);
4081
4082 return retval;
4083 }
4084
4085 void rts51x_ms_free_l2p_tbl(struct rts51x_chip *chip)
4086 {
4087 struct ms_info *ms_card = &(chip->ms_card);
4088 int i = 0;
4089
4090 if (ms_card->segment != NULL) {
4091 for (i = 0; i < ms_card->segment_cnt; i++) {
4092 if (ms_card->segment[i].l2p_table != NULL) {
4093 vfree(ms_card->segment[i].l2p_table);
4094 ms_card->segment[i].l2p_table = NULL;
4095 }
4096 if (ms_card->segment[i].free_table != NULL) {
4097 vfree(ms_card->segment[i].free_table);
4098 ms_card->segment[i].free_table = NULL;
4099 }
4100 }
4101 vfree(ms_card->segment);
4102 ms_card->segment = NULL;
4103 }
4104 }
4105
4106 void rts51x_ms_cleanup_work(struct rts51x_chip *chip)
4107 {
4108 struct ms_info *ms_card = &(chip->ms_card);
4109
4110 if (CHK_MSPRO(ms_card)) {
4111 if (ms_card->seq_mode) {
4112 RTS51X_DEBUGP("MS Pro: stop transmission\n");
4113 mspro_stop_seq_mode(chip);
4114 ms_card->counter = 0;
4115 }
4116 if (CHK_MSHG(ms_card)) {
4117 u8 value;
4118 rts51x_read_register(chip, MS_CFG, &value);
4119 if (value & MS_2K_SECTOR_MODE)
4120 rts51x_write_register(chip, MS_CFG,
4121 MS_2K_SECTOR_MODE, 0x00);
4122 }
4123 } else if ((!CHK_MSPRO(ms_card))
4124 && ms_card->delay_write.delay_write_flag) {
4125 RTS51X_DEBUGP("MS: delay write\n");
4126 rts51x_ms_delay_write(chip);
4127 ms_card->counter = 0;
4128 }
4129 }
4130
4131 static int ms_power_off_card3v3(struct rts51x_chip *chip)
4132 {
4133 int retval;
4134
4135 rts51x_init_cmd(chip);
4136
4137 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
4138 if (chip->asic_code)
4139 ms_pull_ctl_disable(chip);
4140 else
4141 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
4142 FPGA_MS_PULL_CTL_BIT | 0x20,
4143 FPGA_MS_PULL_CTL_BIT);
4144 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
4145 if (!chip->option.FT2_fast_mode) {
4146 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
4147 POWER_OFF);
4148 }
4149
4150 retval = rts51x_send_cmd(chip, MODE_C, 100);
4151 if (retval != STATUS_SUCCESS)
4152 TRACE_RET(chip, retval);
4153
4154 return STATUS_SUCCESS;
4155 }
4156
4157 int rts51x_release_ms_card(struct rts51x_chip *chip)
4158 {
4159 struct ms_info *ms_card = &(chip->ms_card);
4160 int retval;
4161
4162 RTS51X_DEBUGP("rts51x_release_ms_card\n");
4163
4164 ms_card->delay_write.delay_write_flag = 0;
4165 ms_card->pro_under_formatting = 0;
4166
4167 chip->card_ready &= ~MS_CARD;
4168 chip->card_fail &= ~MS_CARD;
4169 chip->card_wp &= ~MS_CARD;
4170
4171 rts51x_ms_free_l2p_tbl(chip);
4172
4173 rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
4174
4175 memset(ms_card->raw_sys_info, 0, 96);
4176 #ifdef SUPPORT_PCGL_1P18
4177 memset(ms_card->raw_model_name, 0, 48);
4178 #endif
4179
4180 retval = ms_power_off_card3v3(chip);
4181 if (retval != STATUS_SUCCESS)
4182 TRACE_RET(chip, retval);
4183
4184 return STATUS_SUCCESS;
4185 }
Linux with added FPC-III support