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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / arch / arm / mach-davinci / devices-da8xx.c
blobddfdd820e6f2b99f6bfa80a51a287255794d74d5
1 /*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-contiguous.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19 #include <linux/reboot.h>
20
21 #include <mach/cputype.h>
22 #include <mach/common.h>
23 #include <mach/time.h>
24 #include <mach/da8xx.h>
25 #include <mach/cpuidle.h>
26 #include <mach/sram.h>
27
28 #include "clock.h"
29 #include "asp.h"
30
31 #define DA8XX_TPCC_BASE 0x01c00000
32 #define DA8XX_TPTC0_BASE 0x01c08000
33 #define DA8XX_TPTC1_BASE 0x01c08400
34 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
35 #define DA8XX_I2C0_BASE 0x01c22000
36 #define DA8XX_RTC_BASE 0x01c23000
37 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
38 #define DA8XX_MMCSD0_BASE 0x01c40000
39 #define DA8XX_SPI0_BASE 0x01c41000
40 #define DA830_SPI1_BASE 0x01e12000
41 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
42 #define DA850_SATA_BASE 0x01e18000
43 #define DA850_MMCSD1_BASE 0x01e1b000
44 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
45 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
46 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
47 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
48 #define DA8XX_I2C1_BASE 0x01e28000
49 #define DA850_TPCC1_BASE 0x01e30000
50 #define DA850_TPTC2_BASE 0x01e38000
51 #define DA850_SPI1_BASE 0x01f0e000
52 #define DA8XX_DDR2_CTL_BASE 0xb0000000
53
54 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
55 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
56 #define DA8XX_EMAC_RAM_OFFSET 0x0000
57 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
58
59 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
60 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
61 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
62 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
63 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
64 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
65 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
66 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
67
68 void __iomem *da8xx_syscfg0_base;
69 void __iomem *da8xx_syscfg1_base;
70
71 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
72 {
73 .mapbase = DA8XX_UART0_BASE,
74 .irq = IRQ_DA8XX_UARTINT0,
75 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
76 UPF_IOREMAP,
77 .iotype = UPIO_MEM,
78 .regshift = 2,
79 },
80 {
81 .flags = 0,
82 }
83 };
84 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
85 {
86 .mapbase = DA8XX_UART1_BASE,
87 .irq = IRQ_DA8XX_UARTINT1,
88 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
89 UPF_IOREMAP,
90 .iotype = UPIO_MEM,
91 .regshift = 2,
92 },
93 {
94 .flags = 0,
95 }
96 };
97 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
98 {
99 .mapbase = DA8XX_UART2_BASE,
100 .irq = IRQ_DA8XX_UARTINT2,
101 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
102 UPF_IOREMAP,
103 .iotype = UPIO_MEM,
104 .regshift = 2,
105 },
106 {
107 .flags = 0,
108 }
109 };
110
111 struct platform_device da8xx_serial_device[] = {
112 {
113 .name = "serial8250",
114 .id = PLAT8250_DEV_PLATFORM,
115 .dev = {
116 .platform_data = da8xx_serial0_pdata,
117 }
118 },
119 {
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM1,
122 .dev = {
123 .platform_data = da8xx_serial1_pdata,
124 }
125 },
126 {
127 .name = "serial8250",
128 .id = PLAT8250_DEV_PLATFORM2,
129 .dev = {
130 .platform_data = da8xx_serial2_pdata,
131 }
132 },
133 {
134 }
135 };
136
137 static s8 da8xx_queue_priority_mapping[][2] = {
138 /* {event queue no, Priority} */
139 {0, 3},
140 {1, 7},
141 {-1, -1}
142 };
143
144 static s8 da850_queue_priority_mapping[][2] = {
145 /* {event queue no, Priority} */
146 {0, 3},
147 {-1, -1}
148 };
149
150 static struct edma_soc_info da830_edma_cc0_info = {
151 .queue_priority_mapping = da8xx_queue_priority_mapping,
152 .default_queue = EVENTQ_1,
153 };
154
155 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
156 &da830_edma_cc0_info,
157 };
158
159 static struct edma_soc_info da850_edma_cc_info[] = {
160 {
161 .queue_priority_mapping = da8xx_queue_priority_mapping,
162 .default_queue = EVENTQ_1,
163 },
164 {
165 .queue_priority_mapping = da850_queue_priority_mapping,
166 .default_queue = EVENTQ_0,
167 },
168 };
169
170 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
171 &da850_edma_cc_info[0],
172 &da850_edma_cc_info[1],
173 };
174
175 static struct resource da830_edma_resources[] = {
176 {
177 .name = "edma_cc0",
178 .start = DA8XX_TPCC_BASE,
179 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 {
183 .name = "edma_tc0",
184 .start = DA8XX_TPTC0_BASE,
185 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 {
189 .name = "edma_tc1",
190 .start = DA8XX_TPTC1_BASE,
191 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
192 .flags = IORESOURCE_MEM,
193 },
194 {
195 .name = "edma0",
196 .start = IRQ_DA8XX_CCINT0,
197 .flags = IORESOURCE_IRQ,
198 },
199 {
200 .name = "edma0_err",
201 .start = IRQ_DA8XX_CCERRINT,
202 .flags = IORESOURCE_IRQ,
203 },
204 };
205
206 static struct resource da850_edma_resources[] = {
207 {
208 .name = "edma_cc0",
209 .start = DA8XX_TPCC_BASE,
210 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
211 .flags = IORESOURCE_MEM,
212 },
213 {
214 .name = "edma_tc0",
215 .start = DA8XX_TPTC0_BASE,
216 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
217 .flags = IORESOURCE_MEM,
218 },
219 {
220 .name = "edma_tc1",
221 .start = DA8XX_TPTC1_BASE,
222 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
223 .flags = IORESOURCE_MEM,
224 },
225 {
226 .name = "edma_cc1",
227 .start = DA850_TPCC1_BASE,
228 .end = DA850_TPCC1_BASE + SZ_32K - 1,
229 .flags = IORESOURCE_MEM,
230 },
231 {
232 .name = "edma_tc2",
233 .start = DA850_TPTC2_BASE,
234 .end = DA850_TPTC2_BASE + SZ_1K - 1,
235 .flags = IORESOURCE_MEM,
236 },
237 {
238 .name = "edma0",
239 .start = IRQ_DA8XX_CCINT0,
240 .flags = IORESOURCE_IRQ,
241 },
242 {
243 .name = "edma0_err",
244 .start = IRQ_DA8XX_CCERRINT,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .name = "edma1",
249 .start = IRQ_DA850_CCINT1,
250 .flags = IORESOURCE_IRQ,
251 },
252 {
253 .name = "edma1_err",
254 .start = IRQ_DA850_CCERRINT1,
255 .flags = IORESOURCE_IRQ,
256 },
257 };
258
259 static struct platform_device da830_edma_device = {
260 .name = "edma",
261 .id = -1,
262 .dev = {
263 .platform_data = da830_edma_info,
264 },
265 .num_resources = ARRAY_SIZE(da830_edma_resources),
266 .resource = da830_edma_resources,
267 };
268
269 static struct platform_device da850_edma_device = {
270 .name = "edma",
271 .id = -1,
272 .dev = {
273 .platform_data = da850_edma_info,
274 },
275 .num_resources = ARRAY_SIZE(da850_edma_resources),
276 .resource = da850_edma_resources,
277 };
278
279 int __init da830_register_edma(struct edma_rsv_info *rsv)
280 {
281 da830_edma_cc0_info.rsv = rsv;
282
283 return platform_device_register(&da830_edma_device);
284 }
285
286 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
287 {
288 if (rsv) {
289 da850_edma_cc_info[0].rsv = rsv[0];
290 da850_edma_cc_info[1].rsv = rsv[1];
291 }
292
293 return platform_device_register(&da850_edma_device);
294 }
295
296 static struct resource da8xx_i2c_resources0[] = {
297 {
298 .start = DA8XX_I2C0_BASE,
299 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
300 .flags = IORESOURCE_MEM,
301 },
302 {
303 .start = IRQ_DA8XX_I2CINT0,
304 .end = IRQ_DA8XX_I2CINT0,
305 .flags = IORESOURCE_IRQ,
306 },
307 };
308
309 static struct platform_device da8xx_i2c_device0 = {
310 .name = "i2c_davinci",
311 .id = 1,
312 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
313 .resource = da8xx_i2c_resources0,
314 };
315
316 static struct resource da8xx_i2c_resources1[] = {
317 {
318 .start = DA8XX_I2C1_BASE,
319 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 .start = IRQ_DA8XX_I2CINT1,
324 .end = IRQ_DA8XX_I2CINT1,
325 .flags = IORESOURCE_IRQ,
326 },
327 };
328
329 static struct platform_device da8xx_i2c_device1 = {
330 .name = "i2c_davinci",
331 .id = 2,
332 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
333 .resource = da8xx_i2c_resources1,
334 };
335
336 int __init da8xx_register_i2c(int instance,
337 struct davinci_i2c_platform_data *pdata)
338 {
339 struct platform_device *pdev;
340
341 if (instance == 0)
342 pdev = &da8xx_i2c_device0;
343 else if (instance == 1)
344 pdev = &da8xx_i2c_device1;
345 else
346 return -EINVAL;
347
348 pdev->dev.platform_data = pdata;
349 return platform_device_register(pdev);
350 }
351
352 static struct resource da8xx_watchdog_resources[] = {
353 {
354 .start = DA8XX_WDOG_BASE,
355 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
356 .flags = IORESOURCE_MEM,
357 },
358 };
359
360 static struct platform_device da8xx_wdt_device = {
361 .name = "davinci-wdt",
362 .id = -1,
363 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
364 .resource = da8xx_watchdog_resources,
365 };
366
367 void da8xx_restart(enum reboot_mode mode, const char *cmd)
368 {
369 struct device *dev;
370
371 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
372 if (!dev) {
373 pr_err("%s: failed to find watchdog device\n", __func__);
374 return;
375 }
376
377 davinci_watchdog_reset(to_platform_device(dev));
378 }
379
380 int __init da8xx_register_watchdog(void)
381 {
382 return platform_device_register(&da8xx_wdt_device);
383 }
384
385 static struct resource da8xx_emac_resources[] = {
386 {
387 .start = DA8XX_EMAC_CPPI_PORT_BASE,
388 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
393 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = IRQ_DA8XX_C0_RX_PULSE,
398 .end = IRQ_DA8XX_C0_RX_PULSE,
399 .flags = IORESOURCE_IRQ,
400 },
401 {
402 .start = IRQ_DA8XX_C0_TX_PULSE,
403 .end = IRQ_DA8XX_C0_TX_PULSE,
404 .flags = IORESOURCE_IRQ,
405 },
406 {
407 .start = IRQ_DA8XX_C0_MISC_PULSE,
408 .end = IRQ_DA8XX_C0_MISC_PULSE,
409 .flags = IORESOURCE_IRQ,
410 },
411 };
412
413 struct emac_platform_data da8xx_emac_pdata = {
414 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
415 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
416 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
417 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
418 .version = EMAC_VERSION_2,
419 };
420
421 static struct platform_device da8xx_emac_device = {
422 .name = "davinci_emac",
423 .id = 1,
424 .dev = {
425 .platform_data = &da8xx_emac_pdata,
426 },
427 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
428 .resource = da8xx_emac_resources,
429 };
430
431 static struct resource da8xx_mdio_resources[] = {
432 {
433 .start = DA8XX_EMAC_MDIO_BASE,
434 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
435 .flags = IORESOURCE_MEM,
436 },
437 };
438
439 static struct platform_device da8xx_mdio_device = {
440 .name = "davinci_mdio",
441 .id = 0,
442 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
443 .resource = da8xx_mdio_resources,
444 };
445
446 int __init da8xx_register_emac(void)
447 {
448 int ret;
449
450 ret = platform_device_register(&da8xx_mdio_device);
451 if (ret < 0)
452 return ret;
453
454 return platform_device_register(&da8xx_emac_device);
455 }
456
457 static struct resource da830_mcasp1_resources[] = {
458 {
459 .name = "mpu",
460 .start = DAVINCI_DA830_MCASP1_REG_BASE,
461 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
462 .flags = IORESOURCE_MEM,
463 },
464 /* TX event */
465 {
466 .name = "tx",
467 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
468 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
469 .flags = IORESOURCE_DMA,
470 },
471 /* RX event */
472 {
473 .name = "rx",
474 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
475 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
476 .flags = IORESOURCE_DMA,
477 },
478 {
479 .name = "common",
480 .start = IRQ_DA8XX_MCASPINT,
481 .flags = IORESOURCE_IRQ,
482 },
483 };
484
485 static struct platform_device da830_mcasp1_device = {
486 .name = "davinci-mcasp",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
489 .resource = da830_mcasp1_resources,
490 };
491
492 static struct resource da830_mcasp2_resources[] = {
493 {
494 .name = "mpu",
495 .start = DAVINCI_DA830_MCASP2_REG_BASE,
496 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
497 .flags = IORESOURCE_MEM,
498 },
499 /* TX event */
500 {
501 .name = "tx",
502 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
503 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
504 .flags = IORESOURCE_DMA,
505 },
506 /* RX event */
507 {
508 .name = "rx",
509 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
510 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
511 .flags = IORESOURCE_DMA,
512 },
513 {
514 .name = "common",
515 .start = IRQ_DA8XX_MCASPINT,
516 .flags = IORESOURCE_IRQ,
517 },
518 };
519
520 static struct platform_device da830_mcasp2_device = {
521 .name = "davinci-mcasp",
522 .id = 2,
523 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
524 .resource = da830_mcasp2_resources,
525 };
526
527 static struct resource da850_mcasp_resources[] = {
528 {
529 .name = "mpu",
530 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
531 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
532 .flags = IORESOURCE_MEM,
533 },
534 /* TX event */
535 {
536 .name = "tx",
537 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
538 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
539 .flags = IORESOURCE_DMA,
540 },
541 /* RX event */
542 {
543 .name = "rx",
544 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
545 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
546 .flags = IORESOURCE_DMA,
547 },
548 {
549 .name = "common",
550 .start = IRQ_DA8XX_MCASPINT,
551 .flags = IORESOURCE_IRQ,
552 },
553 };
554
555 static struct platform_device da850_mcasp_device = {
556 .name = "davinci-mcasp",
557 .id = 0,
558 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
559 .resource = da850_mcasp_resources,
560 };
561
562 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
563 {
564 struct platform_device *pdev;
565
566 switch (id) {
567 case 0:
568 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
569 pdev = &da850_mcasp_device;
570 break;
571 case 1:
572 /* Valid for DA830/OMAP-L137 only */
573 if (!cpu_is_davinci_da830())
574 return;
575 pdev = &da830_mcasp1_device;
576 break;
577 case 2:
578 /* Valid for DA830/OMAP-L137 only */
579 if (!cpu_is_davinci_da830())
580 return;
581 pdev = &da830_mcasp2_device;
582 break;
583 default:
584 return;
585 }
586
587 pdev->dev.platform_data = pdata;
588 platform_device_register(pdev);
589 }
590
591 static struct resource da8xx_pruss_resources[] = {
592 {
593 .start = DA8XX_PRUSS_MEM_BASE,
594 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
595 .flags = IORESOURCE_MEM,
596 },
597 {
598 .start = IRQ_DA8XX_EVTOUT0,
599 .end = IRQ_DA8XX_EVTOUT0,
600 .flags = IORESOURCE_IRQ,
601 },
602 {
603 .start = IRQ_DA8XX_EVTOUT1,
604 .end = IRQ_DA8XX_EVTOUT1,
605 .flags = IORESOURCE_IRQ,
606 },
607 {
608 .start = IRQ_DA8XX_EVTOUT2,
609 .end = IRQ_DA8XX_EVTOUT2,
610 .flags = IORESOURCE_IRQ,
611 },
612 {
613 .start = IRQ_DA8XX_EVTOUT3,
614 .end = IRQ_DA8XX_EVTOUT3,
615 .flags = IORESOURCE_IRQ,
616 },
617 {
618 .start = IRQ_DA8XX_EVTOUT4,
619 .end = IRQ_DA8XX_EVTOUT4,
620 .flags = IORESOURCE_IRQ,
621 },
622 {
623 .start = IRQ_DA8XX_EVTOUT5,
624 .end = IRQ_DA8XX_EVTOUT5,
625 .flags = IORESOURCE_IRQ,
626 },
627 {
628 .start = IRQ_DA8XX_EVTOUT6,
629 .end = IRQ_DA8XX_EVTOUT6,
630 .flags = IORESOURCE_IRQ,
631 },
632 {
633 .start = IRQ_DA8XX_EVTOUT7,
634 .end = IRQ_DA8XX_EVTOUT7,
635 .flags = IORESOURCE_IRQ,
636 },
637 };
638
639 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
640 .pintc_base = 0x4000,
641 };
642
643 static struct platform_device da8xx_uio_pruss_dev = {
644 .name = "pruss_uio",
645 .id = -1,
646 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
647 .resource = da8xx_pruss_resources,
648 .dev = {
649 .coherent_dma_mask = DMA_BIT_MASK(32),
650 .platform_data = &da8xx_uio_pruss_pdata,
651 }
652 };
653
654 int __init da8xx_register_uio_pruss(void)
655 {
656 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
657 return platform_device_register(&da8xx_uio_pruss_dev);
658 }
659
660 static struct lcd_ctrl_config lcd_cfg = {
661 .panel_shade = COLOR_ACTIVE,
662 .bpp = 16,
663 };
664
665 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
666 .manu_name = "sharp",
667 .controller_data = &lcd_cfg,
668 .type = "Sharp_LCD035Q3DG01",
669 };
670
671 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
672 .manu_name = "sharp",
673 .controller_data = &lcd_cfg,
674 .type = "Sharp_LK043T1DG01",
675 };
676
677 static struct resource da8xx_lcdc_resources[] = {
678 [0] = { /* registers */
679 .start = DA8XX_LCD_CNTRL_BASE,
680 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
681 .flags = IORESOURCE_MEM,
682 },
683 [1] = { /* interrupt */
684 .start = IRQ_DA8XX_LCDINT,
685 .end = IRQ_DA8XX_LCDINT,
686 .flags = IORESOURCE_IRQ,
687 },
688 };
689
690 static struct platform_device da8xx_lcdc_device = {
691 .name = "da8xx_lcdc",
692 .id = 0,
693 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
694 .resource = da8xx_lcdc_resources,
695 };
696
697 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
698 {
699 da8xx_lcdc_device.dev.platform_data = pdata;
700 return platform_device_register(&da8xx_lcdc_device);
701 }
702
703 static struct resource da8xx_gpio_resources[] = {
704 { /* registers */
705 .start = DA8XX_GPIO_BASE,
706 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
707 .flags = IORESOURCE_MEM,
708 },
709 { /* interrupt */
710 .start = IRQ_DA8XX_GPIO0,
711 .end = IRQ_DA8XX_GPIO8,
712 .flags = IORESOURCE_IRQ,
713 },
714 };
715
716 static struct platform_device da8xx_gpio_device = {
717 .name = "davinci_gpio",
718 .id = -1,
719 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
720 .resource = da8xx_gpio_resources,
721 };
722
723 int __init da8xx_register_gpio(void *pdata)
724 {
725 da8xx_gpio_device.dev.platform_data = pdata;
726 return platform_device_register(&da8xx_gpio_device);
727 }
728
729 static struct resource da8xx_mmcsd0_resources[] = {
730 { /* registers */
731 .start = DA8XX_MMCSD0_BASE,
732 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
733 .flags = IORESOURCE_MEM,
734 },
735 { /* interrupt */
736 .start = IRQ_DA8XX_MMCSDINT0,
737 .end = IRQ_DA8XX_MMCSDINT0,
738 .flags = IORESOURCE_IRQ,
739 },
740 { /* DMA RX */
741 .start = DA8XX_DMA_MMCSD0_RX,
742 .end = DA8XX_DMA_MMCSD0_RX,
743 .flags = IORESOURCE_DMA,
744 },
745 { /* DMA TX */
746 .start = DA8XX_DMA_MMCSD0_TX,
747 .end = DA8XX_DMA_MMCSD0_TX,
748 .flags = IORESOURCE_DMA,
749 },
750 };
751
752 static struct platform_device da8xx_mmcsd0_device = {
753 .name = "da830-mmc",
754 .id = 0,
755 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
756 .resource = da8xx_mmcsd0_resources,
757 };
758
759 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
760 {
761 da8xx_mmcsd0_device.dev.platform_data = config;
762 return platform_device_register(&da8xx_mmcsd0_device);
763 }
764
765 #ifdef CONFIG_ARCH_DAVINCI_DA850
766 static struct resource da850_mmcsd1_resources[] = {
767 { /* registers */
768 .start = DA850_MMCSD1_BASE,
769 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
770 .flags = IORESOURCE_MEM,
771 },
772 { /* interrupt */
773 .start = IRQ_DA850_MMCSDINT0_1,
774 .end = IRQ_DA850_MMCSDINT0_1,
775 .flags = IORESOURCE_IRQ,
776 },
777 { /* DMA RX */
778 .start = DA850_DMA_MMCSD1_RX,
779 .end = DA850_DMA_MMCSD1_RX,
780 .flags = IORESOURCE_DMA,
781 },
782 { /* DMA TX */
783 .start = DA850_DMA_MMCSD1_TX,
784 .end = DA850_DMA_MMCSD1_TX,
785 .flags = IORESOURCE_DMA,
786 },
787 };
788
789 static struct platform_device da850_mmcsd1_device = {
790 .name = "da830-mmc",
791 .id = 1,
792 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
793 .resource = da850_mmcsd1_resources,
794 };
795
796 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
797 {
798 da850_mmcsd1_device.dev.platform_data = config;
799 return platform_device_register(&da850_mmcsd1_device);
800 }
801 #endif
802
803 static struct resource da8xx_rproc_resources[] = {
804 { /* DSP boot address */
805 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
806 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
807 .flags = IORESOURCE_MEM,
808 },
809 { /* DSP interrupt registers */
810 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
811 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
812 .flags = IORESOURCE_MEM,
813 },
814 { /* dsp irq */
815 .start = IRQ_DA8XX_CHIPINT0,
816 .end = IRQ_DA8XX_CHIPINT0,
817 .flags = IORESOURCE_IRQ,
818 },
819 };
820
821 static struct platform_device da8xx_dsp = {
822 .name = "davinci-rproc",
823 .dev = {
824 .coherent_dma_mask = DMA_BIT_MASK(32),
825 },
826 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
827 .resource = da8xx_rproc_resources,
828 };
829
830 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
831
832 static phys_addr_t rproc_base __initdata;
833 static unsigned long rproc_size __initdata;
834
835 static int __init early_rproc_mem(char *p)
836 {
837 char *endp;
838
839 if (p == NULL)
840 return 0;
841
842 rproc_size = memparse(p, &endp);
843 if (*endp == '@')
844 rproc_base = memparse(endp + 1, NULL);
845
846 return 0;
847 }
848 early_param("rproc_mem", early_rproc_mem);
849
850 void __init da8xx_rproc_reserve_cma(void)
851 {
852 int ret;
853
854 if (!rproc_base || !rproc_size) {
855 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
856 " 'nn' and 'address' must both be non-zero\n",
857 __func__);
858
859 return;
860 }
861
862 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
863 __func__, rproc_size, (unsigned long)rproc_base);
864
865 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
866 if (ret)
867 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
868 }
869
870 #else
871
872 void __init da8xx_rproc_reserve_cma(void)
873 {
874 }
875
876 #endif
877
878 int __init da8xx_register_rproc(void)
879 {
880 int ret;
881
882 ret = platform_device_register(&da8xx_dsp);
883 if (ret)
884 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
885
886 return ret;
887 };
888
889 static struct resource da8xx_rtc_resources[] = {
890 {
891 .start = DA8XX_RTC_BASE,
892 .end = DA8XX_RTC_BASE + SZ_4K - 1,
893 .flags = IORESOURCE_MEM,
894 },
895 { /* timer irq */
896 .start = IRQ_DA8XX_RTC,
897 .end = IRQ_DA8XX_RTC,
898 .flags = IORESOURCE_IRQ,
899 },
900 { /* alarm irq */
901 .start = IRQ_DA8XX_RTC,
902 .end = IRQ_DA8XX_RTC,
903 .flags = IORESOURCE_IRQ,
904 },
905 };
906
907 static struct platform_device da8xx_rtc_device = {
908 .name = "da830-rtc",
909 .id = -1,
910 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
911 .resource = da8xx_rtc_resources,
912 };
913
914 int da8xx_register_rtc(void)
915 {
916 return platform_device_register(&da8xx_rtc_device);
917 }
918
919 static void __iomem *da8xx_ddr2_ctlr_base;
920 void __iomem * __init da8xx_get_mem_ctlr(void)
921 {
922 if (da8xx_ddr2_ctlr_base)
923 return da8xx_ddr2_ctlr_base;
924
925 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
926 if (!da8xx_ddr2_ctlr_base)
927 pr_warn("%s: Unable to map DDR2 controller", __func__);
928
929 return da8xx_ddr2_ctlr_base;
930 }
931
932 static struct resource da8xx_cpuidle_resources[] = {
933 {
934 .start = DA8XX_DDR2_CTL_BASE,
935 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
936 .flags = IORESOURCE_MEM,
937 },
938 };
939
940 /* DA8XX devices support DDR2 power down */
941 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
942 .ddr2_pdown = 1,
943 };
944
945
946 static struct platform_device da8xx_cpuidle_device = {
947 .name = "cpuidle-davinci",
948 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
949 .resource = da8xx_cpuidle_resources,
950 .dev = {
951 .platform_data = &da8xx_cpuidle_pdata,
952 },
953 };
954
955 int __init da8xx_register_cpuidle(void)
956 {
957 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
958
959 return platform_device_register(&da8xx_cpuidle_device);
960 }
961
962 static struct resource da8xx_spi0_resources[] = {
963 [0] = {
964 .start = DA8XX_SPI0_BASE,
965 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
966 .flags = IORESOURCE_MEM,
967 },
968 [1] = {
969 .start = IRQ_DA8XX_SPINT0,
970 .end = IRQ_DA8XX_SPINT0,
971 .flags = IORESOURCE_IRQ,
972 },
973 [2] = {
974 .start = DA8XX_DMA_SPI0_RX,
975 .end = DA8XX_DMA_SPI0_RX,
976 .flags = IORESOURCE_DMA,
977 },
978 [3] = {
979 .start = DA8XX_DMA_SPI0_TX,
980 .end = DA8XX_DMA_SPI0_TX,
981 .flags = IORESOURCE_DMA,
982 },
983 };
984
985 static struct resource da8xx_spi1_resources[] = {
986 [0] = {
987 .start = DA830_SPI1_BASE,
988 .end = DA830_SPI1_BASE + SZ_4K - 1,
989 .flags = IORESOURCE_MEM,
990 },
991 [1] = {
992 .start = IRQ_DA8XX_SPINT1,
993 .end = IRQ_DA8XX_SPINT1,
994 .flags = IORESOURCE_IRQ,
995 },
996 [2] = {
997 .start = DA8XX_DMA_SPI1_RX,
998 .end = DA8XX_DMA_SPI1_RX,
999 .flags = IORESOURCE_DMA,
1000 },
1001 [3] = {
1002 .start = DA8XX_DMA_SPI1_TX,
1003 .end = DA8XX_DMA_SPI1_TX,
1004 .flags = IORESOURCE_DMA,
1005 },
1006 };
1007
1008 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1009 [0] = {
1010 .version = SPI_VERSION_2,
1011 .intr_line = 1,
1012 .dma_event_q = EVENTQ_0,
1013 },
1014 [1] = {
1015 .version = SPI_VERSION_2,
1016 .intr_line = 1,
1017 .dma_event_q = EVENTQ_0,
1018 },
1019 };
1020
1021 static struct platform_device da8xx_spi_device[] = {
1022 [0] = {
1023 .name = "spi_davinci",
1024 .id = 0,
1025 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1026 .resource = da8xx_spi0_resources,
1027 .dev = {
1028 .platform_data = &da8xx_spi_pdata[0],
1029 },
1030 },
1031 [1] = {
1032 .name = "spi_davinci",
1033 .id = 1,
1034 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1035 .resource = da8xx_spi1_resources,
1036 .dev = {
1037 .platform_data = &da8xx_spi_pdata[1],
1038 },
1039 },
1040 };
1041
1042 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1043 {
1044 if (instance < 0 || instance > 1)
1045 return -EINVAL;
1046
1047 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1048
1049 if (instance == 1 && cpu_is_davinci_da850()) {
1050 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1051 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1052 }
1053
1054 return platform_device_register(&da8xx_spi_device[instance]);
1055 }
1056
1057 #ifdef CONFIG_ARCH_DAVINCI_DA850
1058 static struct resource da850_sata_resources[] = {
1059 {
1060 .start = DA850_SATA_BASE,
1061 .end = DA850_SATA_BASE + 0x1fff,
1062 .flags = IORESOURCE_MEM,
1063 },
1064 {
1065 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1066 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1067 .flags = IORESOURCE_MEM,
1068 },
1069 {
1070 .start = IRQ_DA850_SATAINT,
1071 .flags = IORESOURCE_IRQ,
1072 },
1073 };
1074
1075 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1076
1077 static struct platform_device da850_sata_device = {
1078 .name = "ahci_da850",
1079 .id = -1,
1080 .dev = {
1081 .dma_mask = &da850_sata_dmamask,
1082 .coherent_dma_mask = DMA_BIT_MASK(32),
1083 },
1084 .num_resources = ARRAY_SIZE(da850_sata_resources),
1085 .resource = da850_sata_resources,
1086 };
1087
1088 int __init da850_register_sata(unsigned long refclkpn)
1089 {
1090 /* please see comment in drivers/ata/ahci_da850.c */
1091 BUG_ON(refclkpn != 100 * 1000 * 1000);
1092
1093 return platform_device_register(&da850_sata_device);
1094 }
1095 #endif
Linux with added FPC-III support