arch/arm/mach-mvebu/coherency.c

   1 /*
   2  * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
   3  * platforms.
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Yehuda Yitschak <yehuday@marvell.com>
   8  * Gregory Clement <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
  16  * responsible for ensuring hardware coherency between all CPUs and between
  17  * CPUs and I/O masters. This file initializes the coherency fabric and
  18  * supplies basic routines for configuring and controlling hardware coherency
  19  */
  20
  21 #define pr_fmt(fmt) "mvebu-coherency: " fmt
  22
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/of_address.h>
  26 #include <linux/io.h>
  27 #include <linux/smp.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include <linux/mbus.h>
  32 #include <linux/pci.h>
  33 #include <asm/smp_plat.h>
  34 #include <asm/cacheflush.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/dma-mapping.h>
  37 #include "coherency.h"
  38 #include "mvebu-soc-id.h"
  39
  40 unsigned long coherency_phys_base;
  41 void __iomem *coherency_base;
  42 static void __iomem *coherency_cpu_base;
  43
  44 /* Coherency fabric registers */
  45 #define IO_SYNC_BARRIER_CTL_OFFSET                 0x0
  46
  47 enum {
  48         COHERENCY_FABRIC_TYPE_NONE,
  49         COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
  50         COHERENCY_FABRIC_TYPE_ARMADA_375,
  51         COHERENCY_FABRIC_TYPE_ARMADA_380,
  52 };
  53
  54 static const struct of_device_id of_coherency_table[] = {
  55         {.compatible = "marvell,coherency-fabric",
  56          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
  57         {.compatible = "marvell,armada-375-coherency-fabric",
  58          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
  59         {.compatible = "marvell,armada-380-coherency-fabric",
  60          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
  61         { /* end of list */ },
  62 };
  63
  64 /* Functions defined in coherency_ll.S */
  65 int ll_enable_coherency(void);
  66 void ll_add_cpu_to_smp_group(void);
  67
  68 int set_cpu_coherent(void)
  69 {
  70         if (!coherency_base) {
  71                 pr_warn("Can't make current CPU cache coherent.\n");
  72                 pr_warn("Coherency fabric is not initialized\n");
  73                 return 1;
  74         }
  75
  76         ll_add_cpu_to_smp_group();
  77         return ll_enable_coherency();
  78 }
  79
  80 static int mvebu_hwcc_notifier(struct notifier_block *nb,
  81                                unsigned long event, void *__dev)
  82 {
  83         struct device *dev = __dev;
  84
  85         if (event != BUS_NOTIFY_ADD_DEVICE)
  86                 return NOTIFY_DONE;
  87         set_dma_ops(dev, &arm_coherent_dma_ops);
  88
  89         return NOTIFY_OK;
  90 }
  91
  92 static struct notifier_block mvebu_hwcc_nb = {
  93         .notifier_call = mvebu_hwcc_notifier,
  94 };
  95
  96 static struct notifier_block mvebu_hwcc_pci_nb = {
  97         .notifier_call = mvebu_hwcc_notifier,
  98 };
  99
 100 static void __init armada_370_coherency_init(struct device_node *np)
 101 {
 102         struct resource res;
 103
 104         of_address_to_resource(np, 0, &res);
 105         coherency_phys_base = res.start;
 106         /*
 107          * Ensure secondary CPUs will see the updated value,
 108          * which they read before they join the coherency
 109          * fabric, and therefore before they are coherent with
 110          * the boot CPU cache.
 111          */
 112         sync_cache_w(&coherency_phys_base);
 113         coherency_base = of_iomap(np, 0);
 114         coherency_cpu_base = of_iomap(np, 1);
 115         set_cpu_coherent();
 116 }
 117
 118 /*
 119  * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
 120  * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
 121  * needed for the HW I/O coherency mechanism to work properly without
 122  * deadlock.
 123  */
 124 static void __iomem *
 125 armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
 126                          unsigned int mtype, void *caller)
 127 {
 128         mtype = MT_UNCACHED;
 129         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 130 }
 131
 132 static void __init armada_375_380_coherency_init(struct device_node *np)
 133 {
 134         struct device_node *cache_dn;
 135
 136         coherency_cpu_base = of_iomap(np, 0);
 137         arch_ioremap_caller = armada_wa_ioremap_caller;
 138
 139         /*
 140          * We should switch the PL310 to I/O coherency mode only if
 141          * I/O coherency is actually enabled.
 142          */
 143         if (!coherency_available())
 144                 return;
 145
 146         /*
 147          * Add the PL310 property "arm,io-coherent". This makes sure the
 148          * outer sync operation is not used, which allows to
 149          * workaround the system erratum that causes deadlocks when
 150          * doing PCIe in an SMP situation on Armada 375 and Armada
 151          * 38x.
 152          */
 153         for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
 154                 struct property *p;
 155
 156                 p = kzalloc(sizeof(*p), GFP_KERNEL);
 157                 p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
 158                 of_add_property(cache_dn, p);
 159         }
 160 }
 161
 162 static int coherency_type(void)
 163 {
 164         struct device_node *np;
 165         const struct of_device_id *match;
 166         int type;
 167
 168         /*
 169          * The coherency fabric is needed:
 170          * - For coherency between processors on Armada XP, so only
 171          *   when SMP is enabled.
 172          * - For coherency between the processor and I/O devices, but
 173          *   this coherency requires many pre-requisites (write
 174          *   allocate cache policy, shareable pages, SMP bit set) that
 175          *   are only meant in SMP situations.
 176          *
 177          * Note that this means that on Armada 370, there is currently
 178          * no way to use hardware I/O coherency, because even when
 179          * CONFIG_SMP is enabled, is_smp() returns false due to the
 180          * Armada 370 being a single-core processor. To lift this
 181          * limitation, we would have to find a way to make the cache
 182          * policy set to write-allocate (on all Armada SoCs), and to
 183          * set the shareable attribute in page tables (on all Armada
 184          * SoCs except the Armada 370). Unfortunately, such decisions
 185          * are taken very early in the kernel boot process, at a point
 186          * where we don't know yet on which SoC we are running.
 187
 188          */
 189         if (!is_smp())
 190                 return COHERENCY_FABRIC_TYPE_NONE;
 191
 192         np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
 193         if (!np)
 194                 return COHERENCY_FABRIC_TYPE_NONE;
 195
 196         type = (int) match->data;
 197
 198         of_node_put(np);
 199
 200         return type;
 201 }
 202
 203 int coherency_available(void)
 204 {
 205         return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
 206 }
 207
 208 int __init coherency_init(void)
 209 {
 210         int type = coherency_type();
 211         struct device_node *np;
 212
 213         np = of_find_matching_node(NULL, of_coherency_table);
 214
 215         if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
 216                 armada_370_coherency_init(np);
 217         else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
 218                  type == COHERENCY_FABRIC_TYPE_ARMADA_380)
 219                 armada_375_380_coherency_init(np);
 220
 221         of_node_put(np);
 222
 223         return 0;
 224 }
 225
 226 static int __init coherency_late_init(void)
 227 {
 228         if (coherency_available())
 229                 bus_register_notifier(&platform_bus_type,
 230                                       &mvebu_hwcc_nb);
 231         return 0;
 232 }
 233
 234 postcore_initcall(coherency_late_init);
 235
 236 #if IS_ENABLED(CONFIG_PCI)
 237 static int __init coherency_pci_init(void)
 238 {
 239         if (coherency_available())
 240                 bus_register_notifier(&pci_bus_type,
 241                                        &mvebu_hwcc_pci_nb);
 242         return 0;
 243 }
 244
 245 arch_initcall(coherency_pci_init);
 246 #endif