2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/clk-provider.h>
25 #include <linux/bitops.h>
26 #include <linux/regmap.h>
27 #include <linux/of_address.h>
28 #include <linux/bootmem.h>
31 #include <trace/events/power.h>
34 #include "clockdomain.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
44 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
45 * for a module to indicate that it is no longer in idle
47 #define MAX_MODULE_ENABLE_WAIT 100000
52 * Clock features setup. Used instead of CPU type checks.
54 struct ti_clk_features ti_clk_features
;
56 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
57 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000
58 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
59 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
60 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
63 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
64 * From device data manual section 4.3 "DPLL and DLL Specifications".
66 #define OMAP3PLUS_DPLL_FINT_MIN 32000
67 #define OMAP3PLUS_DPLL_FINT_MAX 52000000
70 * clkdm_control: if true, then when a clock is enabled in the
71 * hardware, its clockdomain will first be enabled; and when a clock
72 * is disabled in the hardware, its clockdomain will be disabled
75 static bool clkdm_control
= true;
77 static LIST_HEAD(clk_hw_omap_clocks
);
80 struct regmap
*regmap
;
84 static struct clk_iomap
*clk_memmaps
[CLK_MAX_MEMMAPS
];
86 static void clk_memmap_writel(u32 val
, void __iomem
*reg
)
88 struct clk_omap_reg
*r
= (struct clk_omap_reg
*)®
;
89 struct clk_iomap
*io
= clk_memmaps
[r
->index
];
92 regmap_write(io
->regmap
, r
->offset
, val
);
94 writel_relaxed(val
, io
->mem
+ r
->offset
);
97 static u32
clk_memmap_readl(void __iomem
*reg
)
100 struct clk_omap_reg
*r
= (struct clk_omap_reg
*)®
;
101 struct clk_iomap
*io
= clk_memmaps
[r
->index
];
104 regmap_read(io
->regmap
, r
->offset
, &val
);
106 val
= readl_relaxed(io
->mem
+ r
->offset
);
111 void omap2_clk_writel(u32 val
, struct clk_hw_omap
*clk
, void __iomem
*reg
)
113 if (WARN_ON_ONCE(!(clk
->flags
& MEMMAP_ADDRESSING
)))
114 writel_relaxed(val
, reg
);
116 clk_memmap_writel(val
, reg
);
119 u32
omap2_clk_readl(struct clk_hw_omap
*clk
, void __iomem
*reg
)
121 if (WARN_ON_ONCE(!(clk
->flags
& MEMMAP_ADDRESSING
)))
122 return readl_relaxed(reg
);
124 return clk_memmap_readl(reg
);
127 static struct ti_clk_ll_ops omap_clk_ll_ops
= {
128 .clk_readl
= clk_memmap_readl
,
129 .clk_writel
= clk_memmap_writel
,
133 * omap2_clk_provider_init - initialize a clock provider
134 * @match_table: DT device table to match for devices to init
135 * @np: device node pointer for the this clock provider
136 * @index: index for the clock provider
137 + @syscon: syscon regmap pointer
138 * @mem: iomem pointer for the clock provider memory area, only used if
139 * syscon is not provided
141 * Initializes a clock provider module (CM/PRM etc.), registering
142 * the memory mapping at specified index and initializing the
143 * low level driver infrastructure. Returns 0 in success.
145 int __init
omap2_clk_provider_init(struct device_node
*np
, int index
,
146 struct regmap
*syscon
, void __iomem
*mem
)
148 struct clk_iomap
*io
;
150 ti_clk_ll_ops
= &omap_clk_ll_ops
;
152 io
= kzalloc(sizeof(*io
), GFP_KERNEL
);
157 clk_memmaps
[index
] = io
;
159 ti_dt_clk_init_provider(np
, index
);
165 * omap2_clk_legacy_provider_init - initialize a legacy clock provider
166 * @index: index for the clock provider
167 * @mem: iomem pointer for the clock provider memory area
169 * Initializes a legacy clock provider memory mapping.
171 void __init
omap2_clk_legacy_provider_init(int index
, void __iomem
*mem
)
173 struct clk_iomap
*io
;
175 ti_clk_ll_ops
= &omap_clk_ll_ops
;
177 io
= memblock_virt_alloc(sizeof(*io
), 0);
181 clk_memmaps
[index
] = io
;
185 * OMAP2+ specific clock functions
188 /* Private functions */
192 * _wait_idlest_generic - wait for a module to leave the idle state
193 * @clk: module clock to wait for (needed for register offsets)
194 * @reg: virtual address of module IDLEST register
195 * @mask: value to mask against to determine if the module is active
196 * @idlest: idle state indicator (0 or 1) for the clock
197 * @name: name of the clock (for printk)
199 * Wait for a module to leave idle, where its idle-status register is
200 * not inside the CM module. Returns 1 if the module left idle
201 * promptly, or 0 if the module did not leave idle before the timeout
202 * elapsed. XXX Deprecated - should be moved into drivers for the
203 * individual IP block that the IDLEST register exists in.
205 static int _wait_idlest_generic(struct clk_hw_omap
*clk
, void __iomem
*reg
,
206 u32 mask
, u8 idlest
, const char *name
)
210 ena
= (idlest
) ? 0 : mask
;
212 omap_test_timeout(((omap2_clk_readl(clk
, reg
) & mask
) == ena
),
213 MAX_MODULE_ENABLE_WAIT
, i
);
215 if (i
< MAX_MODULE_ENABLE_WAIT
)
216 pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
219 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
220 name
, MAX_MODULE_ENABLE_WAIT
);
222 return (i
< MAX_MODULE_ENABLE_WAIT
) ? 1 : 0;
226 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
227 * @clk: struct clk * belonging to the module
229 * If the necessary clocks for the OMAP hardware IP block that
230 * corresponds to clock @clk are enabled, then wait for the module to
231 * indicate readiness (i.e., to leave IDLE). This code does not
232 * belong in the clock code and will be moved in the medium term to
233 * module-dependent code. No return value.
235 static void _omap2_module_wait_ready(struct clk_hw_omap
*clk
)
237 void __iomem
*companion_reg
, *idlest_reg
;
238 u8 other_bit
, idlest_bit
, idlest_val
, idlest_reg_id
;
242 /* Not all modules have multiple clocks that their IDLEST depends on */
243 if (clk
->ops
->find_companion
) {
244 clk
->ops
->find_companion(clk
, &companion_reg
, &other_bit
);
245 if (!(omap2_clk_readl(clk
, companion_reg
) & (1 << other_bit
)))
249 clk
->ops
->find_idlest(clk
, &idlest_reg
, &idlest_bit
, &idlest_val
);
250 r
= cm_split_idlest_reg(idlest_reg
, &prcm_mod
, &idlest_reg_id
);
252 /* IDLEST register not in the CM module */
253 _wait_idlest_generic(clk
, idlest_reg
, (1 << idlest_bit
),
254 idlest_val
, __clk_get_name(clk
->hw
.clk
));
256 omap_cm_wait_module_ready(0, prcm_mod
, idlest_reg_id
,
261 /* Public functions */
264 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
265 * @clk: OMAP clock struct ptr to use
267 * Convert a clockdomain name stored in a struct clk 'clk' into a
268 * clockdomain pointer, and save it into the struct clk. Intended to be
269 * called during clk_register(). No return value.
271 void omap2_init_clk_clkdm(struct clk_hw
*hw
)
273 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
274 struct clockdomain
*clkdm
;
275 const char *clk_name
;
277 if (!clk
->clkdm_name
)
280 clk_name
= __clk_get_name(hw
->clk
);
282 clkdm
= clkdm_lookup(clk
->clkdm_name
);
284 pr_debug("clock: associated clk %s to clkdm %s\n",
285 clk_name
, clk
->clkdm_name
);
288 pr_debug("clock: could not associate clk %s to clkdm %s\n",
289 clk_name
, clk
->clkdm_name
);
294 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
296 * Prevent the OMAP clock code from calling into the clockdomain code
297 * when a hardware clock in that clockdomain is enabled or disabled.
298 * Intended to be called at init time from omap*_clk_init(). No
301 void __init
omap2_clk_disable_clkdm_control(void)
303 clkdm_control
= false;
307 * omap2_clk_dflt_find_companion - find companion clock to @clk
308 * @clk: struct clk * to find the companion clock of
309 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
310 * @other_bit: u8 ** to return the companion clock bit shift in
312 * Note: We don't need special code here for INVERT_ENABLE for the
313 * time being since INVERT_ENABLE only applies to clocks enabled by
316 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
317 * just a matter of XORing the bits.
319 * Some clocks don't have companion clocks. For example, modules with
320 * only an interface clock (such as MAILBOXES) don't have a companion
321 * clock. Right now, this code relies on the hardware exporting a bit
322 * in the correct companion register that indicates that the
323 * nonexistent 'companion clock' is active. Future patches will
324 * associate this type of code with per-module data structures to
325 * avoid this issue, and remove the casts. No return value.
327 void omap2_clk_dflt_find_companion(struct clk_hw_omap
*clk
,
328 void __iomem
**other_reg
, u8
*other_bit
)
333 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
334 * it's just a matter of XORing the bits.
336 r
= ((__force u32
)clk
->enable_reg
^ (CM_FCLKEN
^ CM_ICLKEN
));
338 *other_reg
= (__force
void __iomem
*)r
;
339 *other_bit
= clk
->enable_bit
;
343 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
344 * @clk: struct clk * to find IDLEST info for
345 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
346 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
347 * @idlest_val: u8 * to return the idle status indicator
349 * Return the CM_IDLEST register address and bit shift corresponding
350 * to the module that "owns" this clock. This default code assumes
351 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
352 * the IDLEST register address ID corresponds to the CM_*CLKEN
353 * register address ID (e.g., that CM_FCLKEN2 corresponds to
354 * CM_IDLEST2). This is not true for all modules. No return value.
356 void omap2_clk_dflt_find_idlest(struct clk_hw_omap
*clk
,
357 void __iomem
**idlest_reg
, u8
*idlest_bit
, u8
*idlest_val
)
361 r
= (((__force u32
)clk
->enable_reg
& ~0xf0) | 0x20);
362 *idlest_reg
= (__force
void __iomem
*)r
;
363 *idlest_bit
= clk
->enable_bit
;
366 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
367 * 34xx reverses this, just to keep us on our toes
368 * AM35xx uses both, depending on the module.
370 *idlest_val
= ti_clk_features
.cm_idlest_val
;
374 * omap2_dflt_clk_enable - enable a clock in the hardware
375 * @hw: struct clk_hw * of the clock to enable
377 * Enable the clock @hw in the hardware. We first call into the OMAP
378 * clockdomain code to "enable" the corresponding clockdomain if this
379 * is the first enabled user of the clockdomain. Then program the
380 * hardware to enable the clock. Then wait for the IP block that uses
381 * this clock to leave idle (if applicable). Returns the error value
382 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
383 * if @hw has a null clock enable_reg, or zero upon success.
385 int omap2_dflt_clk_enable(struct clk_hw
*hw
)
387 struct clk_hw_omap
*clk
;
391 clk
= to_clk_hw_omap(hw
);
393 if (clkdm_control
&& clk
->clkdm
) {
394 ret
= clkdm_clk_enable(clk
->clkdm
, hw
->clk
);
396 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
397 __func__
, __clk_get_name(hw
->clk
),
398 clk
->clkdm
->name
, ret
);
403 if (unlikely(clk
->enable_reg
== NULL
)) {
404 pr_err("%s: %s missing enable_reg\n", __func__
,
405 __clk_get_name(hw
->clk
));
410 /* FIXME should not have INVERT_ENABLE bit here */
411 v
= omap2_clk_readl(clk
, clk
->enable_reg
);
412 if (clk
->flags
& INVERT_ENABLE
)
413 v
&= ~(1 << clk
->enable_bit
);
415 v
|= (1 << clk
->enable_bit
);
416 omap2_clk_writel(v
, clk
, clk
->enable_reg
);
417 v
= omap2_clk_readl(clk
, clk
->enable_reg
); /* OCP barrier */
419 if (clk
->ops
&& clk
->ops
->find_idlest
)
420 _omap2_module_wait_ready(clk
);
425 if (clkdm_control
&& clk
->clkdm
)
426 clkdm_clk_disable(clk
->clkdm
, hw
->clk
);
431 * omap2_dflt_clk_disable - disable a clock in the hardware
432 * @hw: struct clk_hw * of the clock to disable
434 * Disable the clock @hw in the hardware, and call into the OMAP
435 * clockdomain code to "disable" the corresponding clockdomain if all
436 * clocks/hwmods in that clockdomain are now disabled. No return
439 void omap2_dflt_clk_disable(struct clk_hw
*hw
)
441 struct clk_hw_omap
*clk
;
444 clk
= to_clk_hw_omap(hw
);
445 if (!clk
->enable_reg
) {
447 * 'independent' here refers to a clock which is not
448 * controlled by its parent.
450 pr_err("%s: independent clock %s has no enable_reg\n",
451 __func__
, __clk_get_name(hw
->clk
));
455 v
= omap2_clk_readl(clk
, clk
->enable_reg
);
456 if (clk
->flags
& INVERT_ENABLE
)
457 v
|= (1 << clk
->enable_bit
);
459 v
&= ~(1 << clk
->enable_bit
);
460 omap2_clk_writel(v
, clk
, clk
->enable_reg
);
461 /* No OCP barrier needed here since it is a disable operation */
463 if (clkdm_control
&& clk
->clkdm
)
464 clkdm_clk_disable(clk
->clkdm
, hw
->clk
);
468 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
469 * @hw: struct clk_hw * of the clock being enabled
471 * Increment the usecount of the clockdomain of the clock pointed to
472 * by @hw; if the usecount is 1, the clockdomain will be "enabled."
473 * Only needed for clocks that don't use omap2_dflt_clk_enable() as
474 * their enable function pointer. Passes along the return value of
475 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
476 * clockdomain, or 0 if clock framework-based clockdomain control is
479 int omap2_clkops_enable_clkdm(struct clk_hw
*hw
)
481 struct clk_hw_omap
*clk
;
484 clk
= to_clk_hw_omap(hw
);
486 if (unlikely(!clk
->clkdm
)) {
487 pr_err("%s: %s: no clkdm set ?!\n", __func__
,
488 __clk_get_name(hw
->clk
));
492 if (unlikely(clk
->enable_reg
))
493 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__
,
494 __clk_get_name(hw
->clk
));
496 if (!clkdm_control
) {
497 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
498 __func__
, __clk_get_name(hw
->clk
));
502 ret
= clkdm_clk_enable(clk
->clkdm
, hw
->clk
);
503 WARN(ret
, "%s: could not enable %s's clockdomain %s: %d\n",
504 __func__
, __clk_get_name(hw
->clk
), clk
->clkdm
->name
, ret
);
510 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
511 * @hw: struct clk_hw * of the clock being disabled
513 * Decrement the usecount of the clockdomain of the clock pointed to
514 * by @hw; if the usecount is 0, the clockdomain will be "disabled."
515 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
516 * disable function pointer. No return value.
518 void omap2_clkops_disable_clkdm(struct clk_hw
*hw
)
520 struct clk_hw_omap
*clk
;
522 clk
= to_clk_hw_omap(hw
);
524 if (unlikely(!clk
->clkdm
)) {
525 pr_err("%s: %s: no clkdm set ?!\n", __func__
,
526 __clk_get_name(hw
->clk
));
530 if (unlikely(clk
->enable_reg
))
531 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__
,
532 __clk_get_name(hw
->clk
));
534 if (!clkdm_control
) {
535 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
536 __func__
, __clk_get_name(hw
->clk
));
540 clkdm_clk_disable(clk
->clkdm
, hw
->clk
);
544 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
545 * @hw: struct clk_hw * to check
547 * Return 1 if the clock represented by @hw is enabled in the
548 * hardware, or 0 otherwise. Intended for use in the struct
549 * clk_ops.is_enabled function pointer.
551 int omap2_dflt_clk_is_enabled(struct clk_hw
*hw
)
553 struct clk_hw_omap
*clk
= to_clk_hw_omap(hw
);
556 v
= omap2_clk_readl(clk
, clk
->enable_reg
);
558 if (clk
->flags
& INVERT_ENABLE
)
559 v
^= BIT(clk
->enable_bit
);
561 v
&= BIT(clk
->enable_bit
);
566 static int __initdata mpurate
;
569 * By default we use the rate set by the bootloader.
570 * You can override this with mpurate= cmdline option.
572 static int __init
omap_clk_setup(char *str
)
574 get_option(&str
, &mpurate
);
584 __setup("mpurate=", omap_clk_setup
);
587 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
588 * @clk: struct clk * to initialize
590 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used
591 * temporarily for autoidle handling, until this support can be
592 * integrated into the common clock framework code in some way. No
595 void omap2_init_clk_hw_omap_clocks(struct clk
*clk
)
597 struct clk_hw_omap
*c
;
599 if (__clk_get_flags(clk
) & CLK_IS_BASIC
)
602 c
= to_clk_hw_omap(__clk_get_hw(clk
));
603 list_add(&c
->node
, &clk_hw_omap_clocks
);
607 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
610 * Enable clock autoidle on all OMAP clocks that have allow_idle
611 * function pointers associated with them. This function is intended
612 * to be temporary until support for this is added to the common clock
615 int omap2_clk_enable_autoidle_all(void)
617 struct clk_hw_omap
*c
;
619 list_for_each_entry(c
, &clk_hw_omap_clocks
, node
)
620 if (c
->ops
&& c
->ops
->allow_idle
)
621 c
->ops
->allow_idle(c
);
623 of_ti_clk_allow_autoidle_all();
629 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
632 * Disable clock autoidle on all OMAP clocks that have allow_idle
633 * function pointers associated with them. This function is intended
634 * to be temporary until support for this is added to the common clock
637 int omap2_clk_disable_autoidle_all(void)
639 struct clk_hw_omap
*c
;
641 list_for_each_entry(c
, &clk_hw_omap_clocks
, node
)
642 if (c
->ops
&& c
->ops
->deny_idle
)
643 c
->ops
->deny_idle(c
);
645 of_ti_clk_deny_autoidle_all();
651 * omap2_clk_deny_idle - disable autoidle on an OMAP clock
652 * @clk: struct clk * to disable autoidle for
654 * Disable autoidle on an OMAP clock.
656 int omap2_clk_deny_idle(struct clk
*clk
)
658 struct clk_hw_omap
*c
;
660 if (__clk_get_flags(clk
) & CLK_IS_BASIC
)
663 c
= to_clk_hw_omap(__clk_get_hw(clk
));
664 if (c
->ops
&& c
->ops
->deny_idle
)
665 c
->ops
->deny_idle(c
);
670 * omap2_clk_allow_idle - enable autoidle on an OMAP clock
671 * @clk: struct clk * to enable autoidle for
673 * Enable autoidle on an OMAP clock.
675 int omap2_clk_allow_idle(struct clk
*clk
)
677 struct clk_hw_omap
*c
;
679 if (__clk_get_flags(clk
) & CLK_IS_BASIC
)
682 c
= to_clk_hw_omap(__clk_get_hw(clk
));
683 if (c
->ops
&& c
->ops
->allow_idle
)
684 c
->ops
->allow_idle(c
);
689 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
690 * @clk_names: ptr to an array of strings of clock names to enable
691 * @num_clocks: number of clock names in @clk_names
693 * Prepare and enable a list of clocks, named by @clk_names. No
694 * return value. XXX Deprecated; only needed until these clocks are
695 * properly claimed and enabled by the drivers or core code that uses
696 * them. XXX What code disables & calls clk_put on these clocks?
698 void omap2_clk_enable_init_clocks(const char **clk_names
, u8 num_clocks
)
700 struct clk
*init_clk
;
703 for (i
= 0; i
< num_clocks
; i
++) {
704 init_clk
= clk_get(NULL
, clk_names
[i
]);
705 if (WARN(IS_ERR(init_clk
), "could not find init clock %s\n",
708 clk_prepare_enable(init_clk
);
712 const struct clk_hw_omap_ops clkhwops_wait
= {
713 .find_idlest
= omap2_clk_dflt_find_idlest
,
714 .find_companion
= omap2_clk_dflt_find_companion
,
718 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
719 * @mpurate_ck_name: clk name of the clock to change rate
721 * Change the ARM MPU clock rate to the rate specified on the command
722 * line, if one was specified. @mpurate_ck_name should be
723 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
724 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
725 * handled by the virt_prcm_set clock, but this should be handled by
726 * the OPP layer. XXX This is intended to be handled by the OPP layer
727 * code in the near future and should be removed from the clock code.
728 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
729 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
730 * cannot be found, or 0 upon success.
732 int __init
omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name
)
734 struct clk
*mpurate_ck
;
740 mpurate_ck
= clk_get(NULL
, mpurate_ck_name
);
741 if (WARN(IS_ERR(mpurate_ck
), "Failed to get %s.\n", mpurate_ck_name
))
744 r
= clk_set_rate(mpurate_ck
, mpurate
);
746 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
747 mpurate_ck_name
, mpurate
, r
);
759 * omap2_clk_print_new_rates - print summary of current clock tree rates
760 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
761 * @core_ck_name: clk name for the on-chip CORE_CLK
762 * @mpu_ck_name: clk name for the ARM MPU clock
764 * Prints a short message to the console with the HFCLKIN oscillator
765 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
766 * Called by the boot-time MPU rate switching code. XXX This is intended
767 * to be handled by the OPP layer code in the near future and should be
768 * removed from the clock code. No return value.
770 void __init
omap2_clk_print_new_rates(const char *hfclkin_ck_name
,
771 const char *core_ck_name
,
772 const char *mpu_ck_name
)
774 struct clk
*hfclkin_ck
, *core_ck
, *mpu_ck
;
775 unsigned long hfclkin_rate
;
777 mpu_ck
= clk_get(NULL
, mpu_ck_name
);
778 if (WARN(IS_ERR(mpu_ck
), "clock: failed to get %s.\n", mpu_ck_name
))
781 core_ck
= clk_get(NULL
, core_ck_name
);
782 if (WARN(IS_ERR(core_ck
), "clock: failed to get %s.\n", core_ck_name
))
785 hfclkin_ck
= clk_get(NULL
, hfclkin_ck_name
);
786 if (WARN(IS_ERR(hfclkin_ck
), "Failed to get %s.\n", hfclkin_ck_name
))
789 hfclkin_rate
= clk_get_rate(hfclkin_ck
);
791 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
792 (hfclkin_rate
/ 1000000), ((hfclkin_rate
/ 100000) % 10),
793 (clk_get_rate(core_ck
) / 1000000),
794 (clk_get_rate(mpu_ck
) / 1000000));
798 * ti_clk_init_features - init clock features struct for the SoC
800 * Initializes the clock features struct based on the SoC type.
802 void __init
ti_clk_init_features(void)
804 /* Fint setup for DPLLs */
805 if (cpu_is_omap3430()) {
806 ti_clk_features
.fint_min
= OMAP3430_DPLL_FINT_BAND1_MIN
;
807 ti_clk_features
.fint_max
= OMAP3430_DPLL_FINT_BAND2_MAX
;
808 ti_clk_features
.fint_band1_max
= OMAP3430_DPLL_FINT_BAND1_MAX
;
809 ti_clk_features
.fint_band2_min
= OMAP3430_DPLL_FINT_BAND2_MIN
;
811 ti_clk_features
.fint_min
= OMAP3PLUS_DPLL_FINT_MIN
;
812 ti_clk_features
.fint_max
= OMAP3PLUS_DPLL_FINT_MAX
;
815 /* Bypass value setup for DPLLs */
816 if (cpu_is_omap24xx()) {
817 ti_clk_features
.dpll_bypass_vals
|=
818 (1 << OMAP2XXX_EN_DPLL_LPBYPASS
) |
819 (1 << OMAP2XXX_EN_DPLL_FRBYPASS
);
820 } else if (cpu_is_omap34xx()) {
821 ti_clk_features
.dpll_bypass_vals
|=
822 (1 << OMAP3XXX_EN_DPLL_LPBYPASS
) |
823 (1 << OMAP3XXX_EN_DPLL_FRBYPASS
);
824 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
825 soc_is_omap54xx() || soc_is_dra7xx()) {
826 ti_clk_features
.dpll_bypass_vals
|=
827 (1 << OMAP4XXX_EN_DPLL_LPBYPASS
) |
828 (1 << OMAP4XXX_EN_DPLL_FRBYPASS
) |
829 (1 << OMAP4XXX_EN_DPLL_MNBYPASS
);
832 /* Jitter correction only available on OMAP343X */
833 if (cpu_is_omap343x())
834 ti_clk_features
.flags
|= TI_CLK_DPLL_HAS_FREQSEL
;
836 /* Idlest value for interface clocks.
837 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
838 * 34xx reverses this, just to keep us on our toes
839 * AM35xx uses both, depending on the module.
841 if (cpu_is_omap24xx())
842 ti_clk_features
.cm_idlest_val
= OMAP24XX_CM_IDLEST_VAL
;
843 else if (cpu_is_omap34xx())
844 ti_clk_features
.cm_idlest_val
= OMAP34XX_CM_IDLEST_VAL
;
846 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
847 if (omap_rev() == OMAP3430_REV_ES1_0
)
848 ti_clk_features
.flags
|= TI_CLK_DPLL4_DENY_REPROGRAM
;