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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / arch / mips / include / asm / mach-au1x00 / gpio-au1000.h
blob9785e4ebb450f662c6a8da940decf4969cd63aec
1 /*
2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
3 *
4 * Copyright (c) 2009 Manuel Lauss.
5 *
6 * Licensed under the terms outlined in the file COPYING.
7 */
8
9 #ifndef _ALCHEMY_GPIO_AU1000_H_
10 #define _ALCHEMY_GPIO_AU1000_H_
11
12 #include <asm/mach-au1x00/au1000.h>
13
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
16 */
17 #define ALCHEMY_GPIO1_BASE 0
18 #define ALCHEMY_GPIO2_BASE 200
19
20 #define ALCHEMY_GPIO1_NUM 32
21 #define ALCHEMY_GPIO2_NUM 16
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
24
25 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26
27 /* GPIO1 registers within SYS_ area */
28 #define AU1000_SYS_TRIOUTRD 0x100
29 #define AU1000_SYS_TRIOUTCLR 0x100
30 #define AU1000_SYS_OUTPUTRD 0x108
31 #define AU1000_SYS_OUTPUTSET 0x108
32 #define AU1000_SYS_OUTPUTCLR 0x10C
33 #define AU1000_SYS_PINSTATERD 0x110
34 #define AU1000_SYS_PININPUTEN 0x110
35
36 /* register offsets within GPIO2 block */
37 #define AU1000_GPIO2_DIR 0x00
38 #define AU1000_GPIO2_OUTPUT 0x08
39 #define AU1000_GPIO2_PINSTATE 0x0C
40 #define AU1000_GPIO2_INTENABLE 0x10
41 #define AU1000_GPIO2_ENABLE 0x14
42
43 struct gpio;
44
45 static inline int au1000_gpio1_to_irq(int gpio)
46 {
47 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
48 }
49
50 static inline int au1000_gpio2_to_irq(int gpio)
51 {
52 return -ENXIO;
53 }
54
55 static inline int au1000_irq_to_gpio(int irq)
56 {
57 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
58 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
59
60 return -ENXIO;
61 }
62
63 static inline int au1500_gpio1_to_irq(int gpio)
64 {
65 gpio -= ALCHEMY_GPIO1_BASE;
66
67 switch (gpio) {
68 case 0 ... 15:
69 case 20:
70 case 23 ... 28: return MAKE_IRQ(1, gpio);
71 }
72
73 return -ENXIO;
74 }
75
76 static inline int au1500_gpio2_to_irq(int gpio)
77 {
78 gpio -= ALCHEMY_GPIO2_BASE;
79
80 switch (gpio) {
81 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
82 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
83 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
84 }
85
86 return -ENXIO;
87 }
88
89 static inline int au1500_irq_to_gpio(int irq)
90 {
91 switch (irq) {
92 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
93 case AU1500_GPIO20_INT:
94 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
95 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
96 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
97 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
98 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
99 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
100 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
101 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
102 case AU1500_GPIO208_215_INT:
103 return ALCHEMY_GPIO2_BASE + 8;
104 }
105
106 return -ENXIO;
107 }
108
109 static inline int au1100_gpio1_to_irq(int gpio)
110 {
111 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
112 }
113
114 static inline int au1100_gpio2_to_irq(int gpio)
115 {
116 gpio -= ALCHEMY_GPIO2_BASE;
117
118 if ((gpio >= 8) && (gpio <= 15))
119 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
120
121 return -ENXIO;
122 }
123
124 static inline int au1100_irq_to_gpio(int irq)
125 {
126 switch (irq) {
127 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
128 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
129 case AU1100_GPIO208_215_INT:
130 return ALCHEMY_GPIO2_BASE + 8;
131 }
132
133 return -ENXIO;
134 }
135
136 static inline int au1550_gpio1_to_irq(int gpio)
137 {
138 gpio -= ALCHEMY_GPIO1_BASE;
139
140 switch (gpio) {
141 case 0 ... 15:
142 case 20 ... 28: return MAKE_IRQ(1, gpio);
143 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
144 }
145
146 return -ENXIO;
147 }
148
149 static inline int au1550_gpio2_to_irq(int gpio)
150 {
151 gpio -= ALCHEMY_GPIO2_BASE;
152
153 switch (gpio) {
154 case 0: return MAKE_IRQ(1, 16);
155 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
156 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
157 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
158 }
159
160 return -ENXIO;
161 }
162
163 static inline int au1550_irq_to_gpio(int irq)
164 {
165 switch (irq) {
166 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
167 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
168 case AU1550_GPIO200_INT:
169 case AU1550_GPIO201_205_INT:
170 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
171 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
172 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
173 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
174 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
175 }
176
177 return -ENXIO;
178 }
179
180 static inline int au1200_gpio1_to_irq(int gpio)
181 {
182 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
183 }
184
185 static inline int au1200_gpio2_to_irq(int gpio)
186 {
187 gpio -= ALCHEMY_GPIO2_BASE;
188
189 switch (gpio) {
190 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
191 case 3: return MAKE_IRQ(0, 22);
192 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
193 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
194 }
195
196 return -ENXIO;
197 }
198
199 static inline int au1200_irq_to_gpio(int irq)
200 {
201 switch (irq) {
202 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
203 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
204 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
205 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
206 case AU1200_GPIO203_INT:
207 return ALCHEMY_GPIO2_BASE + 3;
208 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
209 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
210 }
211
212 return -ENXIO;
213 }
214
215 /*
216 * GPIO1 block macros for common linux gpio functions.
217 */
218 static inline void alchemy_gpio1_set_value(int gpio, int v)
219 {
220 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
221 unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
222 alchemy_wrsys(mask, r);
223 }
224
225 static inline int alchemy_gpio1_get_value(int gpio)
226 {
227 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
228 return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
229 }
230
231 static inline int alchemy_gpio1_direction_input(int gpio)
232 {
233 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
234 alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
235 return 0;
236 }
237
238 static inline int alchemy_gpio1_direction_output(int gpio, int v)
239 {
240 /* hardware switches to "output" mode when one of the two
241 * "set_value" registers is accessed.
242 */
243 alchemy_gpio1_set_value(gpio, v);
244 return 0;
245 }
246
247 static inline int alchemy_gpio1_is_valid(int gpio)
248 {
249 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
250 }
251
252 static inline int alchemy_gpio1_to_irq(int gpio)
253 {
254 switch (alchemy_get_cputype()) {
255 case ALCHEMY_CPU_AU1000:
256 return au1000_gpio1_to_irq(gpio);
257 case ALCHEMY_CPU_AU1100:
258 return au1100_gpio1_to_irq(gpio);
259 case ALCHEMY_CPU_AU1500:
260 return au1500_gpio1_to_irq(gpio);
261 case ALCHEMY_CPU_AU1550:
262 return au1550_gpio1_to_irq(gpio);
263 case ALCHEMY_CPU_AU1200:
264 return au1200_gpio1_to_irq(gpio);
265 }
266 return -ENXIO;
267 }
268
269 /*
270 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
271 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
272 */
273 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
274 {
275 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
276 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
277 unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
278
279 if (to_out)
280 d |= mask;
281 else
282 d &= ~mask;
283 __raw_writel(d, base + AU1000_GPIO2_DIR);
284 wmb();
285 }
286
287 static inline void alchemy_gpio2_set_value(int gpio, int v)
288 {
289 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
290 unsigned long mask;
291 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
292 __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
293 wmb();
294 }
295
296 static inline int alchemy_gpio2_get_value(int gpio)
297 {
298 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
299 return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
300 (1 << (gpio - ALCHEMY_GPIO2_BASE));
301 }
302
303 static inline int alchemy_gpio2_direction_input(int gpio)
304 {
305 unsigned long flags;
306 local_irq_save(flags);
307 __alchemy_gpio2_mod_dir(gpio, 0);
308 local_irq_restore(flags);
309 return 0;
310 }
311
312 static inline int alchemy_gpio2_direction_output(int gpio, int v)
313 {
314 unsigned long flags;
315 alchemy_gpio2_set_value(gpio, v);
316 local_irq_save(flags);
317 __alchemy_gpio2_mod_dir(gpio, 1);
318 local_irq_restore(flags);
319 return 0;
320 }
321
322 static inline int alchemy_gpio2_is_valid(int gpio)
323 {
324 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
325 }
326
327 static inline int alchemy_gpio2_to_irq(int gpio)
328 {
329 switch (alchemy_get_cputype()) {
330 case ALCHEMY_CPU_AU1000:
331 return au1000_gpio2_to_irq(gpio);
332 case ALCHEMY_CPU_AU1100:
333 return au1100_gpio2_to_irq(gpio);
334 case ALCHEMY_CPU_AU1500:
335 return au1500_gpio2_to_irq(gpio);
336 case ALCHEMY_CPU_AU1550:
337 return au1550_gpio2_to_irq(gpio);
338 case ALCHEMY_CPU_AU1200:
339 return au1200_gpio2_to_irq(gpio);
340 }
341 return -ENXIO;
342 }
343
344 /**********************************************************************/
345
346 /* GPIO2 shared interrupts and control */
347
348 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
349 {
350 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
351 unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
352 if (en)
353 r |= 1 << gpio2;
354 else
355 r &= ~(1 << gpio2);
356 __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
357 wmb();
358 }
359
360 /**
361 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
362 * @gpio2: The GPIO2 pin to activate (200...215).
363 *
364 * GPIO208-215 have one shared interrupt line to the INTC. They are
365 * and'ed with a per-pin enable bit and finally or'ed together to form
366 * a single irq request (useful for active-high sources).
367 * With this function, a pins' individual contribution to the int request
368 * can be enabled. As with all other GPIO-based interrupts, the INTC
369 * must be programmed to accept the GPIO208_215 interrupt as well.
370 *
371 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
372 * GPIO2-based interrupts have their own request to the INTC. Please
373 * consult your Alchemy databook for more information!
374 *
375 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
376 * line to the INTC, GPIO201_205. This function can be used for those
377 * as well.
378 *
379 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
380 * (200-215 by default). No sanity checks are made,
381 */
382 static inline void alchemy_gpio2_enable_int(int gpio2)
383 {
384 unsigned long flags;
385
386 gpio2 -= ALCHEMY_GPIO2_BASE;
387
388 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
389 switch (alchemy_get_cputype()) {
390 case ALCHEMY_CPU_AU1100:
391 case ALCHEMY_CPU_AU1500:
392 gpio2 -= 8;
393 }
394
395 local_irq_save(flags);
396 __alchemy_gpio2_mod_int(gpio2, 1);
397 local_irq_restore(flags);
398 }
399
400 /**
401 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
402 * @gpio2: The GPIO2 pin to activate (200...215).
403 *
404 * see function alchemy_gpio2_enable_int() for more information.
405 */
406 static inline void alchemy_gpio2_disable_int(int gpio2)
407 {
408 unsigned long flags;
409
410 gpio2 -= ALCHEMY_GPIO2_BASE;
411
412 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
413 switch (alchemy_get_cputype()) {
414 case ALCHEMY_CPU_AU1100:
415 case ALCHEMY_CPU_AU1500:
416 gpio2 -= 8;
417 }
418
419 local_irq_save(flags);
420 __alchemy_gpio2_mod_int(gpio2, 0);
421 local_irq_restore(flags);
422 }
423
424 /**
425 * alchemy_gpio2_enable - Activate GPIO2 block.
426 *
427 * The GPIO2 block must be enabled excplicitly to work. On systems
428 * where this isn't done by the bootloader, this macro can be used.
429 */
430 static inline void alchemy_gpio2_enable(void)
431 {
432 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
433 __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */
434 wmb();
435 __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */
436 wmb();
437 }
438
439 /**
440 * alchemy_gpio2_disable - disable GPIO2 block.
441 *
442 * Disable and put GPIO2 block in low-power mode.
443 */
444 static inline void alchemy_gpio2_disable(void)
445 {
446 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
447 __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */
448 wmb();
449 }
450
451 /**********************************************************************/
452
453 /* wrappers for on-chip gpios; can be used before gpio chips have been
454 * registered with gpiolib.
455 */
456 static inline int alchemy_gpio_direction_input(int gpio)
457 {
458 return (gpio >= ALCHEMY_GPIO2_BASE) ?
459 alchemy_gpio2_direction_input(gpio) :
460 alchemy_gpio1_direction_input(gpio);
461 }
462
463 static inline int alchemy_gpio_direction_output(int gpio, int v)
464 {
465 return (gpio >= ALCHEMY_GPIO2_BASE) ?
466 alchemy_gpio2_direction_output(gpio, v) :
467 alchemy_gpio1_direction_output(gpio, v);
468 }
469
470 static inline int alchemy_gpio_get_value(int gpio)
471 {
472 return (gpio >= ALCHEMY_GPIO2_BASE) ?
473 alchemy_gpio2_get_value(gpio) :
474 alchemy_gpio1_get_value(gpio);
475 }
476
477 static inline void alchemy_gpio_set_value(int gpio, int v)
478 {
479 if (gpio >= ALCHEMY_GPIO2_BASE)
480 alchemy_gpio2_set_value(gpio, v);
481 else
482 alchemy_gpio1_set_value(gpio, v);
483 }
484
485 static inline int alchemy_gpio_is_valid(int gpio)
486 {
487 return (gpio >= ALCHEMY_GPIO2_BASE) ?
488 alchemy_gpio2_is_valid(gpio) :
489 alchemy_gpio1_is_valid(gpio);
490 }
491
492 static inline int alchemy_gpio_cansleep(int gpio)
493 {
494 return 0; /* Alchemy never gets tired */
495 }
496
497 static inline int alchemy_gpio_to_irq(int gpio)
498 {
499 return (gpio >= ALCHEMY_GPIO2_BASE) ?
500 alchemy_gpio2_to_irq(gpio) :
501 alchemy_gpio1_to_irq(gpio);
502 }
503
504 static inline int alchemy_irq_to_gpio(int irq)
505 {
506 switch (alchemy_get_cputype()) {
507 case ALCHEMY_CPU_AU1000:
508 return au1000_irq_to_gpio(irq);
509 case ALCHEMY_CPU_AU1100:
510 return au1100_irq_to_gpio(irq);
511 case ALCHEMY_CPU_AU1500:
512 return au1500_irq_to_gpio(irq);
513 case ALCHEMY_CPU_AU1550:
514 return au1550_irq_to_gpio(irq);
515 case ALCHEMY_CPU_AU1200:
516 return au1200_irq_to_gpio(irq);
517 }
518 return -ENXIO;
519 }
520
521 /**********************************************************************/
522
523 /* Linux gpio framework integration.
524 *
525 * 4 use cases of Au1000-Au1200 GPIOS:
526 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
527 * Board must register gpiochips.
528 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
529 * 2 (1 for Au1000) gpio_chips are registered.
530 *
531 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
532 * the boards' gpio.h must provide the linux gpio wrapper functions,
533 *
534 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
535 * inlinable gpio functions are provided which enable access to the
536 * Au1000 gpios only by using the numbers straight out of the data-
537 * sheets.
538
539 * Cases 1 and 3 are intended for boards which want to provide their own
540 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
541 * which are in part provided by spare Au1000 GPIO pins and in part by
542 * an external FPGA but you still want them to be accssible in linux
543 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
544 * as required).
545 */
546
547 #ifndef CONFIG_GPIOLIB
548
549 #ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
550
551 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
552
553 static inline int gpio_direction_input(int gpio)
554 {
555 return alchemy_gpio_direction_input(gpio);
556 }
557
558 static inline int gpio_direction_output(int gpio, int v)
559 {
560 return alchemy_gpio_direction_output(gpio, v);
561 }
562
563 static inline int gpio_get_value(int gpio)
564 {
565 return alchemy_gpio_get_value(gpio);
566 }
567
568 static inline void gpio_set_value(int gpio, int v)
569 {
570 alchemy_gpio_set_value(gpio, v);
571 }
572
573 static inline int gpio_get_value_cansleep(unsigned gpio)
574 {
575 return gpio_get_value(gpio);
576 }
577
578 static inline void gpio_set_value_cansleep(unsigned gpio, int value)
579 {
580 gpio_set_value(gpio, value);
581 }
582
583 static inline int gpio_is_valid(int gpio)
584 {
585 return alchemy_gpio_is_valid(gpio);
586 }
587
588 static inline int gpio_cansleep(int gpio)
589 {
590 return alchemy_gpio_cansleep(gpio);
591 }
592
593 static inline int gpio_to_irq(int gpio)
594 {
595 return alchemy_gpio_to_irq(gpio);
596 }
597
598 static inline int irq_to_gpio(int irq)
599 {
600 return alchemy_irq_to_gpio(irq);
601 }
602
603 static inline int gpio_request(unsigned gpio, const char *label)
604 {
605 return 0;
606 }
607
608 static inline int gpio_request_one(unsigned gpio,
609 unsigned long flags, const char *label)
610 {
611 return 0;
612 }
613
614 static inline int gpio_request_array(struct gpio *array, size_t num)
615 {
616 return 0;
617 }
618
619 static inline void gpio_free(unsigned gpio)
620 {
621 }
622
623 static inline void gpio_free_array(struct gpio *array, size_t num)
624 {
625 }
626
627 static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
628 {
629 return -ENOSYS;
630 }
631
632 static inline int gpio_export(unsigned gpio, bool direction_may_change)
633 {
634 return -ENOSYS;
635 }
636
637 static inline int gpio_export_link(struct device *dev, const char *name,
638 unsigned gpio)
639 {
640 return -ENOSYS;
641 }
642
643 static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
644 {
645 return -ENOSYS;
646 }
647
648 static inline void gpio_unexport(unsigned gpio)
649 {
650 }
651
652 #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
653
654 #endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
655
656 #endif /* !CONFIG_GPIOLIB */
657
658 #endif /* _ALCHEMY_GPIO_AU1000_H_ */
Linux with added FPC-III support