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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / arch / mips / include / asm / mipsregs.h
blob764e2756b54dacdf0c8aa4eac5600be3d8b30686
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/war.h>
20
21 /*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25 #ifndef __STR
26 #define __STR(x) #x
27 #endif
28 #ifndef STR
29 #define STR(x) __STR(x)
30 #endif
31
32 /*
33 * Configure language
34 */
35 #ifdef __ASSEMBLY__
36 #define _ULCAST_
37 #else
38 #define _ULCAST_ (unsigned long)
39 #endif
40
41 /*
42 * Coprocessor 0 register names
43 */
44 #define CP0_INDEX $0
45 #define CP0_RANDOM $1
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
48 #define CP0_CONF $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
51 #define CP0_WIRED $6
52 #define CP0_INFO $7
53 #define CP0_BADVADDR $8
54 #define CP0_COUNT $9
55 #define CP0_ENTRYHI $10
56 #define CP0_COMPARE $11
57 #define CP0_STATUS $12
58 #define CP0_CAUSE $13
59 #define CP0_EPC $14
60 #define CP0_PRID $15
61 #define CP0_CONFIG $16
62 #define CP0_LLADDR $17
63 #define CP0_WATCHLO $18
64 #define CP0_WATCHHI $19
65 #define CP0_XCONTEXT $20
66 #define CP0_FRAMEMASK $21
67 #define CP0_DIAGNOSTIC $22
68 #define CP0_DEBUG $23
69 #define CP0_DEPC $24
70 #define CP0_PERFORMANCE $25
71 #define CP0_ECC $26
72 #define CP0_CACHEERR $27
73 #define CP0_TAGLO $28
74 #define CP0_TAGHI $29
75 #define CP0_ERROREPC $30
76 #define CP0_DESAVE $31
77
78 /*
79 * R4640/R4650 cp0 register names. These registers are listed
80 * here only for completeness; without MMU these CPUs are not useable
81 * by Linux. A future ELKS port might take make Linux run on them
82 * though ...
83 */
84 #define CP0_IBASE $0
85 #define CP0_IBOUND $1
86 #define CP0_DBASE $2
87 #define CP0_DBOUND $3
88 #define CP0_CALG $17
89 #define CP0_IWATCH $18
90 #define CP0_DWATCH $19
91
92 /*
93 * Coprocessor 0 Set 1 register names
94 */
95 #define CP0_S1_DERRADDR0 $26
96 #define CP0_S1_DERRADDR1 $27
97 #define CP0_S1_INTCONTROL $20
98
99 /*
100 * Coprocessor 0 Set 2 register names
101 */
102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
103
104 /*
105 * Coprocessor 0 Set 3 register names
106 */
107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
108
109 /*
110 * TX39 Series
111 */
112 #define CP0_TX39_CACHE $7
113
114
115 /*
116 * Values for PageMask register
117 */
118 #ifdef CONFIG_CPU_VR41XX
119
120 /* Why doesn't stupidity hurt ... */
121
122 #define PM_1K 0x00000000
123 #define PM_4K 0x00001800
124 #define PM_16K 0x00007800
125 #define PM_64K 0x0001f800
126 #define PM_256K 0x0007f800
127
128 #else
129
130 #define PM_4K 0x00000000
131 #define PM_8K 0x00002000
132 #define PM_16K 0x00006000
133 #define PM_32K 0x0000e000
134 #define PM_64K 0x0001e000
135 #define PM_128K 0x0003e000
136 #define PM_256K 0x0007e000
137 #define PM_512K 0x000fe000
138 #define PM_1M 0x001fe000
139 #define PM_2M 0x003fe000
140 #define PM_4M 0x007fe000
141 #define PM_8M 0x00ffe000
142 #define PM_16M 0x01ffe000
143 #define PM_32M 0x03ffe000
144 #define PM_64M 0x07ffe000
145 #define PM_256M 0x1fffe000
146 #define PM_1G 0x7fffe000
147
148 #endif
149
150 /*
151 * Default page size for a given kernel configuration
152 */
153 #ifdef CONFIG_PAGE_SIZE_4KB
154 #define PM_DEFAULT_MASK PM_4K
155 #elif defined(CONFIG_PAGE_SIZE_8KB)
156 #define PM_DEFAULT_MASK PM_8K
157 #elif defined(CONFIG_PAGE_SIZE_16KB)
158 #define PM_DEFAULT_MASK PM_16K
159 #elif defined(CONFIG_PAGE_SIZE_32KB)
160 #define PM_DEFAULT_MASK PM_32K
161 #elif defined(CONFIG_PAGE_SIZE_64KB)
162 #define PM_DEFAULT_MASK PM_64K
163 #else
164 #error Bad page size configuration!
165 #endif
166
167 /*
168 * Default huge tlb size for a given kernel configuration
169 */
170 #ifdef CONFIG_PAGE_SIZE_4KB
171 #define PM_HUGE_MASK PM_1M
172 #elif defined(CONFIG_PAGE_SIZE_8KB)
173 #define PM_HUGE_MASK PM_4M
174 #elif defined(CONFIG_PAGE_SIZE_16KB)
175 #define PM_HUGE_MASK PM_16M
176 #elif defined(CONFIG_PAGE_SIZE_32KB)
177 #define PM_HUGE_MASK PM_64M
178 #elif defined(CONFIG_PAGE_SIZE_64KB)
179 #define PM_HUGE_MASK PM_256M
180 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
181 #error Bad page size configuration for hugetlbfs!
182 #endif
183
184 /*
185 * Values used for computation of new tlb entries
186 */
187 #define PL_4K 12
188 #define PL_16K 14
189 #define PL_64K 16
190 #define PL_256K 18
191 #define PL_1M 20
192 #define PL_4M 22
193 #define PL_16M 24
194 #define PL_64M 26
195 #define PL_256M 28
196
197 /*
198 * PageGrain bits
199 */
200 #define PG_RIE (_ULCAST_(1) << 31)
201 #define PG_XIE (_ULCAST_(1) << 30)
202 #define PG_ELPA (_ULCAST_(1) << 29)
203 #define PG_ESP (_ULCAST_(1) << 28)
204 #define PG_IEC (_ULCAST_(1) << 27)
205
206 /*
207 * R4x00 interrupt enable / cause bits
208 */
209 #define IE_SW0 (_ULCAST_(1) << 8)
210 #define IE_SW1 (_ULCAST_(1) << 9)
211 #define IE_IRQ0 (_ULCAST_(1) << 10)
212 #define IE_IRQ1 (_ULCAST_(1) << 11)
213 #define IE_IRQ2 (_ULCAST_(1) << 12)
214 #define IE_IRQ3 (_ULCAST_(1) << 13)
215 #define IE_IRQ4 (_ULCAST_(1) << 14)
216 #define IE_IRQ5 (_ULCAST_(1) << 15)
217
218 /*
219 * R4x00 interrupt cause bits
220 */
221 #define C_SW0 (_ULCAST_(1) << 8)
222 #define C_SW1 (_ULCAST_(1) << 9)
223 #define C_IRQ0 (_ULCAST_(1) << 10)
224 #define C_IRQ1 (_ULCAST_(1) << 11)
225 #define C_IRQ2 (_ULCAST_(1) << 12)
226 #define C_IRQ3 (_ULCAST_(1) << 13)
227 #define C_IRQ4 (_ULCAST_(1) << 14)
228 #define C_IRQ5 (_ULCAST_(1) << 15)
229
230 /*
231 * Bitfields in the R4xx0 cp0 status register
232 */
233 #define ST0_IE 0x00000001
234 #define ST0_EXL 0x00000002
235 #define ST0_ERL 0x00000004
236 #define ST0_KSU 0x00000018
237 # define KSU_USER 0x00000010
238 # define KSU_SUPERVISOR 0x00000008
239 # define KSU_KERNEL 0x00000000
240 #define ST0_UX 0x00000020
241 #define ST0_SX 0x00000040
242 #define ST0_KX 0x00000080
243 #define ST0_DE 0x00010000
244 #define ST0_CE 0x00020000
245
246 /*
247 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
248 * cacheops in userspace. This bit exists only on RM7000 and RM9000
249 * processors.
250 */
251 #define ST0_CO 0x08000000
252
253 /*
254 * Bitfields in the R[23]000 cp0 status register.
255 */
256 #define ST0_IEC 0x00000001
257 #define ST0_KUC 0x00000002
258 #define ST0_IEP 0x00000004
259 #define ST0_KUP 0x00000008
260 #define ST0_IEO 0x00000010
261 #define ST0_KUO 0x00000020
262 /* bits 6 & 7 are reserved on R[23]000 */
263 #define ST0_ISC 0x00010000
264 #define ST0_SWC 0x00020000
265 #define ST0_CM 0x00080000
266
267 /*
268 * Bits specific to the R4640/R4650
269 */
270 #define ST0_UM (_ULCAST_(1) << 4)
271 #define ST0_IL (_ULCAST_(1) << 23)
272 #define ST0_DL (_ULCAST_(1) << 24)
273
274 /*
275 * Enable the MIPS MDMX and DSP ASEs
276 */
277 #define ST0_MX 0x01000000
278
279 /*
280 * Status register bits available in all MIPS CPUs.
281 */
282 #define ST0_IM 0x0000ff00
283 #define STATUSB_IP0 8
284 #define STATUSF_IP0 (_ULCAST_(1) << 8)
285 #define STATUSB_IP1 9
286 #define STATUSF_IP1 (_ULCAST_(1) << 9)
287 #define STATUSB_IP2 10
288 #define STATUSF_IP2 (_ULCAST_(1) << 10)
289 #define STATUSB_IP3 11
290 #define STATUSF_IP3 (_ULCAST_(1) << 11)
291 #define STATUSB_IP4 12
292 #define STATUSF_IP4 (_ULCAST_(1) << 12)
293 #define STATUSB_IP5 13
294 #define STATUSF_IP5 (_ULCAST_(1) << 13)
295 #define STATUSB_IP6 14
296 #define STATUSF_IP6 (_ULCAST_(1) << 14)
297 #define STATUSB_IP7 15
298 #define STATUSF_IP7 (_ULCAST_(1) << 15)
299 #define STATUSB_IP8 0
300 #define STATUSF_IP8 (_ULCAST_(1) << 0)
301 #define STATUSB_IP9 1
302 #define STATUSF_IP9 (_ULCAST_(1) << 1)
303 #define STATUSB_IP10 2
304 #define STATUSF_IP10 (_ULCAST_(1) << 2)
305 #define STATUSB_IP11 3
306 #define STATUSF_IP11 (_ULCAST_(1) << 3)
307 #define STATUSB_IP12 4
308 #define STATUSF_IP12 (_ULCAST_(1) << 4)
309 #define STATUSB_IP13 5
310 #define STATUSF_IP13 (_ULCAST_(1) << 5)
311 #define STATUSB_IP14 6
312 #define STATUSF_IP14 (_ULCAST_(1) << 6)
313 #define STATUSB_IP15 7
314 #define STATUSF_IP15 (_ULCAST_(1) << 7)
315 #define ST0_CH 0x00040000
316 #define ST0_NMI 0x00080000
317 #define ST0_SR 0x00100000
318 #define ST0_TS 0x00200000
319 #define ST0_BEV 0x00400000
320 #define ST0_RE 0x02000000
321 #define ST0_FR 0x04000000
322 #define ST0_CU 0xf0000000
323 #define ST0_CU0 0x10000000
324 #define ST0_CU1 0x20000000
325 #define ST0_CU2 0x40000000
326 #define ST0_CU3 0x80000000
327 #define ST0_XX 0x80000000 /* MIPS IV naming */
328
329 /*
330 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
331 */
332 #define INTCTLB_IPFDC 23
333 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
334 #define INTCTLB_IPPCI 26
335 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
336 #define INTCTLB_IPTI 29
337 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
338
339 /*
340 * Bitfields and bit numbers in the coprocessor 0 cause register.
341 *
342 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
343 */
344 #define CAUSEB_EXCCODE 2
345 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
346 #define CAUSEB_IP 8
347 #define CAUSEF_IP (_ULCAST_(255) << 8)
348 #define CAUSEB_IP0 8
349 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
350 #define CAUSEB_IP1 9
351 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
352 #define CAUSEB_IP2 10
353 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
354 #define CAUSEB_IP3 11
355 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
356 #define CAUSEB_IP4 12
357 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
358 #define CAUSEB_IP5 13
359 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
360 #define CAUSEB_IP6 14
361 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
362 #define CAUSEB_IP7 15
363 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
364 #define CAUSEB_FDCI 21
365 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
366 #define CAUSEB_IV 23
367 #define CAUSEF_IV (_ULCAST_(1) << 23)
368 #define CAUSEB_PCI 26
369 #define CAUSEF_PCI (_ULCAST_(1) << 26)
370 #define CAUSEB_CE 28
371 #define CAUSEF_CE (_ULCAST_(3) << 28)
372 #define CAUSEB_TI 30
373 #define CAUSEF_TI (_ULCAST_(1) << 30)
374 #define CAUSEB_BD 31
375 #define CAUSEF_BD (_ULCAST_(1) << 31)
376
377 /*
378 * Bits in the coprocessor 0 config register.
379 */
380 /* Generic bits. */
381 #define CONF_CM_CACHABLE_NO_WA 0
382 #define CONF_CM_CACHABLE_WA 1
383 #define CONF_CM_UNCACHED 2
384 #define CONF_CM_CACHABLE_NONCOHERENT 3
385 #define CONF_CM_CACHABLE_CE 4
386 #define CONF_CM_CACHABLE_COW 5
387 #define CONF_CM_CACHABLE_CUW 6
388 #define CONF_CM_CACHABLE_ACCELERATED 7
389 #define CONF_CM_CMASK 7
390 #define CONF_BE (_ULCAST_(1) << 15)
391
392 /* Bits common to various processors. */
393 #define CONF_CU (_ULCAST_(1) << 3)
394 #define CONF_DB (_ULCAST_(1) << 4)
395 #define CONF_IB (_ULCAST_(1) << 5)
396 #define CONF_DC (_ULCAST_(7) << 6)
397 #define CONF_IC (_ULCAST_(7) << 9)
398 #define CONF_EB (_ULCAST_(1) << 13)
399 #define CONF_EM (_ULCAST_(1) << 14)
400 #define CONF_SM (_ULCAST_(1) << 16)
401 #define CONF_SC (_ULCAST_(1) << 17)
402 #define CONF_EW (_ULCAST_(3) << 18)
403 #define CONF_EP (_ULCAST_(15)<< 24)
404 #define CONF_EC (_ULCAST_(7) << 28)
405 #define CONF_CM (_ULCAST_(1) << 31)
406
407 /* Bits specific to the R4xx0. */
408 #define R4K_CONF_SW (_ULCAST_(1) << 20)
409 #define R4K_CONF_SS (_ULCAST_(1) << 21)
410 #define R4K_CONF_SB (_ULCAST_(3) << 22)
411
412 /* Bits specific to the R5000. */
413 #define R5K_CONF_SE (_ULCAST_(1) << 12)
414 #define R5K_CONF_SS (_ULCAST_(3) << 20)
415
416 /* Bits specific to the RM7000. */
417 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
418 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
419 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
420 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
421 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
422 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
423
424 /* Bits specific to the R10000. */
425 #define R10K_CONF_DN (_ULCAST_(3) << 3)
426 #define R10K_CONF_CT (_ULCAST_(1) << 5)
427 #define R10K_CONF_PE (_ULCAST_(1) << 6)
428 #define R10K_CONF_PM (_ULCAST_(3) << 7)
429 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
430 #define R10K_CONF_SB (_ULCAST_(1) << 13)
431 #define R10K_CONF_SK (_ULCAST_(1) << 14)
432 #define R10K_CONF_SS (_ULCAST_(7) << 16)
433 #define R10K_CONF_SC (_ULCAST_(7) << 19)
434 #define R10K_CONF_DC (_ULCAST_(7) << 26)
435 #define R10K_CONF_IC (_ULCAST_(7) << 29)
436
437 /* Bits specific to the VR41xx. */
438 #define VR41_CONF_CS (_ULCAST_(1) << 12)
439 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
440 #define VR41_CONF_BP (_ULCAST_(1) << 16)
441 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
442 #define VR41_CONF_AD (_ULCAST_(1) << 23)
443
444 /* Bits specific to the R30xx. */
445 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
446 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
447 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
448 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
449 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
450 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
451 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
452 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
453 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
454
455 /* Bits specific to the TX49. */
456 #define TX49_CONF_DC (_ULCAST_(1) << 16)
457 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
458 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
459 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
460
461 /* Bits specific to the MIPS32/64 PRA. */
462 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
463 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
464 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
465 #define MIPS_CONF_M (_ULCAST_(1) << 31)
466
467 /*
468 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
469 */
470 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
471 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
472 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
473 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
474 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
475 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
476 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
477 #define MIPS_CONF1_DA_SHF 7
478 #define MIPS_CONF1_DA_SZ 3
479 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
480 #define MIPS_CONF1_DL_SHF 10
481 #define MIPS_CONF1_DL_SZ 3
482 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
483 #define MIPS_CONF1_DS_SHF 13
484 #define MIPS_CONF1_DS_SZ 3
485 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
486 #define MIPS_CONF1_IA_SHF 16
487 #define MIPS_CONF1_IA_SZ 3
488 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
489 #define MIPS_CONF1_IL_SHF 19
490 #define MIPS_CONF1_IL_SZ 3
491 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
492 #define MIPS_CONF1_IS_SHF 22
493 #define MIPS_CONF1_IS_SZ 3
494 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
495 #define MIPS_CONF1_TLBS_SHIFT (25)
496 #define MIPS_CONF1_TLBS_SIZE (6)
497 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
498
499 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
500 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
501 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
502 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
503 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
504 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
505 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
506 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
507
508 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
509 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
510 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
511 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
512 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
513 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
514 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
515 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
516 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
517 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
518 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
519 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
520 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
521 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
522 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
523 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
524 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
525 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
526 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
527 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
528 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
529 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
530 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
531 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
532 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
533 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
534 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
535
536 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
537 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
538 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
539 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
540 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
541 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
542 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
543 /* bits 10:8 in FTLB-only configurations */
544 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
545 /* bits 12:8 in VTLB-FTLB only configurations */
546 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
547 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
548 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
549 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
550 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
551 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
552 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
553 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
554 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
555 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
556 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
557
558 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
559 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
560 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
561 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
562 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
563 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
564 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
565 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
566 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
567 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
568 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
569
570 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
571 /* proAptiv FTLB on/off bit */
572 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
573 /* FTLB probability bits */
574 #define MIPS_CONF6_FTLBP_SHIFT (16)
575
576 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
577
578 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
579
580 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
581 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
582
583 /* MAAR bit definitions */
584 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
585 #define MIPS_MAAR_ADDR_SHIFT 12
586 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
587 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
588
589 /* EntryHI bit definition */
590 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
591
592 /* CMGCRBase bit definitions */
593 #define MIPS_CMGCRB_BASE 11
594 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
595
596 /*
597 * Bits in the MIPS32 Memory Segmentation registers.
598 */
599 #define MIPS_SEGCFG_PA_SHIFT 9
600 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
601 #define MIPS_SEGCFG_AM_SHIFT 4
602 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
603 #define MIPS_SEGCFG_EU_SHIFT 3
604 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
605 #define MIPS_SEGCFG_C_SHIFT 0
606 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
607
608 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
609 #define MIPS_SEGCFG_USK _ULCAST_(5)
610 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
611 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
612 #define MIPS_SEGCFG_MSK _ULCAST_(2)
613 #define MIPS_SEGCFG_MK _ULCAST_(1)
614 #define MIPS_SEGCFG_UK _ULCAST_(0)
615
616 #define MIPS_PWFIELD_GDI_SHIFT 24
617 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
618 #define MIPS_PWFIELD_UDI_SHIFT 18
619 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
620 #define MIPS_PWFIELD_MDI_SHIFT 12
621 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
622 #define MIPS_PWFIELD_PTI_SHIFT 6
623 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
624 #define MIPS_PWFIELD_PTEI_SHIFT 0
625 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
626
627 #define MIPS_PWSIZE_GDW_SHIFT 24
628 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
629 #define MIPS_PWSIZE_UDW_SHIFT 18
630 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
631 #define MIPS_PWSIZE_MDW_SHIFT 12
632 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
633 #define MIPS_PWSIZE_PTW_SHIFT 6
634 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
635 #define MIPS_PWSIZE_PTEW_SHIFT 0
636 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
637
638 #define MIPS_PWCTL_PWEN_SHIFT 31
639 #define MIPS_PWCTL_PWEN_MASK 0x80000000
640 #define MIPS_PWCTL_DPH_SHIFT 7
641 #define MIPS_PWCTL_DPH_MASK 0x00000080
642 #define MIPS_PWCTL_HUGEPG_SHIFT 6
643 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
644 #define MIPS_PWCTL_PSN_SHIFT 0
645 #define MIPS_PWCTL_PSN_MASK 0x0000003f
646
647 /* CDMMBase register bit definitions */
648 #define MIPS_CDMMBASE_SIZE_SHIFT 0
649 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
650 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
651 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
652 #define MIPS_CDMMBASE_ADDR_SHIFT 11
653 #define MIPS_CDMMBASE_ADDR_START 15
654
655 /*
656 * Bitfields in the TX39 family CP0 Configuration Register 3
657 */
658 #define TX39_CONF_ICS_SHIFT 19
659 #define TX39_CONF_ICS_MASK 0x00380000
660 #define TX39_CONF_ICS_1KB 0x00000000
661 #define TX39_CONF_ICS_2KB 0x00080000
662 #define TX39_CONF_ICS_4KB 0x00100000
663 #define TX39_CONF_ICS_8KB 0x00180000
664 #define TX39_CONF_ICS_16KB 0x00200000
665
666 #define TX39_CONF_DCS_SHIFT 16
667 #define TX39_CONF_DCS_MASK 0x00070000
668 #define TX39_CONF_DCS_1KB 0x00000000
669 #define TX39_CONF_DCS_2KB 0x00010000
670 #define TX39_CONF_DCS_4KB 0x00020000
671 #define TX39_CONF_DCS_8KB 0x00030000
672 #define TX39_CONF_DCS_16KB 0x00040000
673
674 #define TX39_CONF_CWFON 0x00004000
675 #define TX39_CONF_WBON 0x00002000
676 #define TX39_CONF_RF_SHIFT 10
677 #define TX39_CONF_RF_MASK 0x00000c00
678 #define TX39_CONF_DOZE 0x00000200
679 #define TX39_CONF_HALT 0x00000100
680 #define TX39_CONF_LOCK 0x00000080
681 #define TX39_CONF_ICE 0x00000020
682 #define TX39_CONF_DCE 0x00000010
683 #define TX39_CONF_IRSIZE_SHIFT 2
684 #define TX39_CONF_IRSIZE_MASK 0x0000000c
685 #define TX39_CONF_DRSIZE_SHIFT 0
686 #define TX39_CONF_DRSIZE_MASK 0x00000003
687
688
689 /*
690 * Coprocessor 1 (FPU) register names
691 */
692 #define CP1_REVISION $0
693 #define CP1_UFR $1
694 #define CP1_UNFR $4
695 #define CP1_FCCR $25
696 #define CP1_FEXR $26
697 #define CP1_FENR $28
698 #define CP1_STATUS $31
699
700
701 /*
702 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
703 */
704 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
705 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
706 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
707 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
708 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
709 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
710 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
711 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
712 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
713 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
714
715 /*
716 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
717 */
718 #define MIPS_FCCR_CONDX_S 0
719 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
720 #define MIPS_FCCR_COND0_S 0
721 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
722 #define MIPS_FCCR_COND1_S 1
723 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
724 #define MIPS_FCCR_COND2_S 2
725 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
726 #define MIPS_FCCR_COND3_S 3
727 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
728 #define MIPS_FCCR_COND4_S 4
729 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
730 #define MIPS_FCCR_COND5_S 5
731 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
732 #define MIPS_FCCR_COND6_S 6
733 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
734 #define MIPS_FCCR_COND7_S 7
735 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
736
737 /*
738 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
739 */
740 #define MIPS_FENR_FS_S 2
741 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
742
743 /*
744 * FPU Status Register Values
745 */
746 #define FPU_CSR_COND_S 23 /* $fcc0 */
747 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
748
749 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
750 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
751
752 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
753 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
754 #define FPU_CSR_COND1_S 25 /* $fcc1 */
755 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
756 #define FPU_CSR_COND2_S 26 /* $fcc2 */
757 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
758 #define FPU_CSR_COND3_S 27 /* $fcc3 */
759 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
760 #define FPU_CSR_COND4_S 28 /* $fcc4 */
761 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
762 #define FPU_CSR_COND5_S 29 /* $fcc5 */
763 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
764 #define FPU_CSR_COND6_S 30 /* $fcc6 */
765 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
766 #define FPU_CSR_COND7_S 31 /* $fcc7 */
767 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
768
769 /*
770 * Bits 22:20 of the FPU Status Register will be read as 0,
771 * and should be written as zero.
772 */
773 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
774
775 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
776 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
777
778 /*
779 * X the exception cause indicator
780 * E the exception enable
781 * S the sticky/flag bit
782 */
783 #define FPU_CSR_ALL_X 0x0003f000
784 #define FPU_CSR_UNI_X 0x00020000
785 #define FPU_CSR_INV_X 0x00010000
786 #define FPU_CSR_DIV_X 0x00008000
787 #define FPU_CSR_OVF_X 0x00004000
788 #define FPU_CSR_UDF_X 0x00002000
789 #define FPU_CSR_INE_X 0x00001000
790
791 #define FPU_CSR_ALL_E 0x00000f80
792 #define FPU_CSR_INV_E 0x00000800
793 #define FPU_CSR_DIV_E 0x00000400
794 #define FPU_CSR_OVF_E 0x00000200
795 #define FPU_CSR_UDF_E 0x00000100
796 #define FPU_CSR_INE_E 0x00000080
797
798 #define FPU_CSR_ALL_S 0x0000007c
799 #define FPU_CSR_INV_S 0x00000040
800 #define FPU_CSR_DIV_S 0x00000020
801 #define FPU_CSR_OVF_S 0x00000010
802 #define FPU_CSR_UDF_S 0x00000008
803 #define FPU_CSR_INE_S 0x00000004
804
805 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
806 #define FPU_CSR_RM 0x00000003
807 #define FPU_CSR_RN 0x0 /* nearest */
808 #define FPU_CSR_RZ 0x1 /* towards zero */
809 #define FPU_CSR_RU 0x2 /* towards +Infinity */
810 #define FPU_CSR_RD 0x3 /* towards -Infinity */
811
812
813 #ifndef __ASSEMBLY__
814
815 /*
816 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
817 */
818 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
819 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
820 #define get_isa16_mode(x) ((x) & 0x1)
821 #define msk_isa16_mode(x) ((x) & ~0x1)
822 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
823 #else
824 #define get_isa16_mode(x) 0
825 #define msk_isa16_mode(x) (x)
826 #define set_isa16_mode(x) do { } while(0)
827 #endif
828
829 /*
830 * microMIPS instructions can be 16-bit or 32-bit in length. This
831 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
832 */
833 static inline int mm_insn_16bit(u16 insn)
834 {
835 u16 opcode = (insn >> 10) & 0x7;
836
837 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
838 }
839
840 /*
841 * TLB Invalidate Flush
842 */
843 static inline void tlbinvf(void)
844 {
845 __asm__ __volatile__(
846 ".set push\n\t"
847 ".set noreorder\n\t"
848 ".word 0x42000004\n\t" /* tlbinvf */
849 ".set pop");
850 }
851
852
853 /*
854 * Functions to access the R10000 performance counters. These are basically
855 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
856 * performance counter number encoded into bits 1 ... 5 of the instruction.
857 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
858 * disassembler these will look like an access to sel 0 or 1.
859 */
860 #define read_r10k_perf_cntr(counter) \
861 ({ \
862 unsigned int __res; \
863 __asm__ __volatile__( \
864 "mfpc\t%0, %1" \
865 : "=r" (__res) \
866 : "i" (counter)); \
867 \
868 __res; \
869 })
870
871 #define write_r10k_perf_cntr(counter,val) \
872 do { \
873 __asm__ __volatile__( \
874 "mtpc\t%0, %1" \
875 : \
876 : "r" (val), "i" (counter)); \
877 } while (0)
878
879 #define read_r10k_perf_event(counter) \
880 ({ \
881 unsigned int __res; \
882 __asm__ __volatile__( \
883 "mfps\t%0, %1" \
884 : "=r" (__res) \
885 : "i" (counter)); \
886 \
887 __res; \
888 })
889
890 #define write_r10k_perf_cntl(counter,val) \
891 do { \
892 __asm__ __volatile__( \
893 "mtps\t%0, %1" \
894 : \
895 : "r" (val), "i" (counter)); \
896 } while (0)
897
898
899 /*
900 * Macros to access the system control coprocessor
901 */
902
903 #define __read_32bit_c0_register(source, sel) \
904 ({ int __res; \
905 if (sel == 0) \
906 __asm__ __volatile__( \
907 "mfc0\t%0, " #source "\n\t" \
908 : "=r" (__res)); \
909 else \
910 __asm__ __volatile__( \
911 ".set\tmips32\n\t" \
912 "mfc0\t%0, " #source ", " #sel "\n\t" \
913 ".set\tmips0\n\t" \
914 : "=r" (__res)); \
915 __res; \
916 })
917
918 #define __read_64bit_c0_register(source, sel) \
919 ({ unsigned long long __res; \
920 if (sizeof(unsigned long) == 4) \
921 __res = __read_64bit_c0_split(source, sel); \
922 else if (sel == 0) \
923 __asm__ __volatile__( \
924 ".set\tmips3\n\t" \
925 "dmfc0\t%0, " #source "\n\t" \
926 ".set\tmips0" \
927 : "=r" (__res)); \
928 else \
929 __asm__ __volatile__( \
930 ".set\tmips64\n\t" \
931 "dmfc0\t%0, " #source ", " #sel "\n\t" \
932 ".set\tmips0" \
933 : "=r" (__res)); \
934 __res; \
935 })
936
937 #define __write_32bit_c0_register(register, sel, value) \
938 do { \
939 if (sel == 0) \
940 __asm__ __volatile__( \
941 "mtc0\t%z0, " #register "\n\t" \
942 : : "Jr" ((unsigned int)(value))); \
943 else \
944 __asm__ __volatile__( \
945 ".set\tmips32\n\t" \
946 "mtc0\t%z0, " #register ", " #sel "\n\t" \
947 ".set\tmips0" \
948 : : "Jr" ((unsigned int)(value))); \
949 } while (0)
950
951 #define __write_64bit_c0_register(register, sel, value) \
952 do { \
953 if (sizeof(unsigned long) == 4) \
954 __write_64bit_c0_split(register, sel, value); \
955 else if (sel == 0) \
956 __asm__ __volatile__( \
957 ".set\tmips3\n\t" \
958 "dmtc0\t%z0, " #register "\n\t" \
959 ".set\tmips0" \
960 : : "Jr" (value)); \
961 else \
962 __asm__ __volatile__( \
963 ".set\tmips64\n\t" \
964 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
965 ".set\tmips0" \
966 : : "Jr" (value)); \
967 } while (0)
968
969 #define __read_ulong_c0_register(reg, sel) \
970 ((sizeof(unsigned long) == 4) ? \
971 (unsigned long) __read_32bit_c0_register(reg, sel) : \
972 (unsigned long) __read_64bit_c0_register(reg, sel))
973
974 #define __write_ulong_c0_register(reg, sel, val) \
975 do { \
976 if (sizeof(unsigned long) == 4) \
977 __write_32bit_c0_register(reg, sel, val); \
978 else \
979 __write_64bit_c0_register(reg, sel, val); \
980 } while (0)
981
982 /*
983 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
984 */
985 #define __read_32bit_c0_ctrl_register(source) \
986 ({ int __res; \
987 __asm__ __volatile__( \
988 "cfc0\t%0, " #source "\n\t" \
989 : "=r" (__res)); \
990 __res; \
991 })
992
993 #define __write_32bit_c0_ctrl_register(register, value) \
994 do { \
995 __asm__ __volatile__( \
996 "ctc0\t%z0, " #register "\n\t" \
997 : : "Jr" ((unsigned int)(value))); \
998 } while (0)
999
1000 /*
1001 * These versions are only needed for systems with more than 38 bits of
1002 * physical address space running the 32-bit kernel. That's none atm :-)
1003 */
1004 #define __read_64bit_c0_split(source, sel) \
1005 ({ \
1006 unsigned long long __val; \
1007 unsigned long __flags; \
1008 \
1009 local_irq_save(__flags); \
1010 if (sel == 0) \
1011 __asm__ __volatile__( \
1012 ".set\tmips64\n\t" \
1013 "dmfc0\t%M0, " #source "\n\t" \
1014 "dsll\t%L0, %M0, 32\n\t" \
1015 "dsra\t%M0, %M0, 32\n\t" \
1016 "dsra\t%L0, %L0, 32\n\t" \
1017 ".set\tmips0" \
1018 : "=r" (__val)); \
1019 else \
1020 __asm__ __volatile__( \
1021 ".set\tmips64\n\t" \
1022 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1023 "dsll\t%L0, %M0, 32\n\t" \
1024 "dsra\t%M0, %M0, 32\n\t" \
1025 "dsra\t%L0, %L0, 32\n\t" \
1026 ".set\tmips0" \
1027 : "=r" (__val)); \
1028 local_irq_restore(__flags); \
1029 \
1030 __val; \
1031 })
1032
1033 #define __write_64bit_c0_split(source, sel, val) \
1034 do { \
1035 unsigned long __flags; \
1036 \
1037 local_irq_save(__flags); \
1038 if (sel == 0) \
1039 __asm__ __volatile__( \
1040 ".set\tmips64\n\t" \
1041 "dsll\t%L0, %L0, 32\n\t" \
1042 "dsrl\t%L0, %L0, 32\n\t" \
1043 "dsll\t%M0, %M0, 32\n\t" \
1044 "or\t%L0, %L0, %M0\n\t" \
1045 "dmtc0\t%L0, " #source "\n\t" \
1046 ".set\tmips0" \
1047 : : "r" (val)); \
1048 else \
1049 __asm__ __volatile__( \
1050 ".set\tmips64\n\t" \
1051 "dsll\t%L0, %L0, 32\n\t" \
1052 "dsrl\t%L0, %L0, 32\n\t" \
1053 "dsll\t%M0, %M0, 32\n\t" \
1054 "or\t%L0, %L0, %M0\n\t" \
1055 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1056 ".set\tmips0" \
1057 : : "r" (val)); \
1058 local_irq_restore(__flags); \
1059 } while (0)
1060
1061 #define __readx_32bit_c0_register(source) \
1062 ({ \
1063 unsigned int __res; \
1064 \
1065 __asm__ __volatile__( \
1066 " .set push \n" \
1067 " .set noat \n" \
1068 " .set mips32r2 \n" \
1069 " .insn \n" \
1070 " # mfhc0 $1, %1 \n" \
1071 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1072 " move %0, $1 \n" \
1073 " .set pop \n" \
1074 : "=r" (__res) \
1075 : "i" (source)); \
1076 __res; \
1077 })
1078
1079 #define __writex_32bit_c0_register(register, value) \
1080 do { \
1081 __asm__ __volatile__( \
1082 " .set push \n" \
1083 " .set noat \n" \
1084 " .set mips32r2 \n" \
1085 " move $1, %0 \n" \
1086 " # mthc0 $1, %1 \n" \
1087 " .insn \n" \
1088 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1089 " .set pop \n" \
1090 : \
1091 : "r" (value), "i" (register)); \
1092 } while (0)
1093
1094 #define read_c0_index() __read_32bit_c0_register($0, 0)
1095 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1096
1097 #define read_c0_random() __read_32bit_c0_register($1, 0)
1098 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1099
1100 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1101 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1102
1103 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1104 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1105
1106 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1107 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1108
1109 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1110 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1111
1112 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1113 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1114
1115 #define read_c0_context() __read_ulong_c0_register($4, 0)
1116 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1117
1118 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1119 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1120
1121 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1122 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1123
1124 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1125 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1126
1127 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1128 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1129
1130 #define read_c0_info() __read_32bit_c0_register($7, 0)
1131
1132 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1133 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1134
1135 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1136 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1137
1138 #define read_c0_count() __read_32bit_c0_register($9, 0)
1139 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1140
1141 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1142 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1143
1144 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1145 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1146
1147 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1148 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1149
1150 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1151 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1152
1153 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1154 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1155
1156 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1157 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1158
1159 #define read_c0_status() __read_32bit_c0_register($12, 0)
1160
1161 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1162
1163 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1164 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1165
1166 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1167 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1168
1169 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1170
1171 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1172
1173 #define read_c0_config() __read_32bit_c0_register($16, 0)
1174 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1175 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1176 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1177 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1178 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1179 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1180 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1181 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1182 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1183 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1184 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1185 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1186 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1187 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1188 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1189
1190 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1191 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1192 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1193 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1194 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1195 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1196
1197 /*
1198 * The WatchLo register. There may be up to 8 of them.
1199 */
1200 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1201 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1202 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1203 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1204 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1205 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1206 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1207 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1208 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1209 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1210 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1211 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1212 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1213 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1214 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1215 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1216
1217 /*
1218 * The WatchHi register. There may be up to 8 of them.
1219 */
1220 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1221 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1222 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1223 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1224 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1225 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1226 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1227 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1228
1229 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1230 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1231 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1232 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1233 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1234 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1235 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1236 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1237
1238 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1239 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1240
1241 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1242 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1243
1244 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1245 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1246
1247 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1248 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1249
1250 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1251 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1252
1253 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1254 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1255
1256 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1257 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1258
1259 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1260 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1261
1262 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1263 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1264
1265 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1266 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1267
1268 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1269 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1270
1271 /*
1272 * MIPS32 / MIPS64 performance counters
1273 */
1274 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1275 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1276 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1277 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1278 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1279 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1280 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1281 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1282 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1283 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1284 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1285 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1286 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1287 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1288 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1289 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1290 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1291 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1292 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1293 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1294 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1295 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1296 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1297 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1298
1299 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1300 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1301
1302 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1303 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1304
1305 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1306
1307 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1308 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1309
1310 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1311 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1312
1313 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1314 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1315
1316 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1317 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1318
1319 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1320 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1321
1322 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1323 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1324
1325 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1326 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1327
1328 /* MIPSR2 */
1329 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1330 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1331
1332 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1333 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1334
1335 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1336 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1337
1338 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1339 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1340
1341 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1342 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1343
1344 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1345 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1346
1347 /* MIPSR3 */
1348 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1349 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1350
1351 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1352 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1353
1354 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1355 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1356
1357 /* Hardware Page Table Walker */
1358 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1359 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1360
1361 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1362 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1363
1364 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1365 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1366
1367 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1368 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1369
1370 /* Cavium OCTEON (cnMIPS) */
1371 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1372 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1373
1374 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1375 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1376
1377 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1378 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1379 /*
1380 * The cacheerr registers are not standardized. On OCTEON, they are
1381 * 64 bits wide.
1382 */
1383 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1384 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1385
1386 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1387 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1388
1389 /* BMIPS3300 */
1390 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1391 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1392
1393 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1394 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1395
1396 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1397 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1398
1399 /* BMIPS43xx */
1400 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1401 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1402
1403 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1404 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1405
1406 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1407 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1408
1409 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1410 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1411
1412 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1413 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1414
1415 /* BMIPS5000 */
1416 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1417 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1418
1419 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1420 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1421
1422 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1423 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1424
1425 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1426 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1427
1428 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1429 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1430
1431 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1432 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1433
1434 /*
1435 * Macros to access the floating point coprocessor control registers
1436 */
1437 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1438 ({ \
1439 int __res; \
1440 \
1441 __asm__ __volatile__( \
1442 " .set push \n" \
1443 " .set reorder \n" \
1444 " # gas fails to assemble cfc1 for some archs, \n" \
1445 " # like Octeon. \n" \
1446 " .set mips1 \n" \
1447 " "STR(gas_hardfloat)" \n" \
1448 " cfc1 %0,"STR(source)" \n" \
1449 " .set pop \n" \
1450 : "=r" (__res)); \
1451 __res; \
1452 })
1453
1454 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1455 do { \
1456 __asm__ __volatile__( \
1457 " .set push \n" \
1458 " .set reorder \n" \
1459 " "STR(gas_hardfloat)" \n" \
1460 " ctc1 %0,"STR(dest)" \n" \
1461 " .set pop \n" \
1462 : : "r" (val)); \
1463 } while (0)
1464
1465 #ifdef GAS_HAS_SET_HARDFLOAT
1466 #define read_32bit_cp1_register(source) \
1467 _read_32bit_cp1_register(source, .set hardfloat)
1468 #define write_32bit_cp1_register(dest, val) \
1469 _write_32bit_cp1_register(dest, val, .set hardfloat)
1470 #else
1471 #define read_32bit_cp1_register(source) \
1472 _read_32bit_cp1_register(source, )
1473 #define write_32bit_cp1_register(dest, val) \
1474 _write_32bit_cp1_register(dest, val, )
1475 #endif
1476
1477 #ifdef HAVE_AS_DSP
1478 #define rddsp(mask) \
1479 ({ \
1480 unsigned int __dspctl; \
1481 \
1482 __asm__ __volatile__( \
1483 " .set push \n" \
1484 " .set dsp \n" \
1485 " rddsp %0, %x1 \n" \
1486 " .set pop \n" \
1487 : "=r" (__dspctl) \
1488 : "i" (mask)); \
1489 __dspctl; \
1490 })
1491
1492 #define wrdsp(val, mask) \
1493 do { \
1494 __asm__ __volatile__( \
1495 " .set push \n" \
1496 " .set dsp \n" \
1497 " wrdsp %0, %x1 \n" \
1498 " .set pop \n" \
1499 : \
1500 : "r" (val), "i" (mask)); \
1501 } while (0)
1502
1503 #define mflo0() \
1504 ({ \
1505 long mflo0; \
1506 __asm__( \
1507 " .set push \n" \
1508 " .set dsp \n" \
1509 " mflo %0, $ac0 \n" \
1510 " .set pop \n" \
1511 : "=r" (mflo0)); \
1512 mflo0; \
1513 })
1514
1515 #define mflo1() \
1516 ({ \
1517 long mflo1; \
1518 __asm__( \
1519 " .set push \n" \
1520 " .set dsp \n" \
1521 " mflo %0, $ac1 \n" \
1522 " .set pop \n" \
1523 : "=r" (mflo1)); \
1524 mflo1; \
1525 })
1526
1527 #define mflo2() \
1528 ({ \
1529 long mflo2; \
1530 __asm__( \
1531 " .set push \n" \
1532 " .set dsp \n" \
1533 " mflo %0, $ac2 \n" \
1534 " .set pop \n" \
1535 : "=r" (mflo2)); \
1536 mflo2; \
1537 })
1538
1539 #define mflo3() \
1540 ({ \
1541 long mflo3; \
1542 __asm__( \
1543 " .set push \n" \
1544 " .set dsp \n" \
1545 " mflo %0, $ac3 \n" \
1546 " .set pop \n" \
1547 : "=r" (mflo3)); \
1548 mflo3; \
1549 })
1550
1551 #define mfhi0() \
1552 ({ \
1553 long mfhi0; \
1554 __asm__( \
1555 " .set push \n" \
1556 " .set dsp \n" \
1557 " mfhi %0, $ac0 \n" \
1558 " .set pop \n" \
1559 : "=r" (mfhi0)); \
1560 mfhi0; \
1561 })
1562
1563 #define mfhi1() \
1564 ({ \
1565 long mfhi1; \
1566 __asm__( \
1567 " .set push \n" \
1568 " .set dsp \n" \
1569 " mfhi %0, $ac1 \n" \
1570 " .set pop \n" \
1571 : "=r" (mfhi1)); \
1572 mfhi1; \
1573 })
1574
1575 #define mfhi2() \
1576 ({ \
1577 long mfhi2; \
1578 __asm__( \
1579 " .set push \n" \
1580 " .set dsp \n" \
1581 " mfhi %0, $ac2 \n" \
1582 " .set pop \n" \
1583 : "=r" (mfhi2)); \
1584 mfhi2; \
1585 })
1586
1587 #define mfhi3() \
1588 ({ \
1589 long mfhi3; \
1590 __asm__( \
1591 " .set push \n" \
1592 " .set dsp \n" \
1593 " mfhi %0, $ac3 \n" \
1594 " .set pop \n" \
1595 : "=r" (mfhi3)); \
1596 mfhi3; \
1597 })
1598
1599
1600 #define mtlo0(x) \
1601 ({ \
1602 __asm__( \
1603 " .set push \n" \
1604 " .set dsp \n" \
1605 " mtlo %0, $ac0 \n" \
1606 " .set pop \n" \
1607 : \
1608 : "r" (x)); \
1609 })
1610
1611 #define mtlo1(x) \
1612 ({ \
1613 __asm__( \
1614 " .set push \n" \
1615 " .set dsp \n" \
1616 " mtlo %0, $ac1 \n" \
1617 " .set pop \n" \
1618 : \
1619 : "r" (x)); \
1620 })
1621
1622 #define mtlo2(x) \
1623 ({ \
1624 __asm__( \
1625 " .set push \n" \
1626 " .set dsp \n" \
1627 " mtlo %0, $ac2 \n" \
1628 " .set pop \n" \
1629 : \
1630 : "r" (x)); \
1631 })
1632
1633 #define mtlo3(x) \
1634 ({ \
1635 __asm__( \
1636 " .set push \n" \
1637 " .set dsp \n" \
1638 " mtlo %0, $ac3 \n" \
1639 " .set pop \n" \
1640 : \
1641 : "r" (x)); \
1642 })
1643
1644 #define mthi0(x) \
1645 ({ \
1646 __asm__( \
1647 " .set push \n" \
1648 " .set dsp \n" \
1649 " mthi %0, $ac0 \n" \
1650 " .set pop \n" \
1651 : \
1652 : "r" (x)); \
1653 })
1654
1655 #define mthi1(x) \
1656 ({ \
1657 __asm__( \
1658 " .set push \n" \
1659 " .set dsp \n" \
1660 " mthi %0, $ac1 \n" \
1661 " .set pop \n" \
1662 : \
1663 : "r" (x)); \
1664 })
1665
1666 #define mthi2(x) \
1667 ({ \
1668 __asm__( \
1669 " .set push \n" \
1670 " .set dsp \n" \
1671 " mthi %0, $ac2 \n" \
1672 " .set pop \n" \
1673 : \
1674 : "r" (x)); \
1675 })
1676
1677 #define mthi3(x) \
1678 ({ \
1679 __asm__( \
1680 " .set push \n" \
1681 " .set dsp \n" \
1682 " mthi %0, $ac3 \n" \
1683 " .set pop \n" \
1684 : \
1685 : "r" (x)); \
1686 })
1687
1688 #else
1689
1690 #ifdef CONFIG_CPU_MICROMIPS
1691 #define rddsp(mask) \
1692 ({ \
1693 unsigned int __res; \
1694 \
1695 __asm__ __volatile__( \
1696 " .set push \n" \
1697 " .set noat \n" \
1698 " # rddsp $1, %x1 \n" \
1699 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1700 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1701 " move %0, $1 \n" \
1702 " .set pop \n" \
1703 : "=r" (__res) \
1704 : "i" (mask)); \
1705 __res; \
1706 })
1707
1708 #define wrdsp(val, mask) \
1709 do { \
1710 __asm__ __volatile__( \
1711 " .set push \n" \
1712 " .set noat \n" \
1713 " move $1, %0 \n" \
1714 " # wrdsp $1, %x1 \n" \
1715 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1716 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1717 " .set pop \n" \
1718 : \
1719 : "r" (val), "i" (mask)); \
1720 } while (0)
1721
1722 #define _umips_dsp_mfxxx(ins) \
1723 ({ \
1724 unsigned long __treg; \
1725 \
1726 __asm__ __volatile__( \
1727 " .set push \n" \
1728 " .set noat \n" \
1729 " .hword 0x0001 \n" \
1730 " .hword %x1 \n" \
1731 " move %0, $1 \n" \
1732 " .set pop \n" \
1733 : "=r" (__treg) \
1734 : "i" (ins)); \
1735 __treg; \
1736 })
1737
1738 #define _umips_dsp_mtxxx(val, ins) \
1739 do { \
1740 __asm__ __volatile__( \
1741 " .set push \n" \
1742 " .set noat \n" \
1743 " move $1, %0 \n" \
1744 " .hword 0x0001 \n" \
1745 " .hword %x1 \n" \
1746 " .set pop \n" \
1747 : \
1748 : "r" (val), "i" (ins)); \
1749 } while (0)
1750
1751 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1752 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1753
1754 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1755 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1756
1757 #define mflo0() _umips_dsp_mflo(0)
1758 #define mflo1() _umips_dsp_mflo(1)
1759 #define mflo2() _umips_dsp_mflo(2)
1760 #define mflo3() _umips_dsp_mflo(3)
1761
1762 #define mfhi0() _umips_dsp_mfhi(0)
1763 #define mfhi1() _umips_dsp_mfhi(1)
1764 #define mfhi2() _umips_dsp_mfhi(2)
1765 #define mfhi3() _umips_dsp_mfhi(3)
1766
1767 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1768 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1769 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1770 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1771
1772 #define mthi0(x) _umips_dsp_mthi(x, 0)
1773 #define mthi1(x) _umips_dsp_mthi(x, 1)
1774 #define mthi2(x) _umips_dsp_mthi(x, 2)
1775 #define mthi3(x) _umips_dsp_mthi(x, 3)
1776
1777 #else /* !CONFIG_CPU_MICROMIPS */
1778 #define rddsp(mask) \
1779 ({ \
1780 unsigned int __res; \
1781 \
1782 __asm__ __volatile__( \
1783 " .set push \n" \
1784 " .set noat \n" \
1785 " # rddsp $1, %x1 \n" \
1786 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1787 " move %0, $1 \n" \
1788 " .set pop \n" \
1789 : "=r" (__res) \
1790 : "i" (mask)); \
1791 __res; \
1792 })
1793
1794 #define wrdsp(val, mask) \
1795 do { \
1796 __asm__ __volatile__( \
1797 " .set push \n" \
1798 " .set noat \n" \
1799 " move $1, %0 \n" \
1800 " # wrdsp $1, %x1 \n" \
1801 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1802 " .set pop \n" \
1803 : \
1804 : "r" (val), "i" (mask)); \
1805 } while (0)
1806
1807 #define _dsp_mfxxx(ins) \
1808 ({ \
1809 unsigned long __treg; \
1810 \
1811 __asm__ __volatile__( \
1812 " .set push \n" \
1813 " .set noat \n" \
1814 " .word (0x00000810 | %1) \n" \
1815 " move %0, $1 \n" \
1816 " .set pop \n" \
1817 : "=r" (__treg) \
1818 : "i" (ins)); \
1819 __treg; \
1820 })
1821
1822 #define _dsp_mtxxx(val, ins) \
1823 do { \
1824 __asm__ __volatile__( \
1825 " .set push \n" \
1826 " .set noat \n" \
1827 " move $1, %0 \n" \
1828 " .word (0x00200011 | %1) \n" \
1829 " .set pop \n" \
1830 : \
1831 : "r" (val), "i" (ins)); \
1832 } while (0)
1833
1834 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1835 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1836
1837 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1838 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1839
1840 #define mflo0() _dsp_mflo(0)
1841 #define mflo1() _dsp_mflo(1)
1842 #define mflo2() _dsp_mflo(2)
1843 #define mflo3() _dsp_mflo(3)
1844
1845 #define mfhi0() _dsp_mfhi(0)
1846 #define mfhi1() _dsp_mfhi(1)
1847 #define mfhi2() _dsp_mfhi(2)
1848 #define mfhi3() _dsp_mfhi(3)
1849
1850 #define mtlo0(x) _dsp_mtlo(x, 0)
1851 #define mtlo1(x) _dsp_mtlo(x, 1)
1852 #define mtlo2(x) _dsp_mtlo(x, 2)
1853 #define mtlo3(x) _dsp_mtlo(x, 3)
1854
1855 #define mthi0(x) _dsp_mthi(x, 0)
1856 #define mthi1(x) _dsp_mthi(x, 1)
1857 #define mthi2(x) _dsp_mthi(x, 2)
1858 #define mthi3(x) _dsp_mthi(x, 3)
1859
1860 #endif /* CONFIG_CPU_MICROMIPS */
1861 #endif
1862
1863 /*
1864 * TLB operations.
1865 *
1866 * It is responsibility of the caller to take care of any TLB hazards.
1867 */
1868 static inline void tlb_probe(void)
1869 {
1870 __asm__ __volatile__(
1871 ".set noreorder\n\t"
1872 "tlbp\n\t"
1873 ".set reorder");
1874 }
1875
1876 static inline void tlb_read(void)
1877 {
1878 #if MIPS34K_MISSED_ITLB_WAR
1879 int res = 0;
1880
1881 __asm__ __volatile__(
1882 " .set push \n"
1883 " .set noreorder \n"
1884 " .set noat \n"
1885 " .set mips32r2 \n"
1886 " .word 0x41610001 # dvpe $1 \n"
1887 " move %0, $1 \n"
1888 " ehb \n"
1889 " .set pop \n"
1890 : "=r" (res));
1891
1892 instruction_hazard();
1893 #endif
1894
1895 __asm__ __volatile__(
1896 ".set noreorder\n\t"
1897 "tlbr\n\t"
1898 ".set reorder");
1899
1900 #if MIPS34K_MISSED_ITLB_WAR
1901 if ((res & _ULCAST_(1)))
1902 __asm__ __volatile__(
1903 " .set push \n"
1904 " .set noreorder \n"
1905 " .set noat \n"
1906 " .set mips32r2 \n"
1907 " .word 0x41600021 # evpe \n"
1908 " ehb \n"
1909 " .set pop \n");
1910 #endif
1911 }
1912
1913 static inline void tlb_write_indexed(void)
1914 {
1915 __asm__ __volatile__(
1916 ".set noreorder\n\t"
1917 "tlbwi\n\t"
1918 ".set reorder");
1919 }
1920
1921 static inline void tlb_write_random(void)
1922 {
1923 __asm__ __volatile__(
1924 ".set noreorder\n\t"
1925 "tlbwr\n\t"
1926 ".set reorder");
1927 }
1928
1929 /*
1930 * Manipulate bits in a c0 register.
1931 */
1932 #define __BUILD_SET_C0(name) \
1933 static inline unsigned int \
1934 set_c0_##name(unsigned int set) \
1935 { \
1936 unsigned int res, new; \
1937 \
1938 res = read_c0_##name(); \
1939 new = res | set; \
1940 write_c0_##name(new); \
1941 \
1942 return res; \
1943 } \
1944 \
1945 static inline unsigned int \
1946 clear_c0_##name(unsigned int clear) \
1947 { \
1948 unsigned int res, new; \
1949 \
1950 res = read_c0_##name(); \
1951 new = res & ~clear; \
1952 write_c0_##name(new); \
1953 \
1954 return res; \
1955 } \
1956 \
1957 static inline unsigned int \
1958 change_c0_##name(unsigned int change, unsigned int val) \
1959 { \
1960 unsigned int res, new; \
1961 \
1962 res = read_c0_##name(); \
1963 new = res & ~change; \
1964 new |= (val & change); \
1965 write_c0_##name(new); \
1966 \
1967 return res; \
1968 }
1969
1970 __BUILD_SET_C0(status)
1971 __BUILD_SET_C0(cause)
1972 __BUILD_SET_C0(config)
1973 __BUILD_SET_C0(config5)
1974 __BUILD_SET_C0(intcontrol)
1975 __BUILD_SET_C0(intctl)
1976 __BUILD_SET_C0(srsmap)
1977 __BUILD_SET_C0(pagegrain)
1978 __BUILD_SET_C0(brcm_config_0)
1979 __BUILD_SET_C0(brcm_bus_pll)
1980 __BUILD_SET_C0(brcm_reset)
1981 __BUILD_SET_C0(brcm_cmt_intr)
1982 __BUILD_SET_C0(brcm_cmt_ctrl)
1983 __BUILD_SET_C0(brcm_config)
1984 __BUILD_SET_C0(brcm_mode)
1985
1986 /*
1987 * Return low 10 bits of ebase.
1988 * Note that under KVM (MIPSVZ) this returns vcpu id.
1989 */
1990 static inline unsigned int get_ebase_cpunum(void)
1991 {
1992 return read_c0_ebase() & 0x3ff;
1993 }
1994
1995 #endif /* !__ASSEMBLY__ */
1996
1997 #endif /* _ASM_MIPSREGS_H */
Linux with added FPC-III support