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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / bus / arm-ccn.c
blob4d523cfe51cee0416ec04517e8faf3c2c7722a61
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2014 ARM Limited
12 */
13
14 #include <linux/ctype.h>
15 #include <linux/hrtimer.h>
16 #include <linux/idr.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define CCN_NUM_XP_PORTS 2
25 #define CCN_NUM_VCS 4
26 #define CCN_NUM_REGIONS 256
27 #define CCN_REGION_SIZE 0x10000
28
29 #define CCN_ALL_OLY_ID 0xff00
30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
34
35 #define CCN_MN_ERRINT_STATUS 0x0008
36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
49
50 #define CCN_DT_ACTIVE_DSM 0x0000
51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
53 #define CCN_DT_CTL 0x0028
54 #define CCN_DT_CTL__DT_EN (1 << 0)
55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
56 #define CCN_DT_PMCCNTR 0x0140
57 #define CCN_DT_PMCCNTRSR 0x0190
58 #define CCN_DT_PMOVSR 0x0198
59 #define CCN_DT_PMOVSR_CLR 0x01a0
60 #define CCN_DT_PMOVSR_CLR__MASK 0x1f
61 #define CCN_DT_PMCR 0x01a8
62 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
63 #define CCN_DT_PMCR__PMU_EN (1 << 0)
64 #define CCN_DT_PMSR 0x01b0
65 #define CCN_DT_PMSR_REQ 0x01b8
66 #define CCN_DT_PMSR_CLR 0x01c0
67
68 #define CCN_HNF_PMU_EVENT_SEL 0x0600
69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
71
72 #define CCN_XP_DT_CONFIG 0x0300
73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
80 #define CCN_XP_DT_INTERFACE_SEL 0x0308
81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
87 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
88 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
89 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
90 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
91 #define CCN_XP_DT_CONTROL 0x0370
92 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
96 #define CCN_XP_PMU_EVENT_SEL 0x0600
97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
99
100 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
103
104 #define CCN_RNI_PMU_EVENT_SEL 0x0600
105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
107
108 #define CCN_TYPE_MN 0x01
109 #define CCN_TYPE_DT 0x02
110 #define CCN_TYPE_HNF 0x04
111 #define CCN_TYPE_HNI 0x05
112 #define CCN_TYPE_XP 0x08
113 #define CCN_TYPE_SBSX 0x0c
114 #define CCN_TYPE_SBAS 0x10
115 #define CCN_TYPE_RNI_1P 0x14
116 #define CCN_TYPE_RNI_2P 0x15
117 #define CCN_TYPE_RNI_3P 0x16
118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
119 #define CCN_TYPE_RND_2P 0x19
120 #define CCN_TYPE_RND_3P 0x1a
121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
122
123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
124
125 #define CCN_NUM_PMU_EVENTS 4
126 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
127 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
128 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
129
130 #define CCN_NUM_PREDEFINED_MASKS 4
131 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
132 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
133 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
134 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
135
136 struct arm_ccn_component {
137 void __iomem *base;
138 u32 type;
139
140 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
141 union {
142 struct {
143 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
144 } xp;
145 };
146 };
147
148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
149 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
150
151 struct arm_ccn_dt {
152 int id;
153 void __iomem *base;
154
155 spinlock_t config_lock;
156
157 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
158 struct {
159 struct arm_ccn_component *source;
160 struct perf_event *event;
161 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
162
163 struct {
164 u64 l, h;
165 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
166
167 struct hrtimer hrtimer;
168
169 struct pmu pmu;
170 };
171
172 struct arm_ccn {
173 struct device *dev;
174 void __iomem *base;
175 unsigned irq_used:1;
176 unsigned sbas_present:1;
177 unsigned sbsx_present:1;
178
179 int num_nodes;
180 struct arm_ccn_component *node;
181
182 int num_xps;
183 struct arm_ccn_component *xp;
184
185 struct arm_ccn_dt dt;
186 int mn_id;
187 };
188
189
190 static int arm_ccn_node_to_xp(int node)
191 {
192 return node / CCN_NUM_XP_PORTS;
193 }
194
195 static int arm_ccn_node_to_xp_port(int node)
196 {
197 return node % CCN_NUM_XP_PORTS;
198 }
199
200
201 /*
202 * Bit shifts and masks in these defines must be kept in sync with
203 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
204 */
205 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
206 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
207 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
208 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
209 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
210 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
211 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
212 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
213
214 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
215 {
216 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
217 *config |= (node_xp << 0) | (type << 8) | (port << 24);
218 }
219
220 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
221 struct device_attribute *attr, char *buf)
222 {
223 struct dev_ext_attribute *ea = container_of(attr,
224 struct dev_ext_attribute, attr);
225
226 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
227 }
228
229 #define CCN_FORMAT_ATTR(_name, _config) \
230 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
231 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
232 NULL), _config }
233
234 static CCN_FORMAT_ATTR(node, "config:0-7");
235 static CCN_FORMAT_ATTR(xp, "config:0-7");
236 static CCN_FORMAT_ATTR(type, "config:8-15");
237 static CCN_FORMAT_ATTR(event, "config:16-23");
238 static CCN_FORMAT_ATTR(port, "config:24-25");
239 static CCN_FORMAT_ATTR(vc, "config:26-28");
240 static CCN_FORMAT_ATTR(dir, "config:29-29");
241 static CCN_FORMAT_ATTR(mask, "config:30-33");
242 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
243 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
244
245 static struct attribute *arm_ccn_pmu_format_attrs[] = {
246 &arm_ccn_pmu_format_attr_node.attr.attr,
247 &arm_ccn_pmu_format_attr_xp.attr.attr,
248 &arm_ccn_pmu_format_attr_type.attr.attr,
249 &arm_ccn_pmu_format_attr_event.attr.attr,
250 &arm_ccn_pmu_format_attr_port.attr.attr,
251 &arm_ccn_pmu_format_attr_vc.attr.attr,
252 &arm_ccn_pmu_format_attr_dir.attr.attr,
253 &arm_ccn_pmu_format_attr_mask.attr.attr,
254 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
255 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
256 NULL
257 };
258
259 static struct attribute_group arm_ccn_pmu_format_attr_group = {
260 .name = "format",
261 .attrs = arm_ccn_pmu_format_attrs,
262 };
263
264
265 struct arm_ccn_pmu_event {
266 struct device_attribute attr;
267 u32 type;
268 u32 event;
269 int num_ports;
270 int num_vcs;
271 const char *def;
272 int mask;
273 };
274
275 #define CCN_EVENT_ATTR(_name) \
276 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
277
278 /*
279 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
280 * their ports in XP they are connected to. For the sake of usability they are
281 * explicitly defined here (and translated into a relevant watchpoint in
282 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
283 * knowledge of the flit format.
284 */
285
286 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
287 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
288 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
289 .def = _def, .mask = _mask, }
290
291 #define CCN_EVENT_HNI(_name, _def, _mask) { \
292 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
293 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
294 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
295
296 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
297 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
298 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
299 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
300
301 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
302 .type = CCN_TYPE_HNF, .event = _event, }
303
304 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
305 .type = CCN_TYPE_XP, .event = _event, \
306 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
307
308 /*
309 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
310 * on configuration. One of them is picked to represent the whole group,
311 * as they all share the same event types.
312 */
313 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
314 .type = CCN_TYPE_RNI_3P, .event = _event, }
315
316 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
317 .type = CCN_TYPE_SBAS, .event = _event, }
318
319 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
320 .type = CCN_TYPE_CYCLES }
321
322
323 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
324 struct device_attribute *attr, char *buf)
325 {
326 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
327 struct arm_ccn_pmu_event *event = container_of(attr,
328 struct arm_ccn_pmu_event, attr);
329 ssize_t res;
330
331 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
332 if (event->event)
333 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
334 event->event);
335 if (event->def)
336 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
337 event->def);
338 if (event->mask)
339 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
340 event->mask);
341
342 /* Arguments required by an event */
343 switch (event->type) {
344 case CCN_TYPE_CYCLES:
345 break;
346 case CCN_TYPE_XP:
347 res += snprintf(buf + res, PAGE_SIZE - res,
348 ",xp=?,port=?,vc=?,dir=?");
349 if (event->event == CCN_EVENT_WATCHPOINT)
350 res += snprintf(buf + res, PAGE_SIZE - res,
351 ",cmp_l=?,cmp_h=?,mask=?");
352 break;
353 case CCN_TYPE_MN:
354 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
355 break;
356 default:
357 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
358 break;
359 }
360
361 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
362
363 return res;
364 }
365
366 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
367 struct attribute *attr, int index)
368 {
369 struct device *dev = kobj_to_dev(kobj);
370 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
371 struct device_attribute *dev_attr = container_of(attr,
372 struct device_attribute, attr);
373 struct arm_ccn_pmu_event *event = container_of(dev_attr,
374 struct arm_ccn_pmu_event, attr);
375
376 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
377 return 0;
378 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
379 return 0;
380
381 return attr->mode;
382 }
383
384 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
385 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
386 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
387 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
388 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
389 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
390 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
391 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
392 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
393 CCN_IDX_MASK_ORDER),
394 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
395 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
396 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
397 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
398 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
399 CCN_IDX_MASK_ORDER),
400 CCN_EVENT_HNF(cache_miss, 0x1),
401 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
402 CCN_EVENT_HNF(cache_fill, 0x3),
403 CCN_EVENT_HNF(pocq_retry, 0x4),
404 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
405 CCN_EVENT_HNF(sf_hit, 0x6),
406 CCN_EVENT_HNF(sf_evictions, 0x7),
407 CCN_EVENT_HNF(snoops_sent, 0x8),
408 CCN_EVENT_HNF(snoops_broadcast, 0x9),
409 CCN_EVENT_HNF(l3_eviction, 0xa),
410 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
411 CCN_EVENT_HNF(mc_retries, 0xc),
412 CCN_EVENT_HNF(mc_reqs, 0xd),
413 CCN_EVENT_HNF(qos_hh_retry, 0xe),
414 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
415 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
416 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
417 CCN_EVENT_RNI(rxdat_flits, 0x4),
418 CCN_EVENT_RNI(txdat_flits, 0x5),
419 CCN_EVENT_RNI(txreq_flits, 0x6),
420 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
421 CCN_EVENT_RNI(rrt_full, 0x8),
422 CCN_EVENT_RNI(wrt_full, 0x9),
423 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
424 CCN_EVENT_XP(upload_starvation, 0x1),
425 CCN_EVENT_XP(download_starvation, 0x2),
426 CCN_EVENT_XP(respin, 0x3),
427 CCN_EVENT_XP(valid_flit, 0x4),
428 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
429 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
430 CCN_EVENT_SBAS(rxdat_flits, 0x4),
431 CCN_EVENT_SBAS(txdat_flits, 0x5),
432 CCN_EVENT_SBAS(txreq_flits, 0x6),
433 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
434 CCN_EVENT_SBAS(rrt_full, 0x8),
435 CCN_EVENT_SBAS(wrt_full, 0x9),
436 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
437 CCN_EVENT_CYCLES(cycles),
438 };
439
440 /* Populated in arm_ccn_init() */
441 static struct attribute
442 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
443
444 static struct attribute_group arm_ccn_pmu_events_attr_group = {
445 .name = "events",
446 .is_visible = arm_ccn_pmu_events_is_visible,
447 .attrs = arm_ccn_pmu_events_attrs,
448 };
449
450
451 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
452 {
453 unsigned long i;
454
455 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
456 return NULL;
457 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
458
459 switch (name[1]) {
460 case 'l':
461 return &ccn->dt.cmp_mask[i].l;
462 case 'h':
463 return &ccn->dt.cmp_mask[i].h;
464 default:
465 return NULL;
466 }
467 }
468
469 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
470 struct device_attribute *attr, char *buf)
471 {
472 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
473 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
474
475 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
476 }
477
478 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
479 struct device_attribute *attr, const char *buf, size_t count)
480 {
481 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
482 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
483 int err = -EINVAL;
484
485 if (mask)
486 err = kstrtoull(buf, 0, mask);
487
488 return err ? err : count;
489 }
490
491 #define CCN_CMP_MASK_ATTR(_name) \
492 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
493 __ATTR(_name, S_IRUGO | S_IWUSR, \
494 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
495
496 #define CCN_CMP_MASK_ATTR_RO(_name) \
497 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
498 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
499
500 static CCN_CMP_MASK_ATTR(0l);
501 static CCN_CMP_MASK_ATTR(0h);
502 static CCN_CMP_MASK_ATTR(1l);
503 static CCN_CMP_MASK_ATTR(1h);
504 static CCN_CMP_MASK_ATTR(2l);
505 static CCN_CMP_MASK_ATTR(2h);
506 static CCN_CMP_MASK_ATTR(3l);
507 static CCN_CMP_MASK_ATTR(3h);
508 static CCN_CMP_MASK_ATTR(4l);
509 static CCN_CMP_MASK_ATTR(4h);
510 static CCN_CMP_MASK_ATTR(5l);
511 static CCN_CMP_MASK_ATTR(5h);
512 static CCN_CMP_MASK_ATTR(6l);
513 static CCN_CMP_MASK_ATTR(6h);
514 static CCN_CMP_MASK_ATTR(7l);
515 static CCN_CMP_MASK_ATTR(7h);
516 static CCN_CMP_MASK_ATTR_RO(8l);
517 static CCN_CMP_MASK_ATTR_RO(8h);
518 static CCN_CMP_MASK_ATTR_RO(9l);
519 static CCN_CMP_MASK_ATTR_RO(9h);
520 static CCN_CMP_MASK_ATTR_RO(al);
521 static CCN_CMP_MASK_ATTR_RO(ah);
522 static CCN_CMP_MASK_ATTR_RO(bl);
523 static CCN_CMP_MASK_ATTR_RO(bh);
524
525 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
526 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
527 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
528 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
529 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
530 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
531 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
532 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
533 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
534 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
535 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
536 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
537 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
538 NULL
539 };
540
541 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
542 .name = "cmp_mask",
543 .attrs = arm_ccn_pmu_cmp_mask_attrs,
544 };
545
546
547 /*
548 * Default poll period is 10ms, which is way over the top anyway,
549 * as in the worst case scenario (an event every cycle), with 1GHz
550 * clocked bus, the smallest, 32 bit counter will overflow in
551 * more than 4s.
552 */
553 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
554 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
555 S_IRUGO | S_IWUSR);
556
557 static ktime_t arm_ccn_pmu_timer_period(void)
558 {
559 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
560 }
561
562
563 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
564 &arm_ccn_pmu_events_attr_group,
565 &arm_ccn_pmu_format_attr_group,
566 &arm_ccn_pmu_cmp_mask_attr_group,
567 NULL
568 };
569
570
571 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
572 {
573 int bit;
574
575 do {
576 bit = find_first_zero_bit(bitmap, size);
577 if (bit >= size)
578 return -EAGAIN;
579 } while (test_and_set_bit(bit, bitmap));
580
581 return bit;
582 }
583
584 /* All RN-I and RN-D nodes have identical PMUs */
585 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
586 {
587 if (a == b)
588 return 1;
589
590 switch (a) {
591 case CCN_TYPE_RNI_1P:
592 case CCN_TYPE_RNI_2P:
593 case CCN_TYPE_RNI_3P:
594 case CCN_TYPE_RND_1P:
595 case CCN_TYPE_RND_2P:
596 case CCN_TYPE_RND_3P:
597 switch (b) {
598 case CCN_TYPE_RNI_1P:
599 case CCN_TYPE_RNI_2P:
600 case CCN_TYPE_RNI_3P:
601 case CCN_TYPE_RND_1P:
602 case CCN_TYPE_RND_2P:
603 case CCN_TYPE_RND_3P:
604 return 1;
605 }
606 break;
607 }
608
609 return 0;
610 }
611
612 static void arm_ccn_pmu_event_destroy(struct perf_event *event)
613 {
614 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
615 struct hw_perf_event *hw = &event->hw;
616
617 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
618 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
619 } else {
620 struct arm_ccn_component *source =
621 ccn->dt.pmu_counters[hw->idx].source;
622
623 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
624 CCN_CONFIG_EVENT(event->attr.config) ==
625 CCN_EVENT_WATCHPOINT)
626 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
627 else
628 clear_bit(hw->config_base, source->pmu_events_mask);
629 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
630 }
631
632 ccn->dt.pmu_counters[hw->idx].source = NULL;
633 ccn->dt.pmu_counters[hw->idx].event = NULL;
634 }
635
636 static int arm_ccn_pmu_event_init(struct perf_event *event)
637 {
638 struct arm_ccn *ccn;
639 struct hw_perf_event *hw = &event->hw;
640 u32 node_xp, type, event_id;
641 int valid, bit;
642 struct arm_ccn_component *source;
643 int i;
644
645 if (event->attr.type != event->pmu->type)
646 return -ENOENT;
647
648 ccn = pmu_to_arm_ccn(event->pmu);
649 event->destroy = arm_ccn_pmu_event_destroy;
650
651 if (hw->sample_period) {
652 dev_warn(ccn->dev, "Sampling not supported!\n");
653 return -EOPNOTSUPP;
654 }
655
656 if (has_branch_stack(event) || event->attr.exclude_user ||
657 event->attr.exclude_kernel || event->attr.exclude_hv ||
658 event->attr.exclude_idle) {
659 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
660 return -EOPNOTSUPP;
661 }
662
663 if (event->cpu < 0) {
664 dev_warn(ccn->dev, "Can't provide per-task data!\n");
665 return -EOPNOTSUPP;
666 }
667
668 node_xp = CCN_CONFIG_NODE(event->attr.config);
669 type = CCN_CONFIG_TYPE(event->attr.config);
670 event_id = CCN_CONFIG_EVENT(event->attr.config);
671
672 /* Validate node/xp vs topology */
673 switch (type) {
674 case CCN_TYPE_MN:
675 if (node_xp != ccn->mn_id) {
676 dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
677 return -EINVAL;
678 }
679 break;
680 case CCN_TYPE_XP:
681 if (node_xp >= ccn->num_xps) {
682 dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
683 return -EINVAL;
684 }
685 break;
686 case CCN_TYPE_CYCLES:
687 break;
688 default:
689 if (node_xp >= ccn->num_nodes) {
690 dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
691 return -EINVAL;
692 }
693 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
694 dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
695 type, node_xp);
696 return -EINVAL;
697 }
698 break;
699 }
700
701 /* Validate event ID vs available for the type */
702 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
703 i++) {
704 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
705 u32 port = CCN_CONFIG_PORT(event->attr.config);
706 u32 vc = CCN_CONFIG_VC(event->attr.config);
707
708 if (!arm_ccn_pmu_type_eq(type, e->type))
709 continue;
710 if (event_id != e->event)
711 continue;
712 if (e->num_ports && port >= e->num_ports) {
713 dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
714 port, node_xp);
715 return -EINVAL;
716 }
717 if (e->num_vcs && vc >= e->num_vcs) {
718 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
719 vc, node_xp);
720 return -EINVAL;
721 }
722 valid = 1;
723 }
724 if (!valid) {
725 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
726 event_id, node_xp);
727 return -EINVAL;
728 }
729
730 /* Watchpoint-based event for a node is actually set on XP */
731 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
732 u32 port;
733
734 type = CCN_TYPE_XP;
735 port = arm_ccn_node_to_xp_port(node_xp);
736 node_xp = arm_ccn_node_to_xp(node_xp);
737
738 arm_ccn_pmu_config_set(&event->attr.config,
739 node_xp, type, port);
740 }
741
742 /* Allocate the cycle counter */
743 if (type == CCN_TYPE_CYCLES) {
744 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
745 ccn->dt.pmu_counters_mask))
746 return -EAGAIN;
747
748 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
749 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
750
751 return 0;
752 }
753
754 /* Allocate an event counter */
755 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
756 CCN_NUM_PMU_EVENT_COUNTERS);
757 if (hw->idx < 0) {
758 dev_warn(ccn->dev, "No more counters available!\n");
759 return -EAGAIN;
760 }
761
762 if (type == CCN_TYPE_XP)
763 source = &ccn->xp[node_xp];
764 else
765 source = &ccn->node[node_xp];
766 ccn->dt.pmu_counters[hw->idx].source = source;
767
768 /* Allocate an event source or a watchpoint */
769 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
770 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
771 CCN_NUM_XP_WATCHPOINTS);
772 else
773 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
774 CCN_NUM_PMU_EVENTS);
775 if (bit < 0) {
776 dev_warn(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
777 node_xp);
778 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
779 return -EAGAIN;
780 }
781 hw->config_base = bit;
782
783 ccn->dt.pmu_counters[hw->idx].event = event;
784
785 return 0;
786 }
787
788 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
789 {
790 u64 res;
791
792 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
793 #ifdef readq
794 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
795 #else
796 /* 40 bit counter, can do snapshot and read in two parts */
797 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
798 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
799 ;
800 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
801 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
802 res <<= 32;
803 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
804 #endif
805 } else {
806 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
807 }
808
809 return res;
810 }
811
812 static void arm_ccn_pmu_event_update(struct perf_event *event)
813 {
814 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
815 struct hw_perf_event *hw = &event->hw;
816 u64 prev_count, new_count, mask;
817
818 do {
819 prev_count = local64_read(&hw->prev_count);
820 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
821 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
822
823 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
824
825 local64_add((new_count - prev_count) & mask, &event->count);
826 }
827
828 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
829 {
830 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
831 struct hw_perf_event *hw = &event->hw;
832 struct arm_ccn_component *xp;
833 u32 val, dt_cfg;
834
835 /* Nothing to do for cycle counter */
836 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
837 return;
838
839 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
840 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
841 else
842 xp = &ccn->xp[arm_ccn_node_to_xp(
843 CCN_CONFIG_NODE(event->attr.config))];
844
845 if (enable)
846 dt_cfg = hw->event_base;
847 else
848 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
849
850 spin_lock(&ccn->dt.config_lock);
851
852 val = readl(xp->base + CCN_XP_DT_CONFIG);
853 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
854 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
855 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
856 writel(val, xp->base + CCN_XP_DT_CONFIG);
857
858 spin_unlock(&ccn->dt.config_lock);
859 }
860
861 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
862 {
863 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
864 struct hw_perf_event *hw = &event->hw;
865
866 local64_set(&event->hw.prev_count,
867 arm_ccn_pmu_read_counter(ccn, hw->idx));
868 hw->state = 0;
869
870 if (!ccn->irq_used)
871 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
872 HRTIMER_MODE_REL);
873
874 /* Set the DT bus input, engaging the counter */
875 arm_ccn_pmu_xp_dt_config(event, 1);
876 }
877
878 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
879 {
880 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
881 struct hw_perf_event *hw = &event->hw;
882 u64 timeout;
883
884 /* Disable counting, setting the DT bus to pass-through mode */
885 arm_ccn_pmu_xp_dt_config(event, 0);
886
887 if (!ccn->irq_used)
888 hrtimer_cancel(&ccn->dt.hrtimer);
889
890 /* Let the DT bus drain */
891 timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
892 ccn->num_xps;
893 while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
894 timeout)
895 cpu_relax();
896
897 if (flags & PERF_EF_UPDATE)
898 arm_ccn_pmu_event_update(event);
899
900 hw->state |= PERF_HES_STOPPED;
901 }
902
903 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
904 {
905 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
906 struct hw_perf_event *hw = &event->hw;
907 struct arm_ccn_component *source =
908 ccn->dt.pmu_counters[hw->idx].source;
909 unsigned long wp = hw->config_base;
910 u32 val;
911 u64 cmp_l = event->attr.config1;
912 u64 cmp_h = event->attr.config2;
913 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
914 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
915
916 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
917
918 /* Direction (RX/TX), device (port) & virtual channel */
919 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
920 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
921 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
922 val |= CCN_CONFIG_DIR(event->attr.config) <<
923 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
924 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
925 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
926 val |= CCN_CONFIG_PORT(event->attr.config) <<
927 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
928 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
929 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
930 val |= CCN_CONFIG_VC(event->attr.config) <<
931 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
932 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
933
934 /* Comparison values */
935 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
936 writel((cmp_l >> 32) & 0x7fffffff,
937 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
938 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
939 writel((cmp_h >> 32) & 0x0fffffff,
940 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
941
942 /* Mask */
943 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
944 writel((mask_l >> 32) & 0x7fffffff,
945 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
946 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
947 writel((mask_h >> 32) & 0x0fffffff,
948 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
949 }
950
951 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
952 {
953 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
954 struct hw_perf_event *hw = &event->hw;
955 struct arm_ccn_component *source =
956 ccn->dt.pmu_counters[hw->idx].source;
957 u32 val, id;
958
959 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
960
961 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
962 (CCN_CONFIG_PORT(event->attr.config) << 3) |
963 (CCN_CONFIG_EVENT(event->attr.config) << 0);
964
965 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
966 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
967 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
968 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
969 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
970 }
971
972 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
973 {
974 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
975 struct hw_perf_event *hw = &event->hw;
976 struct arm_ccn_component *source =
977 ccn->dt.pmu_counters[hw->idx].source;
978 u32 type = CCN_CONFIG_TYPE(event->attr.config);
979 u32 val, port;
980
981 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
982 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
983 hw->config_base);
984
985 /* These *_event_sel regs should be identical, but let's make sure... */
986 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
987 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
988 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
989 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
990 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
991 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
992 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
993 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
994 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
995 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
996 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
997 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
998 return;
999
1000 /* Set the event id for the pre-allocated counter */
1001 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1002 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1003 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1004 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1005 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1006 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1007 }
1008
1009 static void arm_ccn_pmu_event_config(struct perf_event *event)
1010 {
1011 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1012 struct hw_perf_event *hw = &event->hw;
1013 u32 xp, offset, val;
1014
1015 /* Cycle counter requires no setup */
1016 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1017 return;
1018
1019 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1020 xp = CCN_CONFIG_XP(event->attr.config);
1021 else
1022 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1023
1024 spin_lock(&ccn->dt.config_lock);
1025
1026 /* Set the DT bus "distance" register */
1027 offset = (hw->idx / 4) * 4;
1028 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1029 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1030 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1031 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1032 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1033
1034 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1035 if (CCN_CONFIG_EVENT(event->attr.config) ==
1036 CCN_EVENT_WATCHPOINT)
1037 arm_ccn_pmu_xp_watchpoint_config(event);
1038 else
1039 arm_ccn_pmu_xp_event_config(event);
1040 } else {
1041 arm_ccn_pmu_node_event_config(event);
1042 }
1043
1044 spin_unlock(&ccn->dt.config_lock);
1045 }
1046
1047 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1048 {
1049 struct hw_perf_event *hw = &event->hw;
1050
1051 arm_ccn_pmu_event_config(event);
1052
1053 hw->state = PERF_HES_STOPPED;
1054
1055 if (flags & PERF_EF_START)
1056 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1057
1058 return 0;
1059 }
1060
1061 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1062 {
1063 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1064 }
1065
1066 static void arm_ccn_pmu_event_read(struct perf_event *event)
1067 {
1068 arm_ccn_pmu_event_update(event);
1069 }
1070
1071 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1072 {
1073 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1074 int idx;
1075
1076 if (!pmovsr)
1077 return IRQ_NONE;
1078
1079 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1080
1081 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1082
1083 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1084 struct perf_event *event = dt->pmu_counters[idx].event;
1085 int overflowed = pmovsr & BIT(idx);
1086
1087 WARN_ON_ONCE(overflowed && !event &&
1088 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1089
1090 if (!event || !overflowed)
1091 continue;
1092
1093 arm_ccn_pmu_event_update(event);
1094 }
1095
1096 return IRQ_HANDLED;
1097 }
1098
1099 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1100 {
1101 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1102 hrtimer);
1103 unsigned long flags;
1104
1105 local_irq_save(flags);
1106 arm_ccn_pmu_overflow_handler(dt);
1107 local_irq_restore(flags);
1108
1109 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1110 return HRTIMER_RESTART;
1111 }
1112
1113
1114 static DEFINE_IDA(arm_ccn_pmu_ida);
1115
1116 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1117 {
1118 int i;
1119 char *name;
1120
1121 /* Initialize DT subsystem */
1122 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1123 spin_lock_init(&ccn->dt.config_lock);
1124 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1125 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1126 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1127 ccn->dt.base + CCN_DT_PMCR);
1128 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1129 for (i = 0; i < ccn->num_xps; i++) {
1130 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1131 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1132 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1133 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1134 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1135 CCN_XP_DT_CONTROL__DT_ENABLE,
1136 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1137 }
1138 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1139 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1140 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1141 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1142 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1143 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1144 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1145 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1146
1147 /* Get a convenient /sys/event_source/devices/ name */
1148 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1149 if (ccn->dt.id == 0) {
1150 name = "ccn";
1151 } else {
1152 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1153
1154 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1155 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1156 }
1157
1158 /* Perf driver registration */
1159 ccn->dt.pmu = (struct pmu) {
1160 .attr_groups = arm_ccn_pmu_attr_groups,
1161 .task_ctx_nr = perf_invalid_context,
1162 .event_init = arm_ccn_pmu_event_init,
1163 .add = arm_ccn_pmu_event_add,
1164 .del = arm_ccn_pmu_event_del,
1165 .start = arm_ccn_pmu_event_start,
1166 .stop = arm_ccn_pmu_event_stop,
1167 .read = arm_ccn_pmu_event_read,
1168 };
1169
1170 /* No overflow interrupt? Have to use a timer instead. */
1171 if (!ccn->irq_used) {
1172 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1173 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1174 HRTIMER_MODE_REL);
1175 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1176 }
1177
1178 return perf_pmu_register(&ccn->dt.pmu, name, -1);
1179 }
1180
1181 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1182 {
1183 int i;
1184
1185 for (i = 0; i < ccn->num_xps; i++)
1186 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1187 writel(0, ccn->dt.base + CCN_DT_PMCR);
1188 perf_pmu_unregister(&ccn->dt.pmu);
1189 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1190 }
1191
1192
1193 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1194 int (*callback)(struct arm_ccn *ccn, int region,
1195 void __iomem *base, u32 type, u32 id))
1196 {
1197 int region;
1198
1199 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1200 u32 val, type, id;
1201 void __iomem *base;
1202 int err;
1203
1204 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1205 4 * (region / 32));
1206 if (!(val & (1 << (region % 32))))
1207 continue;
1208
1209 base = ccn->base + region * CCN_REGION_SIZE;
1210 val = readl(base + CCN_ALL_OLY_ID);
1211 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1212 CCN_ALL_OLY_ID__OLY_ID__MASK;
1213 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1214 CCN_ALL_OLY_ID__NODE_ID__MASK;
1215
1216 err = callback(ccn, region, base, type, id);
1217 if (err)
1218 return err;
1219 }
1220
1221 return 0;
1222 }
1223
1224 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1225 void __iomem *base, u32 type, u32 id)
1226 {
1227
1228 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1229 ccn->num_xps = id + 1;
1230 else if (id >= ccn->num_nodes)
1231 ccn->num_nodes = id + 1;
1232
1233 return 0;
1234 }
1235
1236 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1237 void __iomem *base, u32 type, u32 id)
1238 {
1239 struct arm_ccn_component *component;
1240
1241 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1242
1243 switch (type) {
1244 case CCN_TYPE_MN:
1245 ccn->mn_id = id;
1246 return 0;
1247 case CCN_TYPE_DT:
1248 return 0;
1249 case CCN_TYPE_XP:
1250 component = &ccn->xp[id];
1251 break;
1252 case CCN_TYPE_SBSX:
1253 ccn->sbsx_present = 1;
1254 component = &ccn->node[id];
1255 break;
1256 case CCN_TYPE_SBAS:
1257 ccn->sbas_present = 1;
1258 /* Fall-through */
1259 default:
1260 component = &ccn->node[id];
1261 break;
1262 }
1263
1264 component->base = base;
1265 component->type = type;
1266
1267 return 0;
1268 }
1269
1270
1271 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1272 const u32 *err_sig_val)
1273 {
1274 /* This should be really handled by firmware... */
1275 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1276 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1277 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1278 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1279 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1280 ccn->base + CCN_MN_ERRINT_STATUS);
1281
1282 return IRQ_HANDLED;
1283 }
1284
1285
1286 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1287 {
1288 irqreturn_t res = IRQ_NONE;
1289 struct arm_ccn *ccn = dev_id;
1290 u32 err_sig_val[6];
1291 u32 err_or;
1292 int i;
1293
1294 /* PMU overflow is a special case */
1295 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1296 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1297 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1298 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1299 }
1300
1301 /* Have to read all err_sig_vals to clear them */
1302 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1303 err_sig_val[i] = readl(ccn->base +
1304 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1305 err_or |= err_sig_val[i];
1306 }
1307 if (err_or)
1308 res |= arm_ccn_error_handler(ccn, err_sig_val);
1309
1310 if (res != IRQ_NONE)
1311 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1312 ccn->base + CCN_MN_ERRINT_STATUS);
1313
1314 return res;
1315 }
1316
1317
1318 static int arm_ccn_probe(struct platform_device *pdev)
1319 {
1320 struct arm_ccn *ccn;
1321 struct resource *res;
1322 int err;
1323
1324 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1325 if (!ccn)
1326 return -ENOMEM;
1327 ccn->dev = &pdev->dev;
1328 platform_set_drvdata(pdev, ccn);
1329
1330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 if (!res)
1332 return -EINVAL;
1333
1334 if (!devm_request_mem_region(ccn->dev, res->start,
1335 resource_size(res), pdev->name))
1336 return -EBUSY;
1337
1338 ccn->base = devm_ioremap(ccn->dev, res->start,
1339 resource_size(res));
1340 if (!ccn->base)
1341 return -EFAULT;
1342
1343 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1344 if (!res)
1345 return -EINVAL;
1346
1347 /* Check if we can use the interrupt */
1348 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1349 ccn->base + CCN_MN_ERRINT_STATUS);
1350 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1351 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1352 /* Can set 'disable' bits, so can acknowledge interrupts */
1353 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1354 ccn->base + CCN_MN_ERRINT_STATUS);
1355 err = devm_request_irq(ccn->dev, res->start,
1356 arm_ccn_irq_handler, 0, dev_name(ccn->dev),
1357 ccn);
1358 if (err)
1359 return err;
1360
1361 ccn->irq_used = 1;
1362 }
1363
1364
1365 /* Build topology */
1366
1367 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1368 if (err)
1369 return err;
1370
1371 ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1372 GFP_KERNEL);
1373 ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1374 GFP_KERNEL);
1375 if (!ccn->node || !ccn->xp)
1376 return -ENOMEM;
1377
1378 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1379 if (err)
1380 return err;
1381
1382 return arm_ccn_pmu_init(ccn);
1383 }
1384
1385 static int arm_ccn_remove(struct platform_device *pdev)
1386 {
1387 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1388
1389 arm_ccn_pmu_cleanup(ccn);
1390
1391 return 0;
1392 }
1393
1394 static const struct of_device_id arm_ccn_match[] = {
1395 { .compatible = "arm,ccn-504", },
1396 {},
1397 };
1398
1399 static struct platform_driver arm_ccn_driver = {
1400 .driver = {
1401 .name = "arm-ccn",
1402 .of_match_table = arm_ccn_match,
1403 },
1404 .probe = arm_ccn_probe,
1405 .remove = arm_ccn_remove,
1406 };
1407
1408 static int __init arm_ccn_init(void)
1409 {
1410 int i;
1411
1412 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1413 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1414
1415 return platform_driver_register(&arm_ccn_driver);
1416 }
1417
1418 static void __exit arm_ccn_exit(void)
1419 {
1420 platform_driver_unregister(&arm_ccn_driver);
1421 }
1422
1423 module_init(arm_ccn_init);
1424 module_exit(arm_ccn_exit);
1425
1426 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1427 MODULE_LICENSE("GPL");
Linux with added FPC-III support