drivers/clocksource/timer-u300.c

   1 /*
   2  * Copyright (C) 2007-2009 ST-Ericsson AB
   3  * License terms: GNU General Public License (GPL) version 2
   4  * Timer COH 901 328, runs the OS timer interrupt.
   5  * Author: Linus Walleij <linus.walleij@stericsson.com>
   6  */
   7 #include <linux/interrupt.h>
   8 #include <linux/time.h>
   9 #include <linux/timex.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/clocksource.h>
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/irq.h>
  17 #include <linux/delay.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/sched_clock.h>
  21
  22 /* Generic stuff */
  23 #include <asm/mach/map.h>
  24 #include <asm/mach/time.h>
  25
  26 /*
  27  * APP side special timer registers
  28  * This timer contains four timers which can fire an interrupt each.
  29  * OS (operating system) timer @ 32768 Hz
  30  * DD (device driver) timer @ 1 kHz
  31  * GP1 (general purpose 1) timer @ 1MHz
  32  * GP2 (general purpose 2) timer @ 1MHz
  33  */
  34
  35 /* Reset OS Timer 32bit (-/W) */
  36 #define U300_TIMER_APP_ROST                                     (0x0000)
  37 #define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  38 /* Enable OS Timer 32bit (-/W) */
  39 #define U300_TIMER_APP_EOST                                     (0x0004)
  40 #define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  41 /* Disable OS Timer 32bit (-/W) */
  42 #define U300_TIMER_APP_DOST                                     (0x0008)
  43 #define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  44 /* OS Timer Mode Register 32bit (-/W) */
  45 #define U300_TIMER_APP_SOSTM                                    (0x000c)
  46 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  47 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  48 /* OS Timer Status Register 32bit (R/-) */
  49 #define U300_TIMER_APP_OSTS                                     (0x0010)
  50 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  51 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  52 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  53 #define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  54 #define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  55 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  56 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  57 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  58 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  59 /* OS Timer Current Count Register 32bit (R/-) */
  60 #define U300_TIMER_APP_OSTCC                                    (0x0014)
  61 /* OS Timer Terminal Count Register 32bit (R/W) */
  62 #define U300_TIMER_APP_OSTTC                                    (0x0018)
  63 /* OS Timer Interrupt Enable Register 32bit (-/W) */
  64 #define U300_TIMER_APP_OSTIE                                    (0x001c)
  65 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  66 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  67 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  68 #define U300_TIMER_APP_OSTIA                                    (0x0020)
  69 #define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  70
  71 /* Reset DD Timer 32bit (-/W) */
  72 #define U300_TIMER_APP_RDDT                                     (0x0040)
  73 #define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  74 /* Enable DD Timer 32bit (-/W) */
  75 #define U300_TIMER_APP_EDDT                                     (0x0044)
  76 #define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  77 /* Disable DD Timer 32bit (-/W) */
  78 #define U300_TIMER_APP_DDDT                                     (0x0048)
  79 #define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  80 /* DD Timer Mode Register 32bit (-/W) */
  81 #define U300_TIMER_APP_SDDTM                                    (0x004c)
  82 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  83 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  84 /* DD Timer Status Register 32bit (R/-) */
  85 #define U300_TIMER_APP_DDTS                                     (0x0050)
  86 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  87 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  88 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  89 #define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  90 #define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
  91 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
  92 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
  93 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
  94 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
  95 /* DD Timer Current Count Register 32bit (R/-) */
  96 #define U300_TIMER_APP_DDTCC                                    (0x0054)
  97 /* DD Timer Terminal Count Register 32bit (R/W) */
  98 #define U300_TIMER_APP_DDTTC                                    (0x0058)
  99 /* DD Timer Interrupt Enable Register 32bit (-/W) */
 100 #define U300_TIMER_APP_DDTIE                                    (0x005c)
 101 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 102 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 103 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 104 #define U300_TIMER_APP_DDTIA                                    (0x0060)
 105 #define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 106
 107 /* Reset GP1 Timer 32bit (-/W) */
 108 #define U300_TIMER_APP_RGPT1                                    (0x0080)
 109 #define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 110 /* Enable GP1 Timer 32bit (-/W) */
 111 #define U300_TIMER_APP_EGPT1                                    (0x0084)
 112 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 113 /* Disable GP1 Timer 32bit (-/W) */
 114 #define U300_TIMER_APP_DGPT1                                    (0x0088)
 115 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 116 /* GP1 Timer Mode Register 32bit (-/W) */
 117 #define U300_TIMER_APP_SGPT1M                                   (0x008c)
 118 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 119 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 120 /* GP1 Timer Status Register 32bit (R/-) */
 121 #define U300_TIMER_APP_GPT1S                                    (0x0090)
 122 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 123 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 124 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 125 #define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 126 #define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 127 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 128 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 129 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 130 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 131 /* GP1 Timer Current Count Register 32bit (R/-) */
 132 #define U300_TIMER_APP_GPT1CC                                   (0x0094)
 133 /* GP1 Timer Terminal Count Register 32bit (R/W) */
 134 #define U300_TIMER_APP_GPT1TC                                   (0x0098)
 135 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 136 #define U300_TIMER_APP_GPT1IE                                   (0x009c)
 137 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 138 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 139 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 140 #define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 141 #define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 142
 143 /* Reset GP2 Timer 32bit (-/W) */
 144 #define U300_TIMER_APP_RGPT2                                    (0x00c0)
 145 #define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 146 /* Enable GP2 Timer 32bit (-/W) */
 147 #define U300_TIMER_APP_EGPT2                                    (0x00c4)
 148 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 149 /* Disable GP2 Timer 32bit (-/W) */
 150 #define U300_TIMER_APP_DGPT2                                    (0x00c8)
 151 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 152 /* GP2 Timer Mode Register 32bit (-/W) */
 153 #define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 154 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 155 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 156 /* GP2 Timer Status Register 32bit (R/-) */
 157 #define U300_TIMER_APP_GPT2S                                    (0x00d0)
 158 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 159 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 160 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 161 #define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 162 #define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 163 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 164 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 165 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 166 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 167 /* GP2 Timer Current Count Register 32bit (R/-) */
 168 #define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 169 /* GP2 Timer Terminal Count Register 32bit (R/W) */
 170 #define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 171 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 172 #define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 173 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 174 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 175 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 176 #define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 177 #define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 178
 179 /* Clock request control register - all four timers */
 180 #define U300_TIMER_APP_CRC                                      (0x100)
 181 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 182
 183 static void __iomem *u300_timer_base;
 184
 185 struct u300_clockevent_data {
 186         struct clock_event_device cevd;
 187         unsigned ticks_per_jiffy;
 188 };
 189
 190 /*
 191  * The u300_set_mode() function is always called first, if we
 192  * have oneshot timer active, the oneshot scheduling function
 193  * u300_set_next_event() is called immediately after.
 194  */
 195 static void u300_set_mode(enum clock_event_mode mode,
 196                           struct clock_event_device *evt)
 197 {
 198         struct u300_clockevent_data *cevdata =
 199                 container_of(evt, struct u300_clockevent_data, cevd);
 200
 201         switch (mode) {
 202         case CLOCK_EVT_MODE_PERIODIC:
 203                 /* Disable interrupts on GPT1 */
 204                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 205                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 206                 /* Disable GP1 while we're reprogramming it. */
 207                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 208                        u300_timer_base + U300_TIMER_APP_DGPT1);
 209                 /*
 210                  * Set the periodic mode to a certain number of ticks per
 211                  * jiffy.
 212                  */
 213                 writel(cevdata->ticks_per_jiffy,
 214                        u300_timer_base + U300_TIMER_APP_GPT1TC);
 215                 /*
 216                  * Set continuous mode, so the timer keeps triggering
 217                  * interrupts.
 218                  */
 219                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 220                        u300_timer_base + U300_TIMER_APP_SGPT1M);
 221                 /* Enable timer interrupts */
 222                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 223                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 224                 /* Then enable the OS timer again */
 225                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 226                        u300_timer_base + U300_TIMER_APP_EGPT1);
 227                 break;
 228         case CLOCK_EVT_MODE_ONESHOT:
 229                 /* Just break; here? */
 230                 /*
 231                  * The actual event will be programmed by the next event hook,
 232                  * so we just set a dummy value somewhere at the end of the
 233                  * universe here.
 234                  */
 235                 /* Disable interrupts on GPT1 */
 236                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 237                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 238                 /* Disable GP1 while we're reprogramming it. */
 239                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 240                        u300_timer_base + U300_TIMER_APP_DGPT1);
 241                 /*
 242                  * Expire far in the future, u300_set_next_event() will be
 243                  * called soon...
 244                  */
 245                 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
 246                 /* We run one shot per tick here! */
 247                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 248                        u300_timer_base + U300_TIMER_APP_SGPT1M);
 249                 /* Enable interrupts for this timer */
 250                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 251                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 252                 /* Enable timer */
 253                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 254                        u300_timer_base + U300_TIMER_APP_EGPT1);
 255                 break;
 256         case CLOCK_EVT_MODE_UNUSED:
 257         case CLOCK_EVT_MODE_SHUTDOWN:
 258                 /* Disable interrupts on GP1 */
 259                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 260                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 261                 /* Disable GP1 */
 262                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 263                        u300_timer_base + U300_TIMER_APP_DGPT1);
 264                 break;
 265         case CLOCK_EVT_MODE_RESUME:
 266                 /* Ignore this call */
 267                 break;
 268         }
 269 }
 270
 271 /*
 272  * The app timer in one shot mode obviously has to be reprogrammed
 273  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 274  * the interrupt disable + timer disable commands with a reset command,
 275  * it will fail miserably. Apparently (and I found this the hard way)
 276  * the timer is very sensitive to the instruction order, though you don't
 277  * get that impression from the data sheet.
 278  */
 279 static int u300_set_next_event(unsigned long cycles,
 280                                struct clock_event_device *evt)
 281
 282 {
 283         /* Disable interrupts on GPT1 */
 284         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 285                u300_timer_base + U300_TIMER_APP_GPT1IE);
 286         /* Disable GP1 while we're reprogramming it. */
 287         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 288                u300_timer_base + U300_TIMER_APP_DGPT1);
 289         /* Reset the General Purpose timer 1. */
 290         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 291                u300_timer_base + U300_TIMER_APP_RGPT1);
 292         /* IRQ in n * cycles */
 293         writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
 294         /*
 295          * We run one shot per tick here! (This is necessary to reconfigure,
 296          * the timer will tilt if you don't!)
 297          */
 298         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 299                u300_timer_base + U300_TIMER_APP_SGPT1M);
 300         /* Enable timer interrupts */
 301         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 302                u300_timer_base + U300_TIMER_APP_GPT1IE);
 303         /* Then enable the OS timer again */
 304         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 305                u300_timer_base + U300_TIMER_APP_EGPT1);
 306         return 0;
 307 }
 308
 309 static struct u300_clockevent_data u300_clockevent_data = {
 310         /* Use general purpose timer 1 as clock event */
 311         .cevd = {
 312                 .name           = "GPT1",
 313                 /* Reasonably fast and accurate clock event */
 314                 .rating         = 300,
 315                 .features       = CLOCK_EVT_FEAT_PERIODIC |
 316                         CLOCK_EVT_FEAT_ONESHOT,
 317                 .set_next_event = u300_set_next_event,
 318                 .set_mode       = u300_set_mode,
 319         },
 320 };
 321
 322 /* Clock event timer interrupt handler */
 323 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 324 {
 325         struct clock_event_device *evt = &u300_clockevent_data.cevd;
 326         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 327
 328         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 329                 u300_timer_base + U300_TIMER_APP_GPT1IA);
 330         evt->event_handler(evt);
 331         return IRQ_HANDLED;
 332 }
 333
 334 static struct irqaction u300_timer_irq = {
 335         .name           = "U300 Timer Tick",
 336         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 337         .handler        = u300_timer_interrupt,
 338 };
 339
 340 /*
 341  * Override the global weak sched_clock symbol with this
 342  * local implementation which uses the clocksource to get some
 343  * better resolution when scheduling the kernel. We accept that
 344  * this wraps around for now, since it is just a relative time
 345  * stamp. (Inspired by OMAP implementation.)
 346  */
 347
 348 static u64 notrace u300_read_sched_clock(void)
 349 {
 350         return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 351 }
 352
 353 static unsigned long u300_read_current_timer(void)
 354 {
 355         return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 356 }
 357
 358 static struct delay_timer u300_delay_timer;
 359
 360 /*
 361  * This sets up the system timers, clock source and clock event.
 362  */
 363 static void __init u300_timer_init_of(struct device_node *np)
 364 {
 365         unsigned int irq;
 366         struct clk *clk;
 367         unsigned long rate;
 368
 369         u300_timer_base = of_iomap(np, 0);
 370         if (!u300_timer_base)
 371                 panic("could not ioremap system timer\n");
 372
 373         /* Get the IRQ for the GP1 timer */
 374         irq = irq_of_parse_and_map(np, 2);
 375         if (!irq)
 376                 panic("no IRQ for system timer\n");
 377
 378         pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);
 379
 380         /* Clock the interrupt controller */
 381         clk = of_clk_get(np, 0);
 382         BUG_ON(IS_ERR(clk));
 383         clk_prepare_enable(clk);
 384         rate = clk_get_rate(clk);
 385
 386         u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
 387
 388         sched_clock_register(u300_read_sched_clock, 32, rate);
 389
 390         u300_delay_timer.read_current_timer = &u300_read_current_timer;
 391         u300_delay_timer.freq = rate;
 392         register_current_timer_delay(&u300_delay_timer);
 393
 394         /*
 395          * Disable the "OS" and "DD" timers - these are designed for Symbian!
 396          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 397          */
 398         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 399                 u300_timer_base + U300_TIMER_APP_CRC);
 400         writel(U300_TIMER_APP_ROST_TIMER_RESET,
 401                 u300_timer_base + U300_TIMER_APP_ROST);
 402         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 403                 u300_timer_base + U300_TIMER_APP_DOST);
 404         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 405                 u300_timer_base + U300_TIMER_APP_RDDT);
 406         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 407                 u300_timer_base + U300_TIMER_APP_DDDT);
 408
 409         /* Reset the General Purpose timer 1. */
 410         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 411                 u300_timer_base + U300_TIMER_APP_RGPT1);
 412
 413         /* Set up the IRQ handler */
 414         setup_irq(irq, &u300_timer_irq);
 415
 416         /* Reset the General Purpose timer 2 */
 417         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 418                 u300_timer_base + U300_TIMER_APP_RGPT2);
 419         /* Set this timer to run around forever */
 420         writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
 421         /* Set continuous mode so it wraps around */
 422         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 423                u300_timer_base + U300_TIMER_APP_SGPT2M);
 424         /* Disable timer interrupts */
 425         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 426                 u300_timer_base + U300_TIMER_APP_GPT2IE);
 427         /* Then enable the GP2 timer to use as a free running us counter */
 428         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 429                 u300_timer_base + U300_TIMER_APP_EGPT2);
 430
 431         /* Use general purpose timer 2 as clock source */
 432         if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
 433                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 434                 pr_err("timer: failed to initialize U300 clock source\n");
 435
 436         /* Configure and register the clockevent */
 437         clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
 438                                         1, 0xffffffff);
 439
 440         /*
 441          * TODO: init and register the rest of the timers too, they can be
 442          * used by hrtimers!
 443          */
 444 }
 445
 446 CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
 447                        u300_timer_init_of);