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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / edac / sb_edac.c
blobcb46c468b01ec1967366160e5b3fed3f82347b0b
1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab
11 */
12
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
25 #include <asm/mce.h>
26
27 #include "edac_core.h"
28
29 /* Static vars */
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
32 static int probed;
33
34 /*
35 * Alter this version for the module when modifications are made
36 */
37 #define SBRIDGE_REVISION " Ver: 1.1.0 "
38 #define EDAC_MOD_STR "sbridge_edac"
39
40 /*
41 * Debug macros
42 */
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49 /*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
54
55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
56 static const u32 sbridge_dram_rule[] = {
57 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59 };
60
61 static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66 };
67
68 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
69 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
70 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
71 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
72 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
73
74 static char *get_dram_attr(u32 reg)
75 {
76 switch(DRAM_ATTR(reg)) {
77 case 0:
78 return "DRAM";
79 case 1:
80 return "MMCFG";
81 case 2:
82 return "NXM";
83 default:
84 return "unknown";
85 }
86 }
87
88 static const u32 sbridge_interleave_list[] = {
89 0x84, 0x8c, 0x94, 0x9c, 0xa4,
90 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
91 };
92
93 static const u32 ibridge_interleave_list[] = {
94 0x64, 0x6c, 0x74, 0x7c, 0x84,
95 0x8c, 0x94, 0x9c, 0xa4, 0xac,
96 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
97 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
98 };
99
100 struct interleave_pkg {
101 unsigned char start;
102 unsigned char end;
103 };
104
105 static const struct interleave_pkg sbridge_interleave_pkg[] = {
106 { 0, 2 },
107 { 3, 5 },
108 { 8, 10 },
109 { 11, 13 },
110 { 16, 18 },
111 { 19, 21 },
112 { 24, 26 },
113 { 27, 29 },
114 };
115
116 static const struct interleave_pkg ibridge_interleave_pkg[] = {
117 { 0, 3 },
118 { 4, 7 },
119 { 8, 11 },
120 { 12, 15 },
121 { 16, 19 },
122 { 20, 23 },
123 { 24, 27 },
124 { 28, 31 },
125 };
126
127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
128 int interleave)
129 {
130 return GET_BITFIELD(reg, table[interleave].start,
131 table[interleave].end);
132 }
133
134 /* Devices 12 Function 7 */
135
136 #define TOLM 0x80
137 #define TOHM 0x84
138 #define HASWELL_TOLM 0xd0
139 #define HASWELL_TOHM_0 0xd4
140 #define HASWELL_TOHM_1 0xd8
141
142 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
143 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
144
145 /* Device 13 Function 6 */
146
147 #define SAD_TARGET 0xf0
148
149 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
150
151 #define SAD_CONTROL 0xf4
152
153 /* Device 14 function 0 */
154
155 static const u32 tad_dram_rule[] = {
156 0x40, 0x44, 0x48, 0x4c,
157 0x50, 0x54, 0x58, 0x5c,
158 0x60, 0x64, 0x68, 0x6c,
159 };
160 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
161
162 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
163 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
164 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
165 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
166 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
167 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
168 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
169
170 /* Device 15, function 0 */
171
172 #define MCMTR 0x7c
173
174 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
175 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
176 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
177
178 /* Device 15, function 1 */
179
180 #define RASENABLES 0xac
181 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
182
183 /* Device 15, functions 2-5 */
184
185 static const int mtr_regs[] = {
186 0x80, 0x84, 0x88,
187 };
188
189 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
190 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
191 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
192 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
193 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
194
195 static const u32 tad_ch_nilv_offset[] = {
196 0x90, 0x94, 0x98, 0x9c,
197 0xa0, 0xa4, 0xa8, 0xac,
198 0xb0, 0xb4, 0xb8, 0xbc,
199 };
200 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
201 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
202
203 static const u32 rir_way_limit[] = {
204 0x108, 0x10c, 0x110, 0x114, 0x118,
205 };
206 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
207
208 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
209 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
210
211 #define MAX_RIR_WAY 8
212
213 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
214 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
215 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
216 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
217 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
218 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
219 };
220
221 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
222 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
223
224 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
225 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
226
227 /* Device 16, functions 2-7 */
228
229 /*
230 * FIXME: Implement the error count reads directly
231 */
232
233 static const u32 correrrcnt[] = {
234 0x104, 0x108, 0x10c, 0x110,
235 };
236
237 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
238 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
239 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
240 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
241
242 static const u32 correrrthrsld[] = {
243 0x11c, 0x120, 0x124, 0x128,
244 };
245
246 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
247 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
248
249
250 /* Device 17, function 0 */
251
252 #define SB_RANK_CFG_A 0x0328
253
254 #define IB_RANK_CFG_A 0x0320
255
256 /*
257 * sbridge structs
258 */
259
260 #define NUM_CHANNELS 4
261 #define MAX_DIMMS 3 /* Max DIMMS per channel */
262 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
263
264 enum type {
265 SANDY_BRIDGE,
266 IVY_BRIDGE,
267 HASWELL,
268 BROADWELL,
269 };
270
271 struct sbridge_pvt;
272 struct sbridge_info {
273 enum type type;
274 u32 mcmtr;
275 u32 rankcfgr;
276 u64 (*get_tolm)(struct sbridge_pvt *pvt);
277 u64 (*get_tohm)(struct sbridge_pvt *pvt);
278 u64 (*rir_limit)(u32 reg);
279 const u32 *dram_rule;
280 const u32 *interleave_list;
281 const struct interleave_pkg *interleave_pkg;
282 u8 max_sad;
283 u8 max_interleave;
284 u8 (*get_node_id)(struct sbridge_pvt *pvt);
285 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
286 struct pci_dev *pci_vtd;
287 };
288
289 struct sbridge_channel {
290 u32 ranks;
291 u32 dimms;
292 };
293
294 struct pci_id_descr {
295 int dev_id;
296 int optional;
297 };
298
299 struct pci_id_table {
300 const struct pci_id_descr *descr;
301 int n_devs;
302 };
303
304 struct sbridge_dev {
305 struct list_head list;
306 u8 bus, mc;
307 u8 node_id, source_id;
308 struct pci_dev **pdev;
309 int n_devs;
310 struct mem_ctl_info *mci;
311 };
312
313 struct sbridge_pvt {
314 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
315 struct pci_dev *pci_sad0, *pci_sad1;
316 struct pci_dev *pci_ha0, *pci_ha1;
317 struct pci_dev *pci_br0, *pci_br1;
318 struct pci_dev *pci_ha1_ta;
319 struct pci_dev *pci_tad[NUM_CHANNELS];
320
321 struct sbridge_dev *sbridge_dev;
322
323 struct sbridge_info info;
324 struct sbridge_channel channel[NUM_CHANNELS];
325
326 /* Memory type detection */
327 bool is_mirrored, is_lockstep, is_close_pg;
328
329 /* Fifo double buffers */
330 struct mce mce_entry[MCE_LOG_LEN];
331 struct mce mce_outentry[MCE_LOG_LEN];
332
333 /* Fifo in/out counters */
334 unsigned mce_in, mce_out;
335
336 /* Count indicator to show errors not got */
337 unsigned mce_overrun;
338
339 /* Memory description */
340 u64 tolm, tohm;
341 };
342
343 #define PCI_DESCR(device_id, opt) \
344 .dev_id = (device_id), \
345 .optional = opt
346
347 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
348 /* Processor Home Agent */
349 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
350
351 /* Memory controller */
352 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
353 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
354 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
355 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
356 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
357 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
358 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
359
360 /* System Address Decoder */
361 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
362 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
363
364 /* Broadcast Registers */
365 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
366 };
367
368 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
369 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
370 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
371 {0,} /* 0 terminated list. */
372 };
373
374 /* This changes depending if 1HA or 2HA:
375 * 1HA:
376 * 0x0eb8 (17.0) is DDRIO0
377 * 2HA:
378 * 0x0ebc (17.4) is DDRIO0
379 */
380 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
381 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
382
383 /* pci ids */
384 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
385 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
386 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
387 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
388 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
389 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
390 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
391 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
392 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
393 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
394 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
395 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
396 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
397 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
398 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
399
400 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
401 /* Processor Home Agent */
402 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
403
404 /* Memory controller */
405 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
406 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
407 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
408 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
410 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
411
412 /* System Address Decoder */
413 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
414
415 /* Broadcast Registers */
416 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
417 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
418
419 /* Optional, mode 2HA */
420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
421 #if 0
422 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
424 #endif
425 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
426 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
427
428 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
429 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
430 };
431
432 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
433 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
434 {0,} /* 0 terminated list. */
435 };
436
437 /* Haswell support */
438 /* EN processor:
439 * - 1 IMC
440 * - 3 DDR3 channels, 2 DPC per channel
441 * EP processor:
442 * - 1 or 2 IMC
443 * - 4 DDR4 channels, 3 DPC per channel
444 * EP 4S processor:
445 * - 2 IMC
446 * - 4 DDR4 channels, 3 DPC per channel
447 * EX processor:
448 * - 2 IMC
449 * - each IMC interfaces with a SMI 2 channel
450 * - each SMI channel interfaces with a scalable memory buffer
451 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
452 */
453 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
454 #define HASWELL_HASYSDEFEATURE2 0x84
455 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
456 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
457 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
458 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
459 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
460 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
461 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
462 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
463 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
464 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
465 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
466 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
467 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
468 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
469 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
470 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
471 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
472 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
473 static const struct pci_id_descr pci_dev_descr_haswell[] = {
474 /* first item must be the HA */
475 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
476
477 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
479
480 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
481
482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
487 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
488
489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
490
491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
497 };
498
499 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
500 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
501 {0,} /* 0 terminated list. */
502 };
503
504 /*
505 * Broadwell support
506 *
507 * DE processor:
508 * - 1 IMC
509 * - 2 DDR3 channels, 2 DPC per channel
510 */
511 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
512 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
513 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
514 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
515 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
516 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
517 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
518 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
519 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
520 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
521 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
522
523 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
524 /* first item must be the HA */
525 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
526
527 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
528 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
529
530 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
531 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
532 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
533 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
534 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 0) },
535 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 0) },
536 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
537 };
538
539 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
540 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
541 {0,} /* 0 terminated list. */
542 };
543
544 /*
545 * pci_device_id table for which devices we are looking for
546 */
547 static const struct pci_device_id sbridge_pci_tbl[] = {
548 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
549 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
550 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
551 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
552 {0,} /* 0 terminated list. */
553 };
554
555
556 /****************************************************************************
557 Ancillary status routines
558 ****************************************************************************/
559
560 static inline int numrank(enum type type, u32 mtr)
561 {
562 int ranks = (1 << RANK_CNT_BITS(mtr));
563 int max = 4;
564
565 if (type == HASWELL)
566 max = 8;
567
568 if (ranks > max) {
569 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
570 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
571 return -EINVAL;
572 }
573
574 return ranks;
575 }
576
577 static inline int numrow(u32 mtr)
578 {
579 int rows = (RANK_WIDTH_BITS(mtr) + 12);
580
581 if (rows < 13 || rows > 18) {
582 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
583 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
584 return -EINVAL;
585 }
586
587 return 1 << rows;
588 }
589
590 static inline int numcol(u32 mtr)
591 {
592 int cols = (COL_WIDTH_BITS(mtr) + 10);
593
594 if (cols > 12) {
595 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
596 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
597 return -EINVAL;
598 }
599
600 return 1 << cols;
601 }
602
603 static struct sbridge_dev *get_sbridge_dev(u8 bus)
604 {
605 struct sbridge_dev *sbridge_dev;
606
607 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
608 if (sbridge_dev->bus == bus)
609 return sbridge_dev;
610 }
611
612 return NULL;
613 }
614
615 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
616 const struct pci_id_table *table)
617 {
618 struct sbridge_dev *sbridge_dev;
619
620 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
621 if (!sbridge_dev)
622 return NULL;
623
624 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
625 GFP_KERNEL);
626 if (!sbridge_dev->pdev) {
627 kfree(sbridge_dev);
628 return NULL;
629 }
630
631 sbridge_dev->bus = bus;
632 sbridge_dev->n_devs = table->n_devs;
633 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
634
635 return sbridge_dev;
636 }
637
638 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
639 {
640 list_del(&sbridge_dev->list);
641 kfree(sbridge_dev->pdev);
642 kfree(sbridge_dev);
643 }
644
645 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
646 {
647 u32 reg;
648
649 /* Address range is 32:28 */
650 pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
651 return GET_TOLM(reg);
652 }
653
654 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
655 {
656 u32 reg;
657
658 pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
659 return GET_TOHM(reg);
660 }
661
662 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
663 {
664 u32 reg;
665
666 pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
667
668 return GET_TOLM(reg);
669 }
670
671 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
672 {
673 u32 reg;
674
675 pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
676
677 return GET_TOHM(reg);
678 }
679
680 static u64 rir_limit(u32 reg)
681 {
682 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
683 }
684
685 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
686 {
687 u32 reg;
688 enum mem_type mtype;
689
690 if (pvt->pci_ddrio) {
691 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
692 &reg);
693 if (GET_BITFIELD(reg, 11, 11))
694 /* FIXME: Can also be LRDIMM */
695 mtype = MEM_RDDR3;
696 else
697 mtype = MEM_DDR3;
698 } else
699 mtype = MEM_UNKNOWN;
700
701 return mtype;
702 }
703
704 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
705 {
706 u32 reg;
707 bool registered = false;
708 enum mem_type mtype = MEM_UNKNOWN;
709
710 if (!pvt->pci_ddrio)
711 goto out;
712
713 pci_read_config_dword(pvt->pci_ddrio,
714 HASWELL_DDRCRCLKCONTROLS, &reg);
715 /* Is_Rdimm */
716 if (GET_BITFIELD(reg, 16, 16))
717 registered = true;
718
719 pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
720 if (GET_BITFIELD(reg, 14, 14)) {
721 if (registered)
722 mtype = MEM_RDDR4;
723 else
724 mtype = MEM_DDR4;
725 } else {
726 if (registered)
727 mtype = MEM_RDDR3;
728 else
729 mtype = MEM_DDR3;
730 }
731
732 out:
733 return mtype;
734 }
735
736 static u8 get_node_id(struct sbridge_pvt *pvt)
737 {
738 u32 reg;
739 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
740 return GET_BITFIELD(reg, 0, 2);
741 }
742
743 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
744 {
745 u32 reg;
746
747 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
748 return GET_BITFIELD(reg, 0, 3);
749 }
750
751 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
752 {
753 u32 reg;
754
755 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
756 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
757 }
758
759 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
760 {
761 u64 rc;
762 u32 reg;
763
764 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
765 rc = GET_BITFIELD(reg, 26, 31);
766 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
767 rc = ((reg << 6) | rc) << 26;
768
769 return rc | 0x1ffffff;
770 }
771
772 static u64 haswell_rir_limit(u32 reg)
773 {
774 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
775 }
776
777 static inline u8 sad_pkg_socket(u8 pkg)
778 {
779 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
780 return ((pkg >> 3) << 2) | (pkg & 0x3);
781 }
782
783 static inline u8 sad_pkg_ha(u8 pkg)
784 {
785 return (pkg >> 2) & 0x1;
786 }
787
788 /****************************************************************************
789 Memory check routines
790 ****************************************************************************/
791 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
792 {
793 struct pci_dev *pdev = NULL;
794
795 do {
796 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
797 if (pdev && pdev->bus->number == bus)
798 break;
799 } while (pdev);
800
801 return pdev;
802 }
803
804 /**
805 * check_if_ecc_is_active() - Checks if ECC is active
806 * @bus: Device bus
807 * @type: Memory controller type
808 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
809 * disabled
810 */
811 static int check_if_ecc_is_active(const u8 bus, enum type type)
812 {
813 struct pci_dev *pdev = NULL;
814 u32 mcmtr, id;
815
816 switch (type) {
817 case IVY_BRIDGE:
818 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
819 break;
820 case HASWELL:
821 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
822 break;
823 case SANDY_BRIDGE:
824 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
825 break;
826 case BROADWELL:
827 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
828 break;
829 default:
830 return -ENODEV;
831 }
832
833 pdev = get_pdev_same_bus(bus, id);
834 if (!pdev) {
835 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
836 "%04x:%04x! on bus %02d\n",
837 PCI_VENDOR_ID_INTEL, id, bus);
838 return -ENODEV;
839 }
840
841 pci_read_config_dword(pdev, MCMTR, &mcmtr);
842 if (!IS_ECC_ENABLED(mcmtr)) {
843 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
844 return -ENODEV;
845 }
846 return 0;
847 }
848
849 static int get_dimm_config(struct mem_ctl_info *mci)
850 {
851 struct sbridge_pvt *pvt = mci->pvt_info;
852 struct dimm_info *dimm;
853 unsigned i, j, banks, ranks, rows, cols, npages;
854 u64 size;
855 u32 reg;
856 enum edac_type mode;
857 enum mem_type mtype;
858
859 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
860 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
861 else
862 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
863
864 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
865
866 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
867 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
868 pvt->sbridge_dev->mc,
869 pvt->sbridge_dev->node_id,
870 pvt->sbridge_dev->source_id);
871
872 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
873 if (IS_MIRROR_ENABLED(reg)) {
874 edac_dbg(0, "Memory mirror is enabled\n");
875 pvt->is_mirrored = true;
876 } else {
877 edac_dbg(0, "Memory mirror is disabled\n");
878 pvt->is_mirrored = false;
879 }
880
881 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
882 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
883 edac_dbg(0, "Lockstep is enabled\n");
884 mode = EDAC_S8ECD8ED;
885 pvt->is_lockstep = true;
886 } else {
887 edac_dbg(0, "Lockstep is disabled\n");
888 mode = EDAC_S4ECD4ED;
889 pvt->is_lockstep = false;
890 }
891 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
892 edac_dbg(0, "address map is on closed page mode\n");
893 pvt->is_close_pg = true;
894 } else {
895 edac_dbg(0, "address map is on open page mode\n");
896 pvt->is_close_pg = false;
897 }
898
899 mtype = pvt->info.get_memory_type(pvt);
900 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
901 edac_dbg(0, "Memory is registered\n");
902 else if (mtype == MEM_UNKNOWN)
903 edac_dbg(0, "Cannot determine memory type\n");
904 else
905 edac_dbg(0, "Memory is unregistered\n");
906
907 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
908 banks = 16;
909 else
910 banks = 8;
911
912 for (i = 0; i < NUM_CHANNELS; i++) {
913 u32 mtr;
914
915 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
916 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
917 i, j, 0);
918 pci_read_config_dword(pvt->pci_tad[i],
919 mtr_regs[j], &mtr);
920 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
921 if (IS_DIMM_PRESENT(mtr)) {
922 pvt->channel[i].dimms++;
923
924 ranks = numrank(pvt->info.type, mtr);
925 rows = numrow(mtr);
926 cols = numcol(mtr);
927
928 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
929 npages = MiB_TO_PAGES(size);
930
931 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
932 pvt->sbridge_dev->mc, i, j,
933 size, npages,
934 banks, ranks, rows, cols);
935
936 dimm->nr_pages = npages;
937 dimm->grain = 32;
938 switch (banks) {
939 case 16:
940 dimm->dtype = DEV_X16;
941 break;
942 case 8:
943 dimm->dtype = DEV_X8;
944 break;
945 case 4:
946 dimm->dtype = DEV_X4;
947 break;
948 }
949 dimm->mtype = mtype;
950 dimm->edac_mode = mode;
951 snprintf(dimm->label, sizeof(dimm->label),
952 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
953 pvt->sbridge_dev->source_id, i, j);
954 }
955 }
956 }
957
958 return 0;
959 }
960
961 static void get_memory_layout(const struct mem_ctl_info *mci)
962 {
963 struct sbridge_pvt *pvt = mci->pvt_info;
964 int i, j, k, n_sads, n_tads, sad_interl;
965 u32 reg;
966 u64 limit, prv = 0;
967 u64 tmp_mb;
968 u32 gb, mb;
969 u32 rir_way;
970
971 /*
972 * Step 1) Get TOLM/TOHM ranges
973 */
974
975 pvt->tolm = pvt->info.get_tolm(pvt);
976 tmp_mb = (1 + pvt->tolm) >> 20;
977
978 gb = div_u64_rem(tmp_mb, 1024, &mb);
979 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
980 gb, (mb*1000)/1024, (u64)pvt->tolm);
981
982 /* Address range is already 45:25 */
983 pvt->tohm = pvt->info.get_tohm(pvt);
984 tmp_mb = (1 + pvt->tohm) >> 20;
985
986 gb = div_u64_rem(tmp_mb, 1024, &mb);
987 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
988 gb, (mb*1000)/1024, (u64)pvt->tohm);
989
990 /*
991 * Step 2) Get SAD range and SAD Interleave list
992 * TAD registers contain the interleave wayness. However, it
993 * seems simpler to just discover it indirectly, with the
994 * algorithm bellow.
995 */
996 prv = 0;
997 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
998 /* SAD_LIMIT Address range is 45:26 */
999 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1000 &reg);
1001 limit = SAD_LIMIT(reg);
1002
1003 if (!DRAM_RULE_ENABLE(reg))
1004 continue;
1005
1006 if (limit <= prv)
1007 break;
1008
1009 tmp_mb = (limit + 1) >> 20;
1010 gb = div_u64_rem(tmp_mb, 1024, &mb);
1011 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1012 n_sads,
1013 get_dram_attr(reg),
1014 gb, (mb*1000)/1024,
1015 ((u64)tmp_mb) << 20L,
1016 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
1017 reg);
1018 prv = limit;
1019
1020 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1021 &reg);
1022 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1023 for (j = 0; j < 8; j++) {
1024 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1025 if (j > 0 && sad_interl == pkg)
1026 break;
1027
1028 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1029 n_sads, j, pkg);
1030 }
1031 }
1032
1033 /*
1034 * Step 3) Get TAD range
1035 */
1036 prv = 0;
1037 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1038 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1039 &reg);
1040 limit = TAD_LIMIT(reg);
1041 if (limit <= prv)
1042 break;
1043 tmp_mb = (limit + 1) >> 20;
1044
1045 gb = div_u64_rem(tmp_mb, 1024, &mb);
1046 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1047 n_tads, gb, (mb*1000)/1024,
1048 ((u64)tmp_mb) << 20L,
1049 (u32)(1 << TAD_SOCK(reg)),
1050 (u32)TAD_CH(reg) + 1,
1051 (u32)TAD_TGT0(reg),
1052 (u32)TAD_TGT1(reg),
1053 (u32)TAD_TGT2(reg),
1054 (u32)TAD_TGT3(reg),
1055 reg);
1056 prv = limit;
1057 }
1058
1059 /*
1060 * Step 4) Get TAD offsets, per each channel
1061 */
1062 for (i = 0; i < NUM_CHANNELS; i++) {
1063 if (!pvt->channel[i].dimms)
1064 continue;
1065 for (j = 0; j < n_tads; j++) {
1066 pci_read_config_dword(pvt->pci_tad[i],
1067 tad_ch_nilv_offset[j],
1068 &reg);
1069 tmp_mb = TAD_OFFSET(reg) >> 20;
1070 gb = div_u64_rem(tmp_mb, 1024, &mb);
1071 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1072 i, j,
1073 gb, (mb*1000)/1024,
1074 ((u64)tmp_mb) << 20L,
1075 reg);
1076 }
1077 }
1078
1079 /*
1080 * Step 6) Get RIR Wayness/Limit, per each channel
1081 */
1082 for (i = 0; i < NUM_CHANNELS; i++) {
1083 if (!pvt->channel[i].dimms)
1084 continue;
1085 for (j = 0; j < MAX_RIR_RANGES; j++) {
1086 pci_read_config_dword(pvt->pci_tad[i],
1087 rir_way_limit[j],
1088 &reg);
1089
1090 if (!IS_RIR_VALID(reg))
1091 continue;
1092
1093 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1094 rir_way = 1 << RIR_WAY(reg);
1095 gb = div_u64_rem(tmp_mb, 1024, &mb);
1096 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1097 i, j,
1098 gb, (mb*1000)/1024,
1099 ((u64)tmp_mb) << 20L,
1100 rir_way,
1101 reg);
1102
1103 for (k = 0; k < rir_way; k++) {
1104 pci_read_config_dword(pvt->pci_tad[i],
1105 rir_offset[j][k],
1106 &reg);
1107 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1108
1109 gb = div_u64_rem(tmp_mb, 1024, &mb);
1110 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1111 i, j, k,
1112 gb, (mb*1000)/1024,
1113 ((u64)tmp_mb) << 20L,
1114 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1115 reg);
1116 }
1117 }
1118 }
1119 }
1120
1121 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1122 {
1123 struct sbridge_dev *sbridge_dev;
1124
1125 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1126 if (sbridge_dev->node_id == node_id)
1127 return sbridge_dev->mci;
1128 }
1129 return NULL;
1130 }
1131
1132 static int get_memory_error_data(struct mem_ctl_info *mci,
1133 u64 addr,
1134 u8 *socket,
1135 long *channel_mask,
1136 u8 *rank,
1137 char **area_type, char *msg)
1138 {
1139 struct mem_ctl_info *new_mci;
1140 struct sbridge_pvt *pvt = mci->pvt_info;
1141 struct pci_dev *pci_ha;
1142 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1143 int sad_interl, idx, base_ch;
1144 int interleave_mode, shiftup = 0;
1145 unsigned sad_interleave[pvt->info.max_interleave];
1146 u32 reg, dram_rule;
1147 u8 ch_way, sck_way, pkg, sad_ha = 0;
1148 u32 tad_offset;
1149 u32 rir_way;
1150 u32 mb, gb;
1151 u64 ch_addr, offset, limit = 0, prv = 0;
1152
1153
1154 /*
1155 * Step 0) Check if the address is at special memory ranges
1156 * The check bellow is probably enough to fill all cases where
1157 * the error is not inside a memory, except for the legacy
1158 * range (e. g. VGA addresses). It is unlikely, however, that the
1159 * memory controller would generate an error on that range.
1160 */
1161 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1162 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1163 return -EINVAL;
1164 }
1165 if (addr >= (u64)pvt->tohm) {
1166 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1167 return -EINVAL;
1168 }
1169
1170 /*
1171 * Step 1) Get socket
1172 */
1173 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1174 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1175 &reg);
1176
1177 if (!DRAM_RULE_ENABLE(reg))
1178 continue;
1179
1180 limit = SAD_LIMIT(reg);
1181 if (limit <= prv) {
1182 sprintf(msg, "Can't discover the memory socket");
1183 return -EINVAL;
1184 }
1185 if (addr <= limit)
1186 break;
1187 prv = limit;
1188 }
1189 if (n_sads == pvt->info.max_sad) {
1190 sprintf(msg, "Can't discover the memory socket");
1191 return -EINVAL;
1192 }
1193 dram_rule = reg;
1194 *area_type = get_dram_attr(dram_rule);
1195 interleave_mode = INTERLEAVE_MODE(dram_rule);
1196
1197 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1198 &reg);
1199
1200 if (pvt->info.type == SANDY_BRIDGE) {
1201 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1202 for (sad_way = 0; sad_way < 8; sad_way++) {
1203 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1204 if (sad_way > 0 && sad_interl == pkg)
1205 break;
1206 sad_interleave[sad_way] = pkg;
1207 edac_dbg(0, "SAD interleave #%d: %d\n",
1208 sad_way, sad_interleave[sad_way]);
1209 }
1210 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1211 pvt->sbridge_dev->mc,
1212 n_sads,
1213 addr,
1214 limit,
1215 sad_way + 7,
1216 !interleave_mode ? "" : "XOR[18:16]");
1217 if (interleave_mode)
1218 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1219 else
1220 idx = (addr >> 6) & 7;
1221 switch (sad_way) {
1222 case 1:
1223 idx = 0;
1224 break;
1225 case 2:
1226 idx = idx & 1;
1227 break;
1228 case 4:
1229 idx = idx & 3;
1230 break;
1231 case 8:
1232 break;
1233 default:
1234 sprintf(msg, "Can't discover socket interleave");
1235 return -EINVAL;
1236 }
1237 *socket = sad_interleave[idx];
1238 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1239 idx, sad_way, *socket);
1240 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1241 int bits, a7mode = A7MODE(dram_rule);
1242
1243 if (a7mode) {
1244 /* A7 mode swaps P9 with P6 */
1245 bits = GET_BITFIELD(addr, 7, 8) << 1;
1246 bits |= GET_BITFIELD(addr, 9, 9);
1247 } else
1248 bits = GET_BITFIELD(addr, 7, 9);
1249
1250 if (interleave_mode) {
1251 /* interleave mode will XOR {8,7,6} with {18,17,16} */
1252 idx = GET_BITFIELD(addr, 16, 18);
1253 idx ^= bits;
1254 } else
1255 idx = bits;
1256
1257 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1258 *socket = sad_pkg_socket(pkg);
1259 sad_ha = sad_pkg_ha(pkg);
1260
1261 if (a7mode) {
1262 /* MCChanShiftUpEnable */
1263 pci_read_config_dword(pvt->pci_ha0,
1264 HASWELL_HASYSDEFEATURE2, &reg);
1265 shiftup = GET_BITFIELD(reg, 22, 22);
1266 }
1267
1268 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1269 idx, *socket, sad_ha, shiftup);
1270 } else {
1271 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1272 idx = (addr >> 6) & 7;
1273 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1274 *socket = sad_pkg_socket(pkg);
1275 sad_ha = sad_pkg_ha(pkg);
1276 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1277 idx, *socket, sad_ha);
1278 }
1279
1280 /*
1281 * Move to the proper node structure, in order to access the
1282 * right PCI registers
1283 */
1284 new_mci = get_mci_for_node_id(*socket);
1285 if (!new_mci) {
1286 sprintf(msg, "Struct for socket #%u wasn't initialized",
1287 *socket);
1288 return -EINVAL;
1289 }
1290 mci = new_mci;
1291 pvt = mci->pvt_info;
1292
1293 /*
1294 * Step 2) Get memory channel
1295 */
1296 prv = 0;
1297 if (pvt->info.type == SANDY_BRIDGE)
1298 pci_ha = pvt->pci_ha0;
1299 else {
1300 if (sad_ha)
1301 pci_ha = pvt->pci_ha1;
1302 else
1303 pci_ha = pvt->pci_ha0;
1304 }
1305 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1306 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
1307 limit = TAD_LIMIT(reg);
1308 if (limit <= prv) {
1309 sprintf(msg, "Can't discover the memory channel");
1310 return -EINVAL;
1311 }
1312 if (addr <= limit)
1313 break;
1314 prv = limit;
1315 }
1316 if (n_tads == MAX_TAD) {
1317 sprintf(msg, "Can't discover the memory channel");
1318 return -EINVAL;
1319 }
1320
1321 ch_way = TAD_CH(reg) + 1;
1322 sck_way = TAD_SOCK(reg);
1323
1324 if (ch_way == 3)
1325 idx = addr >> 6;
1326 else
1327 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1328 idx = idx % ch_way;
1329
1330 /*
1331 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1332 */
1333 switch (idx) {
1334 case 0:
1335 base_ch = TAD_TGT0(reg);
1336 break;
1337 case 1:
1338 base_ch = TAD_TGT1(reg);
1339 break;
1340 case 2:
1341 base_ch = TAD_TGT2(reg);
1342 break;
1343 case 3:
1344 base_ch = TAD_TGT3(reg);
1345 break;
1346 default:
1347 sprintf(msg, "Can't discover the TAD target");
1348 return -EINVAL;
1349 }
1350 *channel_mask = 1 << base_ch;
1351
1352 pci_read_config_dword(pvt->pci_tad[base_ch],
1353 tad_ch_nilv_offset[n_tads],
1354 &tad_offset);
1355
1356 if (pvt->is_mirrored) {
1357 *channel_mask |= 1 << ((base_ch + 2) % 4);
1358 switch(ch_way) {
1359 case 2:
1360 case 4:
1361 sck_xch = (1 << sck_way) * (ch_way >> 1);
1362 break;
1363 default:
1364 sprintf(msg, "Invalid mirror set. Can't decode addr");
1365 return -EINVAL;
1366 }
1367 } else
1368 sck_xch = (1 << sck_way) * ch_way;
1369
1370 if (pvt->is_lockstep)
1371 *channel_mask |= 1 << ((base_ch + 1) % 4);
1372
1373 offset = TAD_OFFSET(tad_offset);
1374
1375 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1376 n_tads,
1377 addr,
1378 limit,
1379 sck_way,
1380 ch_way,
1381 offset,
1382 idx,
1383 base_ch,
1384 *channel_mask);
1385
1386 /* Calculate channel address */
1387 /* Remove the TAD offset */
1388
1389 if (offset > addr) {
1390 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1391 offset, addr);
1392 return -EINVAL;
1393 }
1394
1395 ch_addr = addr - offset;
1396 ch_addr >>= (6 + shiftup);
1397 ch_addr /= sck_xch;
1398 ch_addr <<= (6 + shiftup);
1399 ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
1400
1401 /*
1402 * Step 3) Decode rank
1403 */
1404 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1405 pci_read_config_dword(pvt->pci_tad[base_ch],
1406 rir_way_limit[n_rir],
1407 &reg);
1408
1409 if (!IS_RIR_VALID(reg))
1410 continue;
1411
1412 limit = pvt->info.rir_limit(reg);
1413 gb = div_u64_rem(limit >> 20, 1024, &mb);
1414 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1415 n_rir,
1416 gb, (mb*1000)/1024,
1417 limit,
1418 1 << RIR_WAY(reg));
1419 if (ch_addr <= limit)
1420 break;
1421 }
1422 if (n_rir == MAX_RIR_RANGES) {
1423 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1424 ch_addr);
1425 return -EINVAL;
1426 }
1427 rir_way = RIR_WAY(reg);
1428
1429 if (pvt->is_close_pg)
1430 idx = (ch_addr >> 6);
1431 else
1432 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1433 idx %= 1 << rir_way;
1434
1435 pci_read_config_dword(pvt->pci_tad[base_ch],
1436 rir_offset[n_rir][idx],
1437 &reg);
1438 *rank = RIR_RNK_TGT(pvt->info.type, reg);
1439
1440 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1441 n_rir,
1442 ch_addr,
1443 limit,
1444 rir_way,
1445 idx);
1446
1447 return 0;
1448 }
1449
1450 /****************************************************************************
1451 Device initialization routines: put/get, init/exit
1452 ****************************************************************************/
1453
1454 /*
1455 * sbridge_put_all_devices 'put' all the devices that we have
1456 * reserved via 'get'
1457 */
1458 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1459 {
1460 int i;
1461
1462 edac_dbg(0, "\n");
1463 for (i = 0; i < sbridge_dev->n_devs; i++) {
1464 struct pci_dev *pdev = sbridge_dev->pdev[i];
1465 if (!pdev)
1466 continue;
1467 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1468 pdev->bus->number,
1469 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1470 pci_dev_put(pdev);
1471 }
1472 }
1473
1474 static void sbridge_put_all_devices(void)
1475 {
1476 struct sbridge_dev *sbridge_dev, *tmp;
1477
1478 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1479 sbridge_put_devices(sbridge_dev);
1480 free_sbridge_dev(sbridge_dev);
1481 }
1482 }
1483
1484 static int sbridge_get_onedevice(struct pci_dev **prev,
1485 u8 *num_mc,
1486 const struct pci_id_table *table,
1487 const unsigned devno)
1488 {
1489 struct sbridge_dev *sbridge_dev;
1490 const struct pci_id_descr *dev_descr = &table->descr[devno];
1491 struct pci_dev *pdev = NULL;
1492 u8 bus = 0;
1493
1494 sbridge_printk(KERN_DEBUG,
1495 "Seeking for: PCI ID %04x:%04x\n",
1496 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1497
1498 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1499 dev_descr->dev_id, *prev);
1500
1501 if (!pdev) {
1502 if (*prev) {
1503 *prev = pdev;
1504 return 0;
1505 }
1506
1507 if (dev_descr->optional)
1508 return 0;
1509
1510 /* if the HA wasn't found */
1511 if (devno == 0)
1512 return -ENODEV;
1513
1514 sbridge_printk(KERN_INFO,
1515 "Device not found: %04x:%04x\n",
1516 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1517
1518 /* End of list, leave */
1519 return -ENODEV;
1520 }
1521 bus = pdev->bus->number;
1522
1523 sbridge_dev = get_sbridge_dev(bus);
1524 if (!sbridge_dev) {
1525 sbridge_dev = alloc_sbridge_dev(bus, table);
1526 if (!sbridge_dev) {
1527 pci_dev_put(pdev);
1528 return -ENOMEM;
1529 }
1530 (*num_mc)++;
1531 }
1532
1533 if (sbridge_dev->pdev[devno]) {
1534 sbridge_printk(KERN_ERR,
1535 "Duplicated device for %04x:%04x\n",
1536 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1537 pci_dev_put(pdev);
1538 return -ENODEV;
1539 }
1540
1541 sbridge_dev->pdev[devno] = pdev;
1542
1543 /* Be sure that the device is enabled */
1544 if (unlikely(pci_enable_device(pdev) < 0)) {
1545 sbridge_printk(KERN_ERR,
1546 "Couldn't enable %04x:%04x\n",
1547 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1548 return -ENODEV;
1549 }
1550
1551 edac_dbg(0, "Detected %04x:%04x\n",
1552 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1553
1554 /*
1555 * As stated on drivers/pci/search.c, the reference count for
1556 * @from is always decremented if it is not %NULL. So, as we need
1557 * to get all devices up to null, we need to do a get for the device
1558 */
1559 pci_dev_get(pdev);
1560
1561 *prev = pdev;
1562
1563 return 0;
1564 }
1565
1566 /*
1567 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1568 * devices we want to reference for this driver.
1569 * @num_mc: pointer to the memory controllers count, to be incremented in case
1570 * of success.
1571 * @table: model specific table
1572 *
1573 * returns 0 in case of success or error code
1574 */
1575 static int sbridge_get_all_devices(u8 *num_mc,
1576 const struct pci_id_table *table)
1577 {
1578 int i, rc;
1579 struct pci_dev *pdev = NULL;
1580
1581 while (table && table->descr) {
1582 for (i = 0; i < table->n_devs; i++) {
1583 pdev = NULL;
1584 do {
1585 rc = sbridge_get_onedevice(&pdev, num_mc,
1586 table, i);
1587 if (rc < 0) {
1588 if (i == 0) {
1589 i = table->n_devs;
1590 break;
1591 }
1592 sbridge_put_all_devices();
1593 return -ENODEV;
1594 }
1595 } while (pdev);
1596 }
1597 table++;
1598 }
1599
1600 return 0;
1601 }
1602
1603 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1604 struct sbridge_dev *sbridge_dev)
1605 {
1606 struct sbridge_pvt *pvt = mci->pvt_info;
1607 struct pci_dev *pdev;
1608 u8 saw_chan_mask = 0;
1609 int i;
1610
1611 for (i = 0; i < sbridge_dev->n_devs; i++) {
1612 pdev = sbridge_dev->pdev[i];
1613 if (!pdev)
1614 continue;
1615
1616 switch (pdev->device) {
1617 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1618 pvt->pci_sad0 = pdev;
1619 break;
1620 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1621 pvt->pci_sad1 = pdev;
1622 break;
1623 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1624 pvt->pci_br0 = pdev;
1625 break;
1626 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1627 pvt->pci_ha0 = pdev;
1628 break;
1629 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1630 pvt->pci_ta = pdev;
1631 break;
1632 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1633 pvt->pci_ras = pdev;
1634 break;
1635 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1636 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1637 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1638 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1639 {
1640 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1641 pvt->pci_tad[id] = pdev;
1642 saw_chan_mask |= 1 << id;
1643 }
1644 break;
1645 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1646 pvt->pci_ddrio = pdev;
1647 break;
1648 default:
1649 goto error;
1650 }
1651
1652 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1653 pdev->vendor, pdev->device,
1654 sbridge_dev->bus,
1655 pdev);
1656 }
1657
1658 /* Check if everything were registered */
1659 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1660 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
1661 goto enodev;
1662
1663 if (saw_chan_mask != 0x0f)
1664 goto enodev;
1665 return 0;
1666
1667 enodev:
1668 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1669 return -ENODEV;
1670
1671 error:
1672 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1673 PCI_VENDOR_ID_INTEL, pdev->device);
1674 return -EINVAL;
1675 }
1676
1677 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1678 struct sbridge_dev *sbridge_dev)
1679 {
1680 struct sbridge_pvt *pvt = mci->pvt_info;
1681 struct pci_dev *pdev, *tmp;
1682 int i;
1683 bool mode_2ha = false;
1684
1685 tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1686 PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL);
1687 if (tmp) {
1688 mode_2ha = true;
1689 pci_dev_put(tmp);
1690 }
1691
1692 for (i = 0; i < sbridge_dev->n_devs; i++) {
1693 pdev = sbridge_dev->pdev[i];
1694 if (!pdev)
1695 continue;
1696
1697 switch (pdev->device) {
1698 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1699 pvt->pci_ha0 = pdev;
1700 break;
1701 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1702 pvt->pci_ta = pdev;
1703 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1704 pvt->pci_ras = pdev;
1705 break;
1706 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1707 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1708 /* if we have 2 HAs active, channels 2 and 3
1709 * are in other device */
1710 if (mode_2ha)
1711 break;
1712 /* fall through */
1713 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1714 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1715 {
1716 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1717 pvt->pci_tad[id] = pdev;
1718 }
1719 break;
1720 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1721 pvt->pci_ddrio = pdev;
1722 break;
1723 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1724 if (!mode_2ha)
1725 pvt->pci_ddrio = pdev;
1726 break;
1727 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1728 pvt->pci_sad0 = pdev;
1729 break;
1730 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1731 pvt->pci_br0 = pdev;
1732 break;
1733 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1734 pvt->pci_br1 = pdev;
1735 break;
1736 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1737 pvt->pci_ha1 = pdev;
1738 break;
1739 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1740 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1741 {
1742 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2;
1743
1744 /* we shouldn't have this device if we have just one
1745 * HA present */
1746 WARN_ON(!mode_2ha);
1747 pvt->pci_tad[id] = pdev;
1748 }
1749 break;
1750 default:
1751 goto error;
1752 }
1753
1754 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1755 sbridge_dev->bus,
1756 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1757 pdev);
1758 }
1759
1760 /* Check if everything were registered */
1761 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1762 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
1763 !pvt->pci_ta)
1764 goto enodev;
1765
1766 for (i = 0; i < NUM_CHANNELS; i++) {
1767 if (!pvt->pci_tad[i])
1768 goto enodev;
1769 }
1770 return 0;
1771
1772 enodev:
1773 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1774 return -ENODEV;
1775
1776 error:
1777 sbridge_printk(KERN_ERR,
1778 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1779 pdev->device);
1780 return -EINVAL;
1781 }
1782
1783 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1784 struct sbridge_dev *sbridge_dev)
1785 {
1786 struct sbridge_pvt *pvt = mci->pvt_info;
1787 struct pci_dev *pdev, *tmp;
1788 int i;
1789 bool mode_2ha = false;
1790
1791 tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1792 PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL);
1793 if (tmp) {
1794 mode_2ha = true;
1795 pci_dev_put(tmp);
1796 }
1797
1798 /* there's only one device per system; not tied to any bus */
1799 if (pvt->info.pci_vtd == NULL)
1800 /* result will be checked later */
1801 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1802 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1803 NULL);
1804
1805 for (i = 0; i < sbridge_dev->n_devs; i++) {
1806 pdev = sbridge_dev->pdev[i];
1807 if (!pdev)
1808 continue;
1809
1810 switch (pdev->device) {
1811 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1812 pvt->pci_sad0 = pdev;
1813 break;
1814 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1815 pvt->pci_sad1 = pdev;
1816 break;
1817 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1818 pvt->pci_ha0 = pdev;
1819 break;
1820 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1821 pvt->pci_ta = pdev;
1822 break;
1823 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1824 pvt->pci_ras = pdev;
1825 break;
1826 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1827 pvt->pci_tad[0] = pdev;
1828 break;
1829 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1830 pvt->pci_tad[1] = pdev;
1831 break;
1832 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1833 if (!mode_2ha)
1834 pvt->pci_tad[2] = pdev;
1835 break;
1836 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1837 if (!mode_2ha)
1838 pvt->pci_tad[3] = pdev;
1839 break;
1840 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1841 pvt->pci_ddrio = pdev;
1842 break;
1843 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1844 pvt->pci_ha1 = pdev;
1845 break;
1846 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1847 pvt->pci_ha1_ta = pdev;
1848 break;
1849 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1850 if (mode_2ha)
1851 pvt->pci_tad[2] = pdev;
1852 break;
1853 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1854 if (mode_2ha)
1855 pvt->pci_tad[3] = pdev;
1856 break;
1857 default:
1858 break;
1859 }
1860
1861 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1862 sbridge_dev->bus,
1863 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1864 pdev);
1865 }
1866
1867 /* Check if everything were registered */
1868 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1869 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1870 goto enodev;
1871
1872 for (i = 0; i < NUM_CHANNELS; i++) {
1873 if (!pvt->pci_tad[i])
1874 goto enodev;
1875 }
1876 return 0;
1877
1878 enodev:
1879 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1880 return -ENODEV;
1881 }
1882
1883 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
1884 struct sbridge_dev *sbridge_dev)
1885 {
1886 struct sbridge_pvt *pvt = mci->pvt_info;
1887 struct pci_dev *pdev;
1888 int i;
1889
1890 /* there's only one device per system; not tied to any bus */
1891 if (pvt->info.pci_vtd == NULL)
1892 /* result will be checked later */
1893 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1894 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
1895 NULL);
1896
1897 for (i = 0; i < sbridge_dev->n_devs; i++) {
1898 pdev = sbridge_dev->pdev[i];
1899 if (!pdev)
1900 continue;
1901
1902 switch (pdev->device) {
1903 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
1904 pvt->pci_sad0 = pdev;
1905 break;
1906 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
1907 pvt->pci_sad1 = pdev;
1908 break;
1909 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
1910 pvt->pci_ha0 = pdev;
1911 break;
1912 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
1913 pvt->pci_ta = pdev;
1914 break;
1915 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
1916 pvt->pci_ras = pdev;
1917 break;
1918 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
1919 pvt->pci_tad[0] = pdev;
1920 break;
1921 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
1922 pvt->pci_tad[1] = pdev;
1923 break;
1924 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
1925 pvt->pci_tad[2] = pdev;
1926 break;
1927 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
1928 pvt->pci_tad[3] = pdev;
1929 break;
1930 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
1931 pvt->pci_ddrio = pdev;
1932 break;
1933 default:
1934 break;
1935 }
1936
1937 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1938 sbridge_dev->bus,
1939 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1940 pdev);
1941 }
1942
1943 /* Check if everything were registered */
1944 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1945 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1946 goto enodev;
1947
1948 for (i = 0; i < NUM_CHANNELS; i++) {
1949 if (!pvt->pci_tad[i])
1950 goto enodev;
1951 }
1952 return 0;
1953
1954 enodev:
1955 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1956 return -ENODEV;
1957 }
1958
1959 /****************************************************************************
1960 Error check routines
1961 ****************************************************************************/
1962
1963 /*
1964 * While Sandy Bridge has error count registers, SMI BIOS read values from
1965 * and resets the counters. So, they are not reliable for the OS to read
1966 * from them. So, we have no option but to just trust on whatever MCE is
1967 * telling us about the errors.
1968 */
1969 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1970 const struct mce *m)
1971 {
1972 struct mem_ctl_info *new_mci;
1973 struct sbridge_pvt *pvt = mci->pvt_info;
1974 enum hw_event_mc_err_type tp_event;
1975 char *type, *optype, msg[256];
1976 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1977 bool overflow = GET_BITFIELD(m->status, 62, 62);
1978 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1979 bool recoverable;
1980 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1981 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1982 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1983 u32 channel = GET_BITFIELD(m->status, 0, 3);
1984 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1985 long channel_mask, first_channel;
1986 u8 rank, socket;
1987 int rc, dimm;
1988 char *area_type = NULL;
1989
1990 if (pvt->info.type == IVY_BRIDGE)
1991 recoverable = true;
1992 else
1993 recoverable = GET_BITFIELD(m->status, 56, 56);
1994
1995 if (uncorrected_error) {
1996 if (ripv) {
1997 type = "FATAL";
1998 tp_event = HW_EVENT_ERR_FATAL;
1999 } else {
2000 type = "NON_FATAL";
2001 tp_event = HW_EVENT_ERR_UNCORRECTED;
2002 }
2003 } else {
2004 type = "CORRECTED";
2005 tp_event = HW_EVENT_ERR_CORRECTED;
2006 }
2007
2008 /*
2009 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2010 * memory errors should fit in this mask:
2011 * 000f 0000 1mmm cccc (binary)
2012 * where:
2013 * f = Correction Report Filtering Bit. If 1, subsequent errors
2014 * won't be shown
2015 * mmm = error type
2016 * cccc = channel
2017 * If the mask doesn't match, report an error to the parsing logic
2018 */
2019 if (! ((errcode & 0xef80) == 0x80)) {
2020 optype = "Can't parse: it is not a mem";
2021 } else {
2022 switch (optypenum) {
2023 case 0:
2024 optype = "generic undef request error";
2025 break;
2026 case 1:
2027 optype = "memory read error";
2028 break;
2029 case 2:
2030 optype = "memory write error";
2031 break;
2032 case 3:
2033 optype = "addr/cmd error";
2034 break;
2035 case 4:
2036 optype = "memory scrubbing error";
2037 break;
2038 default:
2039 optype = "reserved";
2040 break;
2041 }
2042 }
2043
2044 /* Only decode errors with an valid address (ADDRV) */
2045 if (!GET_BITFIELD(m->status, 58, 58))
2046 return;
2047
2048 rc = get_memory_error_data(mci, m->addr, &socket,
2049 &channel_mask, &rank, &area_type, msg);
2050 if (rc < 0)
2051 goto err_parsing;
2052 new_mci = get_mci_for_node_id(socket);
2053 if (!new_mci) {
2054 strcpy(msg, "Error: socket got corrupted!");
2055 goto err_parsing;
2056 }
2057 mci = new_mci;
2058 pvt = mci->pvt_info;
2059
2060 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2061
2062 if (rank < 4)
2063 dimm = 0;
2064 else if (rank < 8)
2065 dimm = 1;
2066 else
2067 dimm = 2;
2068
2069
2070 /*
2071 * FIXME: On some memory configurations (mirror, lockstep), the
2072 * Memory Controller can't point the error to a single DIMM. The
2073 * EDAC core should be handling the channel mask, in order to point
2074 * to the group of dimm's where the error may be happening.
2075 */
2076 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
2077 channel = first_channel;
2078
2079 snprintf(msg, sizeof(msg),
2080 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
2081 overflow ? " OVERFLOW" : "",
2082 (uncorrected_error && recoverable) ? " recoverable" : "",
2083 area_type,
2084 mscod, errcode,
2085 socket,
2086 channel_mask,
2087 rank);
2088
2089 edac_dbg(0, "%s\n", msg);
2090
2091 /* FIXME: need support for channel mask */
2092
2093 if (channel == CHANNEL_UNSPECIFIED)
2094 channel = -1;
2095
2096 /* Call the helper to output message */
2097 edac_mc_handle_error(tp_event, mci, core_err_cnt,
2098 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2099 channel, dimm, -1,
2100 optype, msg);
2101 return;
2102 err_parsing:
2103 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
2104 -1, -1, -1,
2105 msg, "");
2106
2107 }
2108
2109 /*
2110 * sbridge_check_error Retrieve and process errors reported by the
2111 * hardware. Called by the Core module.
2112 */
2113 static void sbridge_check_error(struct mem_ctl_info *mci)
2114 {
2115 struct sbridge_pvt *pvt = mci->pvt_info;
2116 int i;
2117 unsigned count = 0;
2118 struct mce *m;
2119
2120 /*
2121 * MCE first step: Copy all mce errors into a temporary buffer
2122 * We use a double buffering here, to reduce the risk of
2123 * loosing an error.
2124 */
2125 smp_rmb();
2126 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2127 % MCE_LOG_LEN;
2128 if (!count)
2129 return;
2130
2131 m = pvt->mce_outentry;
2132 if (pvt->mce_in + count > MCE_LOG_LEN) {
2133 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2134
2135 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2136 smp_wmb();
2137 pvt->mce_in = 0;
2138 count -= l;
2139 m += l;
2140 }
2141 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2142 smp_wmb();
2143 pvt->mce_in += count;
2144
2145 smp_rmb();
2146 if (pvt->mce_overrun) {
2147 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2148 pvt->mce_overrun);
2149 smp_wmb();
2150 pvt->mce_overrun = 0;
2151 }
2152
2153 /*
2154 * MCE second step: parse errors and display
2155 */
2156 for (i = 0; i < count; i++)
2157 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2158 }
2159
2160 /*
2161 * sbridge_mce_check_error Replicates mcelog routine to get errors
2162 * This routine simply queues mcelog errors, and
2163 * return. The error itself should be handled later
2164 * by sbridge_check_error.
2165 * WARNING: As this routine should be called at NMI time, extra care should
2166 * be taken to avoid deadlocks, and to be as fast as possible.
2167 */
2168 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2169 void *data)
2170 {
2171 struct mce *mce = (struct mce *)data;
2172 struct mem_ctl_info *mci;
2173 struct sbridge_pvt *pvt;
2174 char *type;
2175
2176 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2177 return NOTIFY_DONE;
2178
2179 mci = get_mci_for_node_id(mce->socketid);
2180 if (!mci)
2181 return NOTIFY_DONE;
2182 pvt = mci->pvt_info;
2183
2184 /*
2185 * Just let mcelog handle it if the error is
2186 * outside the memory controller. A memory error
2187 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2188 * bit 12 has an special meaning.
2189 */
2190 if ((mce->status & 0xefff) >> 7 != 1)
2191 return NOTIFY_DONE;
2192
2193 if (mce->mcgstatus & MCG_STATUS_MCIP)
2194 type = "Exception";
2195 else
2196 type = "Event";
2197
2198 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2199
2200 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2201 "Bank %d: %016Lx\n", mce->extcpu, type,
2202 mce->mcgstatus, mce->bank, mce->status);
2203 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2204 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2205 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2206
2207 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2208 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2209 mce->time, mce->socketid, mce->apicid);
2210
2211 smp_rmb();
2212 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2213 smp_wmb();
2214 pvt->mce_overrun++;
2215 return NOTIFY_DONE;
2216 }
2217
2218 /* Copy memory error at the ringbuffer */
2219 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2220 smp_wmb();
2221 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2222
2223 /* Handle fatal errors immediately */
2224 if (mce->mcgstatus & 1)
2225 sbridge_check_error(mci);
2226
2227 /* Advice mcelog that the error were handled */
2228 return NOTIFY_STOP;
2229 }
2230
2231 static struct notifier_block sbridge_mce_dec = {
2232 .notifier_call = sbridge_mce_check_error,
2233 };
2234
2235 /****************************************************************************
2236 EDAC register/unregister logic
2237 ****************************************************************************/
2238
2239 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2240 {
2241 struct mem_ctl_info *mci = sbridge_dev->mci;
2242 struct sbridge_pvt *pvt;
2243
2244 if (unlikely(!mci || !mci->pvt_info)) {
2245 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2246
2247 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2248 return;
2249 }
2250
2251 pvt = mci->pvt_info;
2252
2253 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2254 mci, &sbridge_dev->pdev[0]->dev);
2255
2256 /* Remove MC sysfs nodes */
2257 edac_mc_del_mc(mci->pdev);
2258
2259 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2260 kfree(mci->ctl_name);
2261 edac_mc_free(mci);
2262 sbridge_dev->mci = NULL;
2263 }
2264
2265 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2266 {
2267 struct mem_ctl_info *mci;
2268 struct edac_mc_layer layers[2];
2269 struct sbridge_pvt *pvt;
2270 struct pci_dev *pdev = sbridge_dev->pdev[0];
2271 int rc;
2272
2273 /* Check the number of active and not disabled channels */
2274 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2275 if (unlikely(rc < 0))
2276 return rc;
2277
2278 /* allocate a new MC control structure */
2279 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2280 layers[0].size = NUM_CHANNELS;
2281 layers[0].is_virt_csrow = false;
2282 layers[1].type = EDAC_MC_LAYER_SLOT;
2283 layers[1].size = MAX_DIMMS;
2284 layers[1].is_virt_csrow = true;
2285 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2286 sizeof(*pvt));
2287
2288 if (unlikely(!mci))
2289 return -ENOMEM;
2290
2291 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2292 mci, &pdev->dev);
2293
2294 pvt = mci->pvt_info;
2295 memset(pvt, 0, sizeof(*pvt));
2296
2297 /* Associate sbridge_dev and mci for future usage */
2298 pvt->sbridge_dev = sbridge_dev;
2299 sbridge_dev->mci = mci;
2300
2301 mci->mtype_cap = MEM_FLAG_DDR3;
2302 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2303 mci->edac_cap = EDAC_FLAG_NONE;
2304 mci->mod_name = "sbridge_edac.c";
2305 mci->mod_ver = SBRIDGE_REVISION;
2306 mci->dev_name = pci_name(pdev);
2307 mci->ctl_page_to_phys = NULL;
2308
2309 /* Set the function pointer to an actual operation function */
2310 mci->edac_check = sbridge_check_error;
2311
2312 pvt->info.type = type;
2313 switch (type) {
2314 case IVY_BRIDGE:
2315 pvt->info.rankcfgr = IB_RANK_CFG_A;
2316 pvt->info.get_tolm = ibridge_get_tolm;
2317 pvt->info.get_tohm = ibridge_get_tohm;
2318 pvt->info.dram_rule = ibridge_dram_rule;
2319 pvt->info.get_memory_type = get_memory_type;
2320 pvt->info.get_node_id = get_node_id;
2321 pvt->info.rir_limit = rir_limit;
2322 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2323 pvt->info.interleave_list = ibridge_interleave_list;
2324 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2325 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2326 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2327
2328 /* Store pci devices at mci for faster access */
2329 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2330 if (unlikely(rc < 0))
2331 goto fail0;
2332 break;
2333 case SANDY_BRIDGE:
2334 pvt->info.rankcfgr = SB_RANK_CFG_A;
2335 pvt->info.get_tolm = sbridge_get_tolm;
2336 pvt->info.get_tohm = sbridge_get_tohm;
2337 pvt->info.dram_rule = sbridge_dram_rule;
2338 pvt->info.get_memory_type = get_memory_type;
2339 pvt->info.get_node_id = get_node_id;
2340 pvt->info.rir_limit = rir_limit;
2341 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2342 pvt->info.interleave_list = sbridge_interleave_list;
2343 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2344 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2345 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2346
2347 /* Store pci devices at mci for faster access */
2348 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2349 if (unlikely(rc < 0))
2350 goto fail0;
2351 break;
2352 case HASWELL:
2353 /* rankcfgr isn't used */
2354 pvt->info.get_tolm = haswell_get_tolm;
2355 pvt->info.get_tohm = haswell_get_tohm;
2356 pvt->info.dram_rule = ibridge_dram_rule;
2357 pvt->info.get_memory_type = haswell_get_memory_type;
2358 pvt->info.get_node_id = haswell_get_node_id;
2359 pvt->info.rir_limit = haswell_rir_limit;
2360 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2361 pvt->info.interleave_list = ibridge_interleave_list;
2362 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2363 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2364 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2365
2366 /* Store pci devices at mci for faster access */
2367 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2368 if (unlikely(rc < 0))
2369 goto fail0;
2370 break;
2371 case BROADWELL:
2372 /* rankcfgr isn't used */
2373 pvt->info.get_tolm = haswell_get_tolm;
2374 pvt->info.get_tohm = haswell_get_tohm;
2375 pvt->info.dram_rule = ibridge_dram_rule;
2376 pvt->info.get_memory_type = haswell_get_memory_type;
2377 pvt->info.get_node_id = haswell_get_node_id;
2378 pvt->info.rir_limit = haswell_rir_limit;
2379 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2380 pvt->info.interleave_list = ibridge_interleave_list;
2381 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2382 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2383 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
2384
2385 /* Store pci devices at mci for faster access */
2386 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
2387 if (unlikely(rc < 0))
2388 goto fail0;
2389 break;
2390 }
2391
2392 /* Get dimm basic config and the memory layout */
2393 get_dimm_config(mci);
2394 get_memory_layout(mci);
2395
2396 /* record ptr to the generic device */
2397 mci->pdev = &pdev->dev;
2398
2399 /* add this new MC control structure to EDAC's list of MCs */
2400 if (unlikely(edac_mc_add_mc(mci))) {
2401 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2402 rc = -EINVAL;
2403 goto fail0;
2404 }
2405
2406 return 0;
2407
2408 fail0:
2409 kfree(mci->ctl_name);
2410 edac_mc_free(mci);
2411 sbridge_dev->mci = NULL;
2412 return rc;
2413 }
2414
2415 /*
2416 * sbridge_probe Probe for ONE instance of device to see if it is
2417 * present.
2418 * return:
2419 * 0 for FOUND a device
2420 * < 0 for error code
2421 */
2422
2423 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2424 {
2425 int rc = -ENODEV;
2426 u8 mc, num_mc = 0;
2427 struct sbridge_dev *sbridge_dev;
2428 enum type type = SANDY_BRIDGE;
2429
2430 /* get the pci devices we want to reserve for our use */
2431 mutex_lock(&sbridge_edac_lock);
2432
2433 /*
2434 * All memory controllers are allocated at the first pass.
2435 */
2436 if (unlikely(probed >= 1)) {
2437 mutex_unlock(&sbridge_edac_lock);
2438 return -ENODEV;
2439 }
2440 probed++;
2441
2442 switch (pdev->device) {
2443 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2444 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2445 type = IVY_BRIDGE;
2446 break;
2447 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2448 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2449 type = SANDY_BRIDGE;
2450 break;
2451 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2452 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2453 type = HASWELL;
2454 break;
2455 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2456 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
2457 type = BROADWELL;
2458 break;
2459 }
2460 if (unlikely(rc < 0)) {
2461 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
2462 goto fail0;
2463 }
2464
2465 mc = 0;
2466
2467 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2468 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2469 mc, mc + 1, num_mc);
2470
2471 sbridge_dev->mc = mc++;
2472 rc = sbridge_register_mci(sbridge_dev, type);
2473 if (unlikely(rc < 0))
2474 goto fail1;
2475 }
2476
2477 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
2478
2479 mutex_unlock(&sbridge_edac_lock);
2480 return 0;
2481
2482 fail1:
2483 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2484 sbridge_unregister_mci(sbridge_dev);
2485
2486 sbridge_put_all_devices();
2487 fail0:
2488 mutex_unlock(&sbridge_edac_lock);
2489 return rc;
2490 }
2491
2492 /*
2493 * sbridge_remove destructor for one instance of device
2494 *
2495 */
2496 static void sbridge_remove(struct pci_dev *pdev)
2497 {
2498 struct sbridge_dev *sbridge_dev;
2499
2500 edac_dbg(0, "\n");
2501
2502 /*
2503 * we have a trouble here: pdev value for removal will be wrong, since
2504 * it will point to the X58 register used to detect that the machine
2505 * is a Nehalem or upper design. However, due to the way several PCI
2506 * devices are grouped together to provide MC functionality, we need
2507 * to use a different method for releasing the devices
2508 */
2509
2510 mutex_lock(&sbridge_edac_lock);
2511
2512 if (unlikely(!probed)) {
2513 mutex_unlock(&sbridge_edac_lock);
2514 return;
2515 }
2516
2517 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2518 sbridge_unregister_mci(sbridge_dev);
2519
2520 /* Release PCI resources */
2521 sbridge_put_all_devices();
2522
2523 probed--;
2524
2525 mutex_unlock(&sbridge_edac_lock);
2526 }
2527
2528 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2529
2530 /*
2531 * sbridge_driver pci_driver structure for this module
2532 *
2533 */
2534 static struct pci_driver sbridge_driver = {
2535 .name = "sbridge_edac",
2536 .probe = sbridge_probe,
2537 .remove = sbridge_remove,
2538 .id_table = sbridge_pci_tbl,
2539 };
2540
2541 /*
2542 * sbridge_init Module entry function
2543 * Try to initialize this module for its devices
2544 */
2545 static int __init sbridge_init(void)
2546 {
2547 int pci_rc;
2548
2549 edac_dbg(2, "\n");
2550
2551 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2552 opstate_init();
2553
2554 pci_rc = pci_register_driver(&sbridge_driver);
2555 if (pci_rc >= 0) {
2556 mce_register_decode_chain(&sbridge_mce_dec);
2557 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2558 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2559 return 0;
2560 }
2561
2562 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2563 pci_rc);
2564
2565 return pci_rc;
2566 }
2567
2568 /*
2569 * sbridge_exit() Module exit function
2570 * Unregister the driver
2571 */
2572 static void __exit sbridge_exit(void)
2573 {
2574 edac_dbg(2, "\n");
2575 pci_unregister_driver(&sbridge_driver);
2576 mce_unregister_decode_chain(&sbridge_mce_dec);
2577 }
2578
2579 module_init(sbridge_init);
2580 module_exit(sbridge_exit);
2581
2582 module_param(edac_op_state, int, 0444);
2583 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2584
2585 MODULE_LICENSE("GPL");
2586 MODULE_AUTHOR("Mauro Carvalho Chehab");
2587 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2588 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
2589 SBRIDGE_REVISION);
Linux with added FPC-III support