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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-baytrail.c
blobb2602210784dc0f47846a55de58edf5ebc9178dd
1 /*
2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/gpio.h>
29 #include <linux/acpi.h>
30 #include <linux/platform_device.h>
31 #include <linux/seq_file.h>
32 #include <linux/io.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/pinctrl/pinctrl.h>
35
36 /* memory mapped register offsets */
37 #define BYT_CONF0_REG 0x000
38 #define BYT_CONF1_REG 0x004
39 #define BYT_VAL_REG 0x008
40 #define BYT_DFT_REG 0x00c
41 #define BYT_INT_STAT_REG 0x800
42
43 /* BYT_CONF0_REG register bits */
44 #define BYT_IODEN BIT(31)
45 #define BYT_DIRECT_IRQ_EN BIT(27)
46 #define BYT_TRIG_NEG BIT(26)
47 #define BYT_TRIG_POS BIT(25)
48 #define BYT_TRIG_LVL BIT(24)
49 #define BYT_PULL_STR_SHIFT 9
50 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_ASSIGN_SHIFT 7
56 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
59 #define BYT_PIN_MUX 0x07
60
61 /* BYT_VAL_REG register bits */
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
65
66 #define BYT_DIR_MASK (BIT(1) | BIT(2))
67 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
68
69 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
70 BYT_PIN_MUX)
71 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
72
73 #define BYT_NGPIO_SCORE 102
74 #define BYT_NGPIO_NCORE 28
75 #define BYT_NGPIO_SUS 44
76
77 #define BYT_SCORE_ACPI_UID "1"
78 #define BYT_NCORE_ACPI_UID "2"
79 #define BYT_SUS_ACPI_UID "3"
80
81 /*
82 * Baytrail gpio controller consist of three separate sub-controllers called
83 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
84 *
85 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
86 * _not_ correspond to the first gpio register at controller's gpio base.
87 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
88 * each sub-controller needs to have its own mapping table
89 */
90
91 /* score_pins[gpio_nr] = pad_nr */
92
93 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
94 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
95 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
96 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
97 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
98 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
99 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
100 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
101 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
102 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
103 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
104 97, 100,
105 };
106
107 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
108 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
109 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
110 3, 6, 10, 13, 2, 5, 9, 7,
111 };
112
113 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
114 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
115 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
116 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
117 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
118 52, 53, 59, 40,
119 };
120
121 static struct pinctrl_gpio_range byt_ranges[] = {
122 {
123 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
124 .npins = BYT_NGPIO_SCORE,
125 .pins = score_pins,
126 },
127 {
128 .name = BYT_NCORE_ACPI_UID,
129 .npins = BYT_NGPIO_NCORE,
130 .pins = ncore_pins,
131 },
132 {
133 .name = BYT_SUS_ACPI_UID,
134 .npins = BYT_NGPIO_SUS,
135 .pins = sus_pins,
136 },
137 {
138 },
139 };
140
141 struct byt_gpio_pin_context {
142 u32 conf0;
143 u32 val;
144 };
145
146 struct byt_gpio {
147 struct gpio_chip chip;
148 struct platform_device *pdev;
149 raw_spinlock_t lock;
150 void __iomem *reg_base;
151 struct pinctrl_gpio_range *range;
152 struct byt_gpio_pin_context *saved_context;
153 };
154
155 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
156
157 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
158 int reg)
159 {
160 struct byt_gpio *vg = to_byt_gpio(chip);
161 u32 reg_offset;
162
163 if (reg == BYT_INT_STAT_REG)
164 reg_offset = (offset / 32) * 4;
165 else
166 reg_offset = vg->range->pins[offset] * 16;
167
168 return vg->reg_base + reg_offset + reg;
169 }
170
171 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
172 {
173 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
174 unsigned long flags;
175 u32 value;
176
177 raw_spin_lock_irqsave(&vg->lock, flags);
178 value = readl(reg);
179 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
180 writel(value, reg);
181 raw_spin_unlock_irqrestore(&vg->lock, flags);
182 }
183
184 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
185 {
186 /* SCORE pin 92-93 */
187 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
188 offset >= 92 && offset <= 93)
189 return 1;
190
191 /* SUS pin 11-21 */
192 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
193 offset >= 11 && offset <= 21)
194 return 1;
195
196 return 0;
197 }
198
199 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
200 {
201 struct byt_gpio *vg = to_byt_gpio(chip);
202 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
203 u32 value, gpio_mux;
204 unsigned long flags;
205
206 raw_spin_lock_irqsave(&vg->lock, flags);
207
208 /*
209 * In most cases, func pin mux 000 means GPIO function.
210 * But, some pins may have func pin mux 001 represents
211 * GPIO function.
212 *
213 * Because there are devices out there where some pins were not
214 * configured correctly we allow changing the mux value from
215 * request (but print out warning about that).
216 */
217 value = readl(reg) & BYT_PIN_MUX;
218 gpio_mux = byt_get_gpio_mux(vg, offset);
219 if (WARN_ON(gpio_mux != value)) {
220 value = readl(reg) & ~BYT_PIN_MUX;
221 value |= gpio_mux;
222 writel(value, reg);
223
224 dev_warn(&vg->pdev->dev,
225 "pin %u forcibly re-configured as GPIO\n", offset);
226 }
227
228 raw_spin_unlock_irqrestore(&vg->lock, flags);
229
230 pm_runtime_get(&vg->pdev->dev);
231
232 return 0;
233 }
234
235 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
236 {
237 struct byt_gpio *vg = to_byt_gpio(chip);
238
239 byt_gpio_clear_triggering(vg, offset);
240 pm_runtime_put(&vg->pdev->dev);
241 }
242
243 static int byt_irq_type(struct irq_data *d, unsigned type)
244 {
245 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
246 u32 offset = irqd_to_hwirq(d);
247 u32 value;
248 unsigned long flags;
249 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
250
251 if (offset >= vg->chip.ngpio)
252 return -EINVAL;
253
254 raw_spin_lock_irqsave(&vg->lock, flags);
255 value = readl(reg);
256
257 WARN(value & BYT_DIRECT_IRQ_EN,
258 "Bad pad config for io mode, force direct_irq_en bit clearing");
259
260 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
261 * are used to indicate high and low level triggering
262 */
263 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
264 BYT_TRIG_LVL);
265
266 writel(value, reg);
267
268 if (type & IRQ_TYPE_EDGE_BOTH)
269 __irq_set_handler_locked(d->irq, handle_edge_irq);
270 else if (type & IRQ_TYPE_LEVEL_MASK)
271 __irq_set_handler_locked(d->irq, handle_level_irq);
272
273 raw_spin_unlock_irqrestore(&vg->lock, flags);
274
275 return 0;
276 }
277
278 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
279 {
280 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
281 struct byt_gpio *vg = to_byt_gpio(chip);
282 unsigned long flags;
283 u32 val;
284
285 raw_spin_lock_irqsave(&vg->lock, flags);
286 val = readl(reg);
287 raw_spin_unlock_irqrestore(&vg->lock, flags);
288
289 return val & BYT_LEVEL;
290 }
291
292 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
293 {
294 struct byt_gpio *vg = to_byt_gpio(chip);
295 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
296 unsigned long flags;
297 u32 old_val;
298
299 raw_spin_lock_irqsave(&vg->lock, flags);
300
301 old_val = readl(reg);
302
303 if (value)
304 writel(old_val | BYT_LEVEL, reg);
305 else
306 writel(old_val & ~BYT_LEVEL, reg);
307
308 raw_spin_unlock_irqrestore(&vg->lock, flags);
309 }
310
311 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
312 {
313 struct byt_gpio *vg = to_byt_gpio(chip);
314 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
315 unsigned long flags;
316 u32 value;
317
318 raw_spin_lock_irqsave(&vg->lock, flags);
319
320 value = readl(reg) | BYT_DIR_MASK;
321 value &= ~BYT_INPUT_EN; /* active low */
322 writel(value, reg);
323
324 raw_spin_unlock_irqrestore(&vg->lock, flags);
325
326 return 0;
327 }
328
329 static int byt_gpio_direction_output(struct gpio_chip *chip,
330 unsigned gpio, int value)
331 {
332 struct byt_gpio *vg = to_byt_gpio(chip);
333 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
334 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
335 unsigned long flags;
336 u32 reg_val;
337
338 raw_spin_lock_irqsave(&vg->lock, flags);
339
340 /*
341 * Before making any direction modifications, do a check if gpio
342 * is set for direct IRQ. On baytrail, setting GPIO to output does
343 * not make sense, so let's at least warn the caller before they shoot
344 * themselves in the foot.
345 */
346 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
347 "Potential Error: Setting GPIO with direct_irq_en to output");
348
349 reg_val = readl(reg) | BYT_DIR_MASK;
350 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
351
352 if (value)
353 writel(reg_val | BYT_LEVEL, reg);
354 else
355 writel(reg_val & ~BYT_LEVEL, reg);
356
357 raw_spin_unlock_irqrestore(&vg->lock, flags);
358
359 return 0;
360 }
361
362 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
363 {
364 struct byt_gpio *vg = to_byt_gpio(chip);
365 int i;
366 u32 conf0, val, offs;
367
368 for (i = 0; i < vg->chip.ngpio; i++) {
369 const char *pull_str = NULL;
370 const char *pull = NULL;
371 unsigned long flags;
372 const char *label;
373 offs = vg->range->pins[i] * 16;
374
375 raw_spin_lock_irqsave(&vg->lock, flags);
376 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
377 val = readl(vg->reg_base + offs + BYT_VAL_REG);
378 raw_spin_unlock_irqrestore(&vg->lock, flags);
379
380 label = gpiochip_is_requested(chip, i);
381 if (!label)
382 label = "Unrequested";
383
384 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
385 case BYT_PULL_ASSIGN_UP:
386 pull = "up";
387 break;
388 case BYT_PULL_ASSIGN_DOWN:
389 pull = "down";
390 break;
391 }
392
393 switch (conf0 & BYT_PULL_STR_MASK) {
394 case BYT_PULL_STR_2K:
395 pull_str = "2k";
396 break;
397 case BYT_PULL_STR_10K:
398 pull_str = "10k";
399 break;
400 case BYT_PULL_STR_20K:
401 pull_str = "20k";
402 break;
403 case BYT_PULL_STR_40K:
404 pull_str = "40k";
405 break;
406 }
407
408 seq_printf(s,
409 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
410 i,
411 label,
412 val & BYT_INPUT_EN ? " " : "in",
413 val & BYT_OUTPUT_EN ? " " : "out",
414 val & BYT_LEVEL ? "hi" : "lo",
415 vg->range->pins[i], offs,
416 conf0 & 0x7,
417 conf0 & BYT_TRIG_NEG ? " fall" : " ",
418 conf0 & BYT_TRIG_POS ? " rise" : " ",
419 conf0 & BYT_TRIG_LVL ? " level" : " ");
420
421 if (pull && pull_str)
422 seq_printf(s, " %-4s %-3s", pull, pull_str);
423 else
424 seq_puts(s, " ");
425
426 if (conf0 & BYT_IODEN)
427 seq_puts(s, " open-drain");
428
429 seq_puts(s, "\n");
430 }
431 }
432
433 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
434 {
435 struct irq_data *data = irq_desc_get_irq_data(desc);
436 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
437 struct irq_chip *chip = irq_data_get_irq_chip(data);
438 u32 base, pin;
439 void __iomem *reg;
440 unsigned long pending;
441 unsigned virq;
442
443 /* check from GPIO controller which pin triggered the interrupt */
444 for (base = 0; base < vg->chip.ngpio; base += 32) {
445 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
446 pending = readl(reg);
447 for_each_set_bit(pin, &pending, 32) {
448 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
449 generic_handle_irq(virq);
450 }
451 }
452 chip->irq_eoi(data);
453 }
454
455 static void byt_irq_ack(struct irq_data *d)
456 {
457 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
458 struct byt_gpio *vg = to_byt_gpio(gc);
459 unsigned offset = irqd_to_hwirq(d);
460 void __iomem *reg;
461
462 raw_spin_lock(&vg->lock);
463 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
464 writel(BIT(offset % 32), reg);
465 raw_spin_unlock(&vg->lock);
466 }
467
468 static void byt_irq_unmask(struct irq_data *d)
469 {
470 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
471 struct byt_gpio *vg = to_byt_gpio(gc);
472 unsigned offset = irqd_to_hwirq(d);
473 unsigned long flags;
474 void __iomem *reg;
475 u32 value;
476
477 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
478
479 raw_spin_lock_irqsave(&vg->lock, flags);
480 value = readl(reg);
481
482 switch (irqd_get_trigger_type(d)) {
483 case IRQ_TYPE_LEVEL_HIGH:
484 value |= BYT_TRIG_LVL;
485 case IRQ_TYPE_EDGE_RISING:
486 value |= BYT_TRIG_POS;
487 break;
488 case IRQ_TYPE_LEVEL_LOW:
489 value |= BYT_TRIG_LVL;
490 case IRQ_TYPE_EDGE_FALLING:
491 value |= BYT_TRIG_NEG;
492 break;
493 case IRQ_TYPE_EDGE_BOTH:
494 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
495 break;
496 }
497
498 writel(value, reg);
499
500 raw_spin_unlock_irqrestore(&vg->lock, flags);
501 }
502
503 static void byt_irq_mask(struct irq_data *d)
504 {
505 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
506 struct byt_gpio *vg = to_byt_gpio(gc);
507
508 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
509 }
510
511 static struct irq_chip byt_irqchip = {
512 .name = "BYT-GPIO",
513 .irq_ack = byt_irq_ack,
514 .irq_mask = byt_irq_mask,
515 .irq_unmask = byt_irq_unmask,
516 .irq_set_type = byt_irq_type,
517 .flags = IRQCHIP_SKIP_SET_WAKE,
518 };
519
520 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
521 {
522 void __iomem *reg;
523 u32 base, value;
524 int i;
525
526 /*
527 * Clear interrupt triggers for all pins that are GPIOs and
528 * do not use direct IRQ mode. This will prevent spurious
529 * interrupts from misconfigured pins.
530 */
531 for (i = 0; i < vg->chip.ngpio; i++) {
532 value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
533 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
534 !(value & BYT_DIRECT_IRQ_EN)) {
535 byt_gpio_clear_triggering(vg, i);
536 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
537 }
538 }
539
540 /* clear interrupt status trigger registers */
541 for (base = 0; base < vg->chip.ngpio; base += 32) {
542 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
543 writel(0xffffffff, reg);
544 /* make sure trigger bits are cleared, if not then a pin
545 might be misconfigured in bios */
546 value = readl(reg);
547 if (value)
548 dev_err(&vg->pdev->dev,
549 "GPIO interrupt error, pins misconfigured\n");
550 }
551 }
552
553 static int byt_gpio_probe(struct platform_device *pdev)
554 {
555 struct byt_gpio *vg;
556 struct gpio_chip *gc;
557 struct resource *mem_rc, *irq_rc;
558 struct device *dev = &pdev->dev;
559 struct acpi_device *acpi_dev;
560 struct pinctrl_gpio_range *range;
561 acpi_handle handle = ACPI_HANDLE(dev);
562 int ret;
563
564 if (acpi_bus_get_device(handle, &acpi_dev))
565 return -ENODEV;
566
567 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
568 if (!vg) {
569 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
570 return -ENOMEM;
571 }
572
573 for (range = byt_ranges; range->name; range++) {
574 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
575 vg->chip.ngpio = range->npins;
576 vg->range = range;
577 break;
578 }
579 }
580
581 if (!vg->chip.ngpio || !vg->range)
582 return -ENODEV;
583
584 vg->pdev = pdev;
585 platform_set_drvdata(pdev, vg);
586
587 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
588 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
589 if (IS_ERR(vg->reg_base))
590 return PTR_ERR(vg->reg_base);
591
592 raw_spin_lock_init(&vg->lock);
593
594 gc = &vg->chip;
595 gc->label = dev_name(&pdev->dev);
596 gc->owner = THIS_MODULE;
597 gc->request = byt_gpio_request;
598 gc->free = byt_gpio_free;
599 gc->direction_input = byt_gpio_direction_input;
600 gc->direction_output = byt_gpio_direction_output;
601 gc->get = byt_gpio_get;
602 gc->set = byt_gpio_set;
603 gc->dbg_show = byt_gpio_dbg_show;
604 gc->base = -1;
605 gc->can_sleep = false;
606 gc->dev = dev;
607
608 #ifdef CONFIG_PM_SLEEP
609 vg->saved_context = devm_kcalloc(&pdev->dev, gc->ngpio,
610 sizeof(*vg->saved_context), GFP_KERNEL);
611 #endif
612
613 ret = gpiochip_add(gc);
614 if (ret) {
615 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
616 return ret;
617 }
618
619 /* set up interrupts */
620 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
621 if (irq_rc && irq_rc->start) {
622 byt_gpio_irq_init_hw(vg);
623 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
624 handle_simple_irq, IRQ_TYPE_NONE);
625 if (ret) {
626 dev_err(dev, "failed to add irqchip\n");
627 gpiochip_remove(gc);
628 return ret;
629 }
630
631 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
632 (unsigned)irq_rc->start,
633 byt_gpio_irq_handler);
634 }
635
636 pm_runtime_enable(dev);
637
638 return 0;
639 }
640
641 #ifdef CONFIG_PM_SLEEP
642 static int byt_gpio_suspend(struct device *dev)
643 {
644 struct platform_device *pdev = to_platform_device(dev);
645 struct byt_gpio *vg = platform_get_drvdata(pdev);
646 int i;
647
648 for (i = 0; i < vg->chip.ngpio; i++) {
649 void __iomem *reg;
650 u32 value;
651
652 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
653 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
654 vg->saved_context[i].conf0 = value;
655
656 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
657 value = readl(reg) & BYT_VAL_RESTORE_MASK;
658 vg->saved_context[i].val = value;
659 }
660
661 return 0;
662 }
663
664 static int byt_gpio_resume(struct device *dev)
665 {
666 struct platform_device *pdev = to_platform_device(dev);
667 struct byt_gpio *vg = platform_get_drvdata(pdev);
668 int i;
669
670 for (i = 0; i < vg->chip.ngpio; i++) {
671 void __iomem *reg;
672 u32 value;
673
674 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
675 value = readl(reg);
676 if ((value & BYT_CONF0_RESTORE_MASK) !=
677 vg->saved_context[i].conf0) {
678 value &= ~BYT_CONF0_RESTORE_MASK;
679 value |= vg->saved_context[i].conf0;
680 writel(value, reg);
681 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
682 }
683
684 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
685 value = readl(reg);
686 if ((value & BYT_VAL_RESTORE_MASK) !=
687 vg->saved_context[i].val) {
688 u32 v;
689
690 v = value & ~BYT_VAL_RESTORE_MASK;
691 v |= vg->saved_context[i].val;
692 if (v != value) {
693 writel(v, reg);
694 dev_dbg(dev, "restored pin %d val %#08x\n",
695 i, v);
696 }
697 }
698 }
699
700 return 0;
701 }
702 #endif
703
704 static int byt_gpio_runtime_suspend(struct device *dev)
705 {
706 return 0;
707 }
708
709 static int byt_gpio_runtime_resume(struct device *dev)
710 {
711 return 0;
712 }
713
714 static const struct dev_pm_ops byt_gpio_pm_ops = {
715 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
716 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
717 NULL)
718 };
719
720 static const struct acpi_device_id byt_gpio_acpi_match[] = {
721 { "INT33B2", 0 },
722 { "INT33FC", 0 },
723 { }
724 };
725 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
726
727 static int byt_gpio_remove(struct platform_device *pdev)
728 {
729 struct byt_gpio *vg = platform_get_drvdata(pdev);
730
731 pm_runtime_disable(&pdev->dev);
732 gpiochip_remove(&vg->chip);
733
734 return 0;
735 }
736
737 static struct platform_driver byt_gpio_driver = {
738 .probe = byt_gpio_probe,
739 .remove = byt_gpio_remove,
740 .driver = {
741 .name = "byt_gpio",
742 .pm = &byt_gpio_pm_ops,
743 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
744 },
745 };
746
747 static int __init byt_gpio_init(void)
748 {
749 return platform_driver_register(&byt_gpio_driver);
750 }
751 subsys_initcall(byt_gpio_init);
752
753 static void __exit byt_gpio_exit(void)
754 {
755 platform_driver_unregister(&byt_gpio_driver);
756 }
757 module_exit(byt_gpio_exit);
Linux with added FPC-III support