gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-intel.h
blob4ec8b572a288fbc337f5b40affdfbd012634a028
1 /*
2 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef PINCTRL_INTEL_H
14 #define PINCTRL_INTEL_H
16 struct pinctrl_pin_desc;
17 struct platform_device;
18 struct device;
20 /**
21 * struct intel_pingroup - Description about group of pins
22 * @name: Name of the groups
23 * @pins: All pins in this group
24 * @npins: Number of pins in this groups
25 * @mode: Native mode in which the group is muxed out @pins
27 struct intel_pingroup {
28 const char *name;
29 const unsigned *pins;
30 size_t npins;
31 unsigned short mode;
34 /**
35 * struct intel_function - Description about a function
36 * @name: Name of the function
37 * @groups: An array of groups for this function
38 * @ngroups: Number of groups in @groups
40 struct intel_function {
41 const char *name;
42 const char * const *groups;
43 size_t ngroups;
46 /**
47 * struct intel_community - Intel pin community description
48 * @barno: MMIO BAR number where registers for this community reside
49 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
50 * then there is no support for owner.
51 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
52 * locking is not supported.
53 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
54 * is assumed that the host owns the pin (rather than
55 * ACPI).
56 * @ie_offset: Register offset of GPI_IE from @regs.
57 * @pin_base: Starting pin of pins in this community
58 * @npins: Number of pins in this community
59 * @regs: Community specific common registers (reserved for core driver)
60 * @pad_regs: Community specific pad registers (reserved for core driver)
61 * @ngpps: Number of groups (hw groups) in this community (reserved for
62 * core driver)
64 struct intel_community {
65 unsigned barno;
66 unsigned padown_offset;
67 unsigned padcfglock_offset;
68 unsigned hostown_offset;
69 unsigned ie_offset;
70 unsigned pin_base;
71 size_t npins;
72 void __iomem *regs;
73 void __iomem *pad_regs;
74 size_t ngpps;
77 #define PIN_GROUP(n, p, m) \
78 { \
79 .name = (n), \
80 .pins = (p), \
81 .npins = ARRAY_SIZE((p)), \
82 .mode = (m), \
85 #define FUNCTION(n, g) \
86 { \
87 .name = (n), \
88 .groups = (g), \
89 .ngroups = ARRAY_SIZE((g)), \
92 /**
93 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
94 * @uid: ACPI _UID for the probe driver use if needed
95 * @pins: Array if pins this pinctrl controls
96 * @npins: Number of pins in the array
97 * @groups: Array of pin groups
98 * @ngroups: Number of groups in the array
99 * @functions: Array of functions
100 * @nfunctions: Number of functions in the array
101 * @communities: Array of communities this pinctrl handles
102 * @ncommunities: Number of communities in the array
104 * The @communities is used as a template by the core driver. It will make
105 * copy of all communities and fill in rest of the information.
107 struct intel_pinctrl_soc_data {
108 const char *uid;
109 const struct pinctrl_pin_desc *pins;
110 size_t npins;
111 const struct intel_pingroup *groups;
112 size_t ngroups;
113 const struct intel_function *functions;
114 size_t nfunctions;
115 const struct intel_community *communities;
116 size_t ncommunities;
119 int intel_pinctrl_probe(struct platform_device *pdev,
120 const struct intel_pinctrl_soc_data *soc_data);
121 int intel_pinctrl_remove(struct platform_device *pdev);
123 #ifdef CONFIG_PM_SLEEP
124 int intel_pinctrl_suspend(struct device *dev);
125 int intel_pinctrl_resume(struct device *dev);
126 #endif
128 #endif /* PINCTRL_INTEL_H */