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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
blobd32a72e96c72cba5a322c88d8d5afc74797a6cd0
1 /*
2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/io.h>
17 #include <linux/gpio.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/bitops.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <dt-bindings/pinctrl/mt65xx.h>
37
38 #include "../core.h"
39 #include "../pinconf.h"
40 #include "../pinctrl-utils.h"
41 #include "pinctrl-mtk-common.h"
42
43 #define MAX_GPIO_MODE_PER_REG 5
44 #define GPIO_MODE_BITS 3
45
46 static const char * const mtk_gpio_functions[] = {
47 "func0", "func1", "func2", "func3",
48 "func4", "func5", "func6", "func7",
49 };
50
51 /*
52 * There are two base address for pull related configuration
53 * in mt8135, and different GPIO pins use different base address.
54 * When pin number greater than type1_start and less than type1_end,
55 * should use the second base address.
56 */
57 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
58 unsigned long pin)
59 {
60 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
61 return pctl->regmap2;
62 return pctl->regmap1;
63 }
64
65 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
66 {
67 /* Different SoC has different mask and port shift. */
68 return ((pin >> 4) & pctl->devdata->port_mask)
69 << pctl->devdata->port_shf;
70 }
71
72 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
73 struct pinctrl_gpio_range *range, unsigned offset,
74 bool input)
75 {
76 unsigned int reg_addr;
77 unsigned int bit;
78 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
79
80 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
81 bit = BIT(offset & 0xf);
82
83 if (input)
84 /* Different SoC has different alignment offset. */
85 reg_addr = CLR_ADDR(reg_addr, pctl);
86 else
87 reg_addr = SET_ADDR(reg_addr, pctl);
88
89 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
90 return 0;
91 }
92
93 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
94 {
95 unsigned int reg_addr;
96 unsigned int bit;
97 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
98
99 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
100 bit = BIT(offset & 0xf);
101
102 if (value)
103 reg_addr = SET_ADDR(reg_addr, pctl);
104 else
105 reg_addr = CLR_ADDR(reg_addr, pctl);
106
107 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
108 }
109
110 static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
111 int value, enum pin_config_param param)
112 {
113 unsigned int reg_addr, offset;
114 unsigned int bit;
115 int ret;
116
117 /*
118 * Due to some pins are irregular, their input enable and smt
119 * control register are discontinuous, but they are mapping together.
120 * So we need this special handle.
121 */
122 if (pctl->devdata->spec_ies_smt_set) {
123 ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
124 pin, pctl->devdata->port_align, value);
125 if (!ret)
126 return;
127 }
128
129 bit = BIT(pin & 0xf);
130
131 if (param == PIN_CONFIG_INPUT_ENABLE)
132 offset = pctl->devdata->ies_offset;
133 else
134 offset = pctl->devdata->smt_offset;
135
136 if (value)
137 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
138 else
139 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
140
141 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
142 }
143
144 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
145 struct mtk_pinctrl *pctl, unsigned long pin) {
146 int i;
147
148 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
149 const struct mtk_pin_drv_grp *pin_drv =
150 pctl->devdata->pin_drv_grp + i;
151 if (pin == pin_drv->pin)
152 return pin_drv;
153 }
154
155 return NULL;
156 }
157
158 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
159 unsigned int pin, unsigned char driving)
160 {
161 const struct mtk_pin_drv_grp *pin_drv;
162 unsigned int val;
163 unsigned int bits, mask, shift;
164 const struct mtk_drv_group_desc *drv_grp;
165
166 if (pin >= pctl->devdata->npins)
167 return -EINVAL;
168
169 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
170 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
171 return -EINVAL;
172
173 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
174 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
175 && !(driving % drv_grp->step)) {
176 val = driving / drv_grp->step - 1;
177 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
178 mask = BIT(bits) - 1;
179 shift = pin_drv->bit + drv_grp->low_bit;
180 mask <<= shift;
181 val <<= shift;
182 return regmap_update_bits(mtk_get_regmap(pctl, pin),
183 pin_drv->offset, mask, val);
184 }
185
186 return -EINVAL;
187 }
188
189 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
190 unsigned int pin, bool enable, bool isup, unsigned int arg)
191 {
192 unsigned int bit;
193 unsigned int reg_pullen, reg_pullsel;
194 int ret;
195
196 /* Some pins' pull setting are very different,
197 * they have separate pull up/down bit, R0 and R1
198 * resistor bit, so we need this special handle.
199 */
200 if (pctl->devdata->spec_pull_set) {
201 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
202 pin, pctl->devdata->port_align, isup, arg);
203 if (!ret)
204 return 0;
205 }
206
207 /* For generic pull config, default arg value should be 0 or 1. */
208 if (arg != 0 && arg != 1) {
209 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
210 arg, pin);
211 return -EINVAL;
212 }
213
214 bit = BIT(pin & 0xf);
215 if (enable)
216 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
217 pctl->devdata->pullen_offset, pctl);
218 else
219 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
220 pctl->devdata->pullen_offset, pctl);
221
222 if (isup)
223 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
224 pctl->devdata->pullsel_offset, pctl);
225 else
226 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
227 pctl->devdata->pullsel_offset, pctl);
228
229 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
230 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
231 return 0;
232 }
233
234 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
235 unsigned int pin, enum pin_config_param param,
236 enum pin_config_param arg)
237 {
238 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
239
240 switch (param) {
241 case PIN_CONFIG_BIAS_DISABLE:
242 mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
243 break;
244 case PIN_CONFIG_BIAS_PULL_UP:
245 mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
246 break;
247 case PIN_CONFIG_BIAS_PULL_DOWN:
248 mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
249 break;
250 case PIN_CONFIG_INPUT_ENABLE:
251 mtk_pconf_set_ies_smt(pctl, pin, arg, param);
252 break;
253 case PIN_CONFIG_OUTPUT:
254 mtk_gpio_set(pctl->chip, pin, arg);
255 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
256 break;
257 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
258 mtk_pconf_set_ies_smt(pctl, pin, arg, param);
259 break;
260 case PIN_CONFIG_DRIVE_STRENGTH:
261 mtk_pconf_set_driving(pctl, pin, arg);
262 break;
263 default:
264 return -EINVAL;
265 }
266
267 return 0;
268 }
269
270 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
271 unsigned group,
272 unsigned long *config)
273 {
274 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
275
276 *config = pctl->groups[group].config;
277
278 return 0;
279 }
280
281 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
282 unsigned long *configs, unsigned num_configs)
283 {
284 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
285 struct mtk_pinctrl_group *g = &pctl->groups[group];
286 int i;
287
288 for (i = 0; i < num_configs; i++) {
289 mtk_pconf_parse_conf(pctldev, g->pin,
290 pinconf_to_config_param(configs[i]),
291 pinconf_to_config_argument(configs[i]));
292
293 g->config = configs[i];
294 }
295
296 return 0;
297 }
298
299 static const struct pinconf_ops mtk_pconf_ops = {
300 .pin_config_group_get = mtk_pconf_group_get,
301 .pin_config_group_set = mtk_pconf_group_set,
302 };
303
304 static struct mtk_pinctrl_group *
305 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
306 {
307 int i;
308
309 for (i = 0; i < pctl->ngroups; i++) {
310 struct mtk_pinctrl_group *grp = pctl->groups + i;
311
312 if (grp->pin == pin)
313 return grp;
314 }
315
316 return NULL;
317 }
318
319 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
320 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
321 {
322 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
323 const struct mtk_desc_function *func = pin->functions;
324
325 while (func && func->name) {
326 if (func->muxval == fnum)
327 return func;
328 func++;
329 }
330
331 return NULL;
332 }
333
334 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
335 u32 pin_num, u32 fnum)
336 {
337 int i;
338
339 for (i = 0; i < pctl->devdata->npins; i++) {
340 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
341
342 if (pin->pin.number == pin_num) {
343 const struct mtk_desc_function *func =
344 pin->functions;
345
346 while (func && func->name) {
347 if (func->muxval == fnum)
348 return true;
349 func++;
350 }
351
352 break;
353 }
354 }
355
356 return false;
357 }
358
359 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
360 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
361 struct pinctrl_map **map, unsigned *reserved_maps,
362 unsigned *num_maps)
363 {
364 bool ret;
365
366 if (*num_maps == *reserved_maps)
367 return -ENOSPC;
368
369 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
370 (*map)[*num_maps].data.mux.group = grp->name;
371
372 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
373 if (!ret) {
374 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
375 fnum, pin);
376 return -EINVAL;
377 }
378
379 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
380 (*num_maps)++;
381
382 return 0;
383 }
384
385 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
386 struct device_node *node,
387 struct pinctrl_map **map,
388 unsigned *reserved_maps,
389 unsigned *num_maps)
390 {
391 struct property *pins;
392 u32 pinfunc, pin, func;
393 int num_pins, num_funcs, maps_per_pin;
394 unsigned long *configs;
395 unsigned int num_configs;
396 bool has_config = 0;
397 int i, err;
398 unsigned reserve = 0;
399 struct mtk_pinctrl_group *grp;
400 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
401
402 pins = of_find_property(node, "pinmux", NULL);
403 if (!pins) {
404 dev_err(pctl->dev, "missing pins property in node %s .\n",
405 node->name);
406 return -EINVAL;
407 }
408
409 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
410 &num_configs);
411 if (num_configs)
412 has_config = 1;
413
414 num_pins = pins->length / sizeof(u32);
415 num_funcs = num_pins;
416 maps_per_pin = 0;
417 if (num_funcs)
418 maps_per_pin++;
419 if (has_config && num_pins >= 1)
420 maps_per_pin++;
421
422 if (!num_pins || !maps_per_pin)
423 return -EINVAL;
424
425 reserve = num_pins * maps_per_pin;
426
427 err = pinctrl_utils_reserve_map(pctldev, map,
428 reserved_maps, num_maps, reserve);
429 if (err < 0)
430 goto fail;
431
432 for (i = 0; i < num_pins; i++) {
433 err = of_property_read_u32_index(node, "pinmux",
434 i, &pinfunc);
435 if (err)
436 goto fail;
437
438 pin = MTK_GET_PIN_NO(pinfunc);
439 func = MTK_GET_PIN_FUNC(pinfunc);
440
441 if (pin >= pctl->devdata->npins ||
442 func >= ARRAY_SIZE(mtk_gpio_functions)) {
443 dev_err(pctl->dev, "invalid pins value.\n");
444 err = -EINVAL;
445 goto fail;
446 }
447
448 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
449 if (!grp) {
450 dev_err(pctl->dev, "unable to match pin %d to group\n",
451 pin);
452 return -EINVAL;
453 }
454
455 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
456 reserved_maps, num_maps);
457 if (err < 0)
458 goto fail;
459
460 if (has_config) {
461 err = pinctrl_utils_add_map_configs(pctldev, map,
462 reserved_maps, num_maps, grp->name,
463 configs, num_configs,
464 PIN_MAP_TYPE_CONFIGS_GROUP);
465 if (err < 0)
466 goto fail;
467 }
468 }
469
470 return 0;
471
472 fail:
473 return err;
474 }
475
476 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
477 struct device_node *np_config,
478 struct pinctrl_map **map, unsigned *num_maps)
479 {
480 struct device_node *np;
481 unsigned reserved_maps;
482 int ret;
483
484 *map = NULL;
485 *num_maps = 0;
486 reserved_maps = 0;
487
488 for_each_child_of_node(np_config, np) {
489 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
490 &reserved_maps, num_maps);
491 if (ret < 0) {
492 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
493 return ret;
494 }
495 }
496
497 return 0;
498 }
499
500 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
501 {
502 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
503
504 return pctl->ngroups;
505 }
506
507 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
508 unsigned group)
509 {
510 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
511
512 return pctl->groups[group].name;
513 }
514
515 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
516 unsigned group,
517 const unsigned **pins,
518 unsigned *num_pins)
519 {
520 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
521
522 *pins = (unsigned *)&pctl->groups[group].pin;
523 *num_pins = 1;
524
525 return 0;
526 }
527
528 static const struct pinctrl_ops mtk_pctrl_ops = {
529 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
530 .dt_free_map = pinctrl_utils_dt_free_map,
531 .get_groups_count = mtk_pctrl_get_groups_count,
532 .get_group_name = mtk_pctrl_get_group_name,
533 .get_group_pins = mtk_pctrl_get_group_pins,
534 };
535
536 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
537 {
538 return ARRAY_SIZE(mtk_gpio_functions);
539 }
540
541 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
542 unsigned selector)
543 {
544 return mtk_gpio_functions[selector];
545 }
546
547 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
548 unsigned function,
549 const char * const **groups,
550 unsigned * const num_groups)
551 {
552 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
553
554 *groups = pctl->grp_names;
555 *num_groups = pctl->ngroups;
556
557 return 0;
558 }
559
560 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
561 unsigned long pin, unsigned long mode)
562 {
563 unsigned int reg_addr;
564 unsigned char bit;
565 unsigned int val;
566 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
567 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
568
569 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
570 + pctl->devdata->pinmux_offset;
571
572 bit = pin % MAX_GPIO_MODE_PER_REG;
573 mask <<= (GPIO_MODE_BITS * bit);
574 val = (mode << (GPIO_MODE_BITS * bit));
575 return regmap_update_bits(mtk_get_regmap(pctl, pin),
576 reg_addr, mask, val);
577 }
578
579 static const struct mtk_desc_pin *
580 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
581 {
582 int i;
583 const struct mtk_desc_pin *pin;
584
585 for (i = 0; i < pctl->devdata->npins; i++) {
586 pin = pctl->devdata->pins + i;
587 if (pin->eint.eintnum == eint_num)
588 return pin;
589 }
590
591 return NULL;
592 }
593
594 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
595 unsigned function,
596 unsigned group)
597 {
598 bool ret;
599 const struct mtk_desc_function *desc;
600 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
601 struct mtk_pinctrl_group *g = pctl->groups + group;
602
603 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
604 if (!ret) {
605 dev_err(pctl->dev, "invaild function %d on group %d .\n",
606 function, group);
607 return -EINVAL;
608 }
609
610 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
611 if (!desc)
612 return -EINVAL;
613 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
614 return 0;
615 }
616
617 static const struct pinmux_ops mtk_pmx_ops = {
618 .get_functions_count = mtk_pmx_get_funcs_cnt,
619 .get_function_name = mtk_pmx_get_func_name,
620 .get_function_groups = mtk_pmx_get_func_groups,
621 .set_mux = mtk_pmx_set_mux,
622 .gpio_set_direction = mtk_pmx_gpio_set_direction,
623 };
624
625 static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
626 {
627 return pinctrl_request_gpio(chip->base + offset);
628 }
629
630 static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
631 {
632 pinctrl_free_gpio(chip->base + offset);
633 }
634
635 static int mtk_gpio_direction_input(struct gpio_chip *chip,
636 unsigned offset)
637 {
638 return pinctrl_gpio_direction_input(chip->base + offset);
639 }
640
641 static int mtk_gpio_direction_output(struct gpio_chip *chip,
642 unsigned offset, int value)
643 {
644 mtk_gpio_set(chip, offset, value);
645 return pinctrl_gpio_direction_output(chip->base + offset);
646 }
647
648 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
649 {
650 unsigned int reg_addr;
651 unsigned int bit;
652 unsigned int read_val = 0;
653
654 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
655
656 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
657 bit = BIT(offset & 0xf);
658 regmap_read(pctl->regmap1, reg_addr, &read_val);
659 return !!(read_val & bit);
660 }
661
662 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
663 {
664 unsigned int reg_addr;
665 unsigned int bit;
666 unsigned int read_val = 0;
667 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
668
669 if (mtk_gpio_get_direction(chip, offset))
670 reg_addr = mtk_get_port(pctl, offset) +
671 pctl->devdata->dout_offset;
672 else
673 reg_addr = mtk_get_port(pctl, offset) +
674 pctl->devdata->din_offset;
675
676 bit = BIT(offset & 0xf);
677 regmap_read(pctl->regmap1, reg_addr, &read_val);
678 return !!(read_val & bit);
679 }
680
681 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
682 {
683 const struct mtk_desc_pin *pin;
684 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
685 int irq;
686
687 pin = pctl->devdata->pins + offset;
688 if (pin->eint.eintnum == NO_EINT_SUPPORT)
689 return -EINVAL;
690
691 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
692 if (!irq)
693 return -EINVAL;
694
695 return irq;
696 }
697
698 static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
699 {
700 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
701 const struct mtk_desc_pin *pin;
702 int ret;
703
704 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
705
706 if (!pin) {
707 dev_err(pctl->dev, "Can not find pin\n");
708 return -EINVAL;
709 }
710
711 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
712 if (ret) {
713 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
714 irqd_to_hwirq(d));
715 return ret;
716 }
717
718 /* set mux to INT mode */
719 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
720
721 return 0;
722 }
723
724 static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
725 {
726 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
727 const struct mtk_desc_pin *pin;
728
729 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
730
731 if (!pin) {
732 dev_err(pctl->dev, "Can not find pin\n");
733 return;
734 }
735
736 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
737 }
738
739 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
740 unsigned int eint_num, unsigned int offset)
741 {
742 unsigned int eint_base = 0;
743 void __iomem *reg;
744
745 if (eint_num >= pctl->devdata->ap_num)
746 eint_base = pctl->devdata->ap_num;
747
748 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
749
750 return reg;
751 }
752
753 /*
754 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
755 * @eint_num: the EINT number to setmtk_pinctrl
756 */
757 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
758 unsigned int eint_num)
759 {
760 unsigned int sens;
761 unsigned int bit = BIT(eint_num % 32);
762 const struct mtk_eint_offsets *eint_offsets =
763 &pctl->devdata->eint_offsets;
764
765 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
766 eint_offsets->sens);
767
768 if (readl(reg) & bit)
769 sens = MT_LEVEL_SENSITIVE;
770 else
771 sens = MT_EDGE_SENSITIVE;
772
773 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
774 return 1;
775 else
776 return 0;
777 }
778
779 /*
780 * mtk_eint_get_mask: To get the eint mask
781 * @eint_num: the EINT number to get
782 */
783 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
784 unsigned int eint_num)
785 {
786 unsigned int bit = BIT(eint_num % 32);
787 const struct mtk_eint_offsets *eint_offsets =
788 &pctl->devdata->eint_offsets;
789
790 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
791 eint_offsets->mask);
792
793 return !!(readl(reg) & bit);
794 }
795
796 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
797 {
798 int start_level, curr_level;
799 unsigned int reg_offset;
800 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
801 u32 mask = 1 << (hwirq & 0x1f);
802 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
803 void __iomem *reg = pctl->eint_reg_base + (port << 2);
804 const struct mtk_desc_pin *pin;
805
806 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
807 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
808 do {
809 start_level = curr_level;
810 if (start_level)
811 reg_offset = eint_offsets->pol_clr;
812 else
813 reg_offset = eint_offsets->pol_set;
814 writel(mask, reg + reg_offset);
815
816 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
817 } while (start_level != curr_level);
818
819 return start_level;
820 }
821
822 static void mtk_eint_mask(struct irq_data *d)
823 {
824 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
825 const struct mtk_eint_offsets *eint_offsets =
826 &pctl->devdata->eint_offsets;
827 u32 mask = BIT(d->hwirq & 0x1f);
828 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
829 eint_offsets->mask_set);
830
831 writel(mask, reg);
832 }
833
834 static void mtk_eint_unmask(struct irq_data *d)
835 {
836 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
837 const struct mtk_eint_offsets *eint_offsets =
838 &pctl->devdata->eint_offsets;
839 u32 mask = BIT(d->hwirq & 0x1f);
840 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
841 eint_offsets->mask_clr);
842
843 writel(mask, reg);
844
845 if (pctl->eint_dual_edges[d->hwirq])
846 mtk_eint_flip_edge(pctl, d->hwirq);
847 }
848
849 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
850 unsigned debounce)
851 {
852 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
853 int eint_num, virq, eint_offset;
854 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
855 static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000,
856 128000, 256000};
857 const struct mtk_desc_pin *pin;
858 struct irq_data *d;
859
860 pin = pctl->devdata->pins + offset;
861 if (pin->eint.eintnum == NO_EINT_SUPPORT)
862 return -EINVAL;
863
864 eint_num = pin->eint.eintnum;
865 virq = irq_find_mapping(pctl->domain, eint_num);
866 eint_offset = (eint_num % 4) * 8;
867 d = irq_get_irq_data(virq);
868
869 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
870 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
871 if (!mtk_eint_can_en_debounce(pctl, eint_num))
872 return -ENOSYS;
873
874 dbnc = ARRAY_SIZE(debounce_time);
875 for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
876 if (debounce <= debounce_time[i]) {
877 dbnc = i;
878 break;
879 }
880 }
881
882 if (!mtk_eint_get_mask(pctl, eint_num)) {
883 mtk_eint_mask(d);
884 unmask = 1;
885 } else {
886 unmask = 0;
887 }
888
889 clr_bit = 0xff << eint_offset;
890 writel(clr_bit, pctl->eint_reg_base + clr_offset);
891
892 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
893 eint_offset;
894 rst = EINT_DBNC_RST_BIT << eint_offset;
895 writel(rst | bit, pctl->eint_reg_base + set_offset);
896
897 /* Delay a while (more than 2T) to wait for hw debounce counter reset
898 work correctly */
899 udelay(1);
900 if (unmask == 1)
901 mtk_eint_unmask(d);
902
903 return 0;
904 }
905
906 static struct gpio_chip mtk_gpio_chip = {
907 .owner = THIS_MODULE,
908 .request = mtk_gpio_request,
909 .free = mtk_gpio_free,
910 .direction_input = mtk_gpio_direction_input,
911 .direction_output = mtk_gpio_direction_output,
912 .get = mtk_gpio_get,
913 .set = mtk_gpio_set,
914 .to_irq = mtk_gpio_to_irq,
915 .set_debounce = mtk_gpio_set_debounce,
916 .of_gpio_n_cells = 2,
917 };
918
919 static int mtk_eint_set_type(struct irq_data *d,
920 unsigned int type)
921 {
922 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
923 const struct mtk_eint_offsets *eint_offsets =
924 &pctl->devdata->eint_offsets;
925 u32 mask = BIT(d->hwirq & 0x1f);
926 void __iomem *reg;
927
928 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
929 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
930 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
931 d->irq, d->hwirq, type);
932 return -EINVAL;
933 }
934
935 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
936 pctl->eint_dual_edges[d->hwirq] = 1;
937 else
938 pctl->eint_dual_edges[d->hwirq] = 0;
939
940 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
941 reg = mtk_eint_get_offset(pctl, d->hwirq,
942 eint_offsets->pol_clr);
943 writel(mask, reg);
944 } else {
945 reg = mtk_eint_get_offset(pctl, d->hwirq,
946 eint_offsets->pol_set);
947 writel(mask, reg);
948 }
949
950 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
951 reg = mtk_eint_get_offset(pctl, d->hwirq,
952 eint_offsets->sens_clr);
953 writel(mask, reg);
954 } else {
955 reg = mtk_eint_get_offset(pctl, d->hwirq,
956 eint_offsets->sens_set);
957 writel(mask, reg);
958 }
959
960 if (pctl->eint_dual_edges[d->hwirq])
961 mtk_eint_flip_edge(pctl, d->hwirq);
962
963 return 0;
964 }
965
966 static void mtk_eint_ack(struct irq_data *d)
967 {
968 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
969 const struct mtk_eint_offsets *eint_offsets =
970 &pctl->devdata->eint_offsets;
971 u32 mask = BIT(d->hwirq & 0x1f);
972 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
973 eint_offsets->ack);
974
975 writel(mask, reg);
976 }
977
978 static struct irq_chip mtk_pinctrl_irq_chip = {
979 .name = "mt-eint",
980 .irq_mask = mtk_eint_mask,
981 .irq_unmask = mtk_eint_unmask,
982 .irq_ack = mtk_eint_ack,
983 .irq_set_type = mtk_eint_set_type,
984 .irq_request_resources = mtk_pinctrl_irq_request_resources,
985 .irq_release_resources = mtk_pinctrl_irq_release_resources,
986 };
987
988 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
989 {
990 const struct mtk_eint_offsets *eint_offsets =
991 &pctl->devdata->eint_offsets;
992 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
993 unsigned int i;
994
995 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
996 writel(0xffffffff, reg);
997 reg += 4;
998 }
999 return 0;
1000 }
1001
1002 static inline void
1003 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1004 {
1005 unsigned int rst, ctrl_offset;
1006 unsigned int bit, dbnc;
1007 const struct mtk_eint_offsets *eint_offsets =
1008 &pctl->devdata->eint_offsets;
1009
1010 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1011 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1012 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1013 if ((bit & dbnc) > 0) {
1014 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1015 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1016 writel(rst, pctl->eint_reg_base + ctrl_offset);
1017 }
1018 }
1019
1020 static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
1021 {
1022 struct irq_chip *chip = irq_get_chip(irq);
1023 struct mtk_pinctrl *pctl = irq_get_handler_data(irq);
1024 unsigned int status, eint_num;
1025 int offset, index, virq;
1026 const struct mtk_eint_offsets *eint_offsets =
1027 &pctl->devdata->eint_offsets;
1028 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
1029 int dual_edges, start_level, curr_level;
1030 const struct mtk_desc_pin *pin;
1031
1032 chained_irq_enter(chip, desc);
1033 for (eint_num = 0;
1034 eint_num < pctl->devdata->ap_num;
1035 eint_num += 32, reg += 4) {
1036 status = readl(reg);
1037 while (status) {
1038 offset = __ffs(status);
1039 index = eint_num + offset;
1040 virq = irq_find_mapping(pctl->domain, index);
1041 status &= ~BIT(offset);
1042
1043 dual_edges = pctl->eint_dual_edges[index];
1044 if (dual_edges) {
1045 /* Clear soft-irq in case we raised it
1046 last time */
1047 writel(BIT(offset), reg - eint_offsets->stat +
1048 eint_offsets->soft_clr);
1049
1050 pin = mtk_find_pin_by_eint_num(pctl, index);
1051 start_level = mtk_gpio_get(pctl->chip,
1052 pin->pin.number);
1053 }
1054
1055 generic_handle_irq(virq);
1056
1057 if (dual_edges) {
1058 curr_level = mtk_eint_flip_edge(pctl, index);
1059
1060 /* If level changed, we might lost one edge
1061 interrupt, raised it through soft-irq */
1062 if (start_level != curr_level)
1063 writel(BIT(offset), reg -
1064 eint_offsets->stat +
1065 eint_offsets->soft_set);
1066 }
1067
1068 if (index < pctl->devdata->db_cnt)
1069 mtk_eint_debounce_process(pctl , index);
1070 }
1071 }
1072 chained_irq_exit(chip, desc);
1073 }
1074
1075 static int mtk_pctrl_build_state(struct platform_device *pdev)
1076 {
1077 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1078 int i;
1079
1080 pctl->ngroups = pctl->devdata->npins;
1081
1082 /* Allocate groups */
1083 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1084 sizeof(*pctl->groups), GFP_KERNEL);
1085 if (!pctl->groups)
1086 return -ENOMEM;
1087
1088 /* We assume that one pin is one group, use pin name as group name. */
1089 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1090 sizeof(*pctl->grp_names), GFP_KERNEL);
1091 if (!pctl->grp_names)
1092 return -ENOMEM;
1093
1094 for (i = 0; i < pctl->devdata->npins; i++) {
1095 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1096 struct mtk_pinctrl_group *group = pctl->groups + i;
1097
1098 group->name = pin->pin.name;
1099 group->pin = pin->pin.number;
1100
1101 pctl->grp_names[i] = pin->pin.name;
1102 }
1103
1104 return 0;
1105 }
1106
1107 static struct pinctrl_desc mtk_pctrl_desc = {
1108 .confops = &mtk_pconf_ops,
1109 .pctlops = &mtk_pctrl_ops,
1110 .pmxops = &mtk_pmx_ops,
1111 };
1112
1113 int mtk_pctrl_init(struct platform_device *pdev,
1114 const struct mtk_pinctrl_devdata *data)
1115 {
1116 struct pinctrl_pin_desc *pins;
1117 struct mtk_pinctrl *pctl;
1118 struct device_node *np = pdev->dev.of_node, *node;
1119 struct property *prop;
1120 struct resource *res;
1121 int i, ret, irq;
1122
1123 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1124 if (!pctl)
1125 return -ENOMEM;
1126
1127 platform_set_drvdata(pdev, pctl);
1128
1129 prop = of_find_property(np, "pins-are-numbered", NULL);
1130 if (!prop) {
1131 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1132 return -EINVAL;
1133 }
1134
1135 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1136 if (node) {
1137 pctl->regmap1 = syscon_node_to_regmap(node);
1138 if (IS_ERR(pctl->regmap1))
1139 return PTR_ERR(pctl->regmap1);
1140 }
1141
1142 /* Only 8135 has two base addr, other SoCs have only one. */
1143 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1144 if (node) {
1145 pctl->regmap2 = syscon_node_to_regmap(node);
1146 if (IS_ERR(pctl->regmap2))
1147 return PTR_ERR(pctl->regmap2);
1148 }
1149
1150 pctl->devdata = data;
1151 ret = mtk_pctrl_build_state(pdev);
1152 if (ret) {
1153 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1154 return -EINVAL;
1155 }
1156
1157 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1158 GFP_KERNEL);
1159 if (!pins)
1160 return -ENOMEM;
1161
1162 for (i = 0; i < pctl->devdata->npins; i++)
1163 pins[i] = pctl->devdata->pins[i].pin;
1164 mtk_pctrl_desc.name = dev_name(&pdev->dev);
1165 mtk_pctrl_desc.owner = THIS_MODULE;
1166 mtk_pctrl_desc.pins = pins;
1167 mtk_pctrl_desc.npins = pctl->devdata->npins;
1168 pctl->dev = &pdev->dev;
1169 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
1170 if (!pctl->pctl_dev) {
1171 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1172 return -EINVAL;
1173 }
1174
1175 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1176 if (!pctl->chip) {
1177 ret = -ENOMEM;
1178 goto pctrl_error;
1179 }
1180
1181 pctl->chip = &mtk_gpio_chip;
1182 pctl->chip->ngpio = pctl->devdata->npins;
1183 pctl->chip->label = dev_name(&pdev->dev);
1184 pctl->chip->dev = &pdev->dev;
1185 pctl->chip->base = 0;
1186
1187 ret = gpiochip_add(pctl->chip);
1188 if (ret) {
1189 ret = -EINVAL;
1190 goto pctrl_error;
1191 }
1192
1193 /* Register the GPIO to pin mappings. */
1194 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1195 0, 0, pctl->devdata->npins);
1196 if (ret) {
1197 ret = -EINVAL;
1198 goto chip_error;
1199 }
1200
1201 /* Get EINT register base from dts. */
1202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203 if (!res) {
1204 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1205 ret = -EINVAL;
1206 goto chip_error;
1207 }
1208
1209 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1210 if (IS_ERR(pctl->eint_reg_base)) {
1211 ret = -EINVAL;
1212 goto chip_error;
1213 }
1214
1215 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1216 sizeof(int), GFP_KERNEL);
1217 if (!pctl->eint_dual_edges) {
1218 ret = -ENOMEM;
1219 goto chip_error;
1220 }
1221
1222 irq = irq_of_parse_and_map(np, 0);
1223 if (!irq) {
1224 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1225 ret = -EINVAL;
1226 goto chip_error;
1227 }
1228
1229 pctl->domain = irq_domain_add_linear(np,
1230 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1231 if (!pctl->domain) {
1232 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1233 ret = -ENOMEM;
1234 goto chip_error;
1235 }
1236
1237 mtk_eint_init(pctl);
1238 for (i = 0; i < pctl->devdata->ap_num; i++) {
1239 int virq = irq_create_mapping(pctl->domain, i);
1240
1241 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1242 handle_level_irq);
1243 irq_set_chip_data(virq, pctl);
1244 set_irq_flags(virq, IRQF_VALID);
1245 };
1246
1247 irq_set_chained_handler(irq, mtk_eint_irq_handler);
1248 irq_set_handler_data(irq, pctl);
1249 set_irq_flags(irq, IRQF_VALID);
1250 return 0;
1251
1252 chip_error:
1253 gpiochip_remove(pctl->chip);
1254 pctrl_error:
1255 pinctrl_unregister(pctl->pctl_dev);
1256 return ret;
1257 }
1258
1259 MODULE_LICENSE("GPL");
1260 MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1261 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
Linux with added FPC-III support