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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-amd.c
blob4e1b3bf580935bfcd4a9d9aea9b0d82bd8d7d210
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
37
38 static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc)
39 {
40 return container_of(gc, struct amd_gpio, gc);
41 }
42
43 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
44 {
45 unsigned long flags;
46 u32 pin_reg;
47 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
48
49 spin_lock_irqsave(&gpio_dev->lock, flags);
50 pin_reg = readl(gpio_dev->base + offset * 4);
51 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
52 writel(pin_reg, gpio_dev->base + offset * 4);
53 spin_unlock_irqrestore(&gpio_dev->lock, flags);
54
55 return 0;
56 }
57
58 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
59 int value)
60 {
61 u32 pin_reg;
62 unsigned long flags;
63 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
64
65 spin_lock_irqsave(&gpio_dev->lock, flags);
66 pin_reg = readl(gpio_dev->base + offset * 4);
67 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
68 if (value)
69 pin_reg |= BIT(OUTPUT_VALUE_OFF);
70 else
71 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
72 writel(pin_reg, gpio_dev->base + offset * 4);
73 spin_unlock_irqrestore(&gpio_dev->lock, flags);
74
75 return 0;
76 }
77
78 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
79 {
80 u32 pin_reg;
81 unsigned long flags;
82 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
83
84 spin_lock_irqsave(&gpio_dev->lock, flags);
85 pin_reg = readl(gpio_dev->base + offset * 4);
86 spin_unlock_irqrestore(&gpio_dev->lock, flags);
87
88 return !!(pin_reg & BIT(PIN_STS_OFF));
89 }
90
91 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
92 {
93 u32 pin_reg;
94 unsigned long flags;
95 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
96
97 spin_lock_irqsave(&gpio_dev->lock, flags);
98 pin_reg = readl(gpio_dev->base + offset * 4);
99 if (value)
100 pin_reg |= BIT(OUTPUT_VALUE_OFF);
101 else
102 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
103 writel(pin_reg, gpio_dev->base + offset * 4);
104 spin_unlock_irqrestore(&gpio_dev->lock, flags);
105 }
106
107 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
108 unsigned debounce)
109 {
110 u32 time;
111 u32 pin_reg;
112 int ret = 0;
113 unsigned long flags;
114 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
115
116 spin_lock_irqsave(&gpio_dev->lock, flags);
117 pin_reg = readl(gpio_dev->base + offset * 4);
118
119 if (debounce) {
120 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
121 pin_reg &= ~DB_TMR_OUT_MASK;
122 /*
123 Debounce Debounce Timer Max
124 TmrLarge TmrOutUnit Unit Debounce
125 Time
126 0 0 61 usec (2 RtcClk) 976 usec
127 0 1 244 usec (8 RtcClk) 3.9 msec
128 1 0 15.6 msec (512 RtcClk) 250 msec
129 1 1 62.5 msec (2048 RtcClk) 1 sec
130 */
131
132 if (debounce < 61) {
133 pin_reg |= 1;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 976) {
137 time = debounce / 61;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 3900) {
142 time = debounce / 244;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 250000) {
147 time = debounce / 15600;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else if (debounce < 1000000) {
152 time = debounce / 62500;
153 pin_reg |= time & DB_TMR_OUT_MASK;
154 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
155 pin_reg |= BIT(DB_TMR_LARGE_OFF);
156 } else {
157 pin_reg &= ~DB_CNTRl_MASK;
158 ret = -EINVAL;
159 }
160 } else {
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
163 pin_reg &= ~DB_TMR_OUT_MASK;
164 pin_reg &= ~DB_CNTRl_MASK;
165 }
166 writel(pin_reg, gpio_dev->base + offset * 4);
167 spin_unlock_irqrestore(&gpio_dev->lock, flags);
168
169 return ret;
170 }
171
172 #ifdef CONFIG_DEBUG_FS
173 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
174 {
175 u32 pin_reg;
176 unsigned long flags;
177 unsigned int bank, i, pin_num;
178 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
179
180 char *level_trig;
181 char *active_level;
182 char *interrupt_enable;
183 char *interrupt_mask;
184 char *wake_cntrl0;
185 char *wake_cntrl1;
186 char *wake_cntrl2;
187 char *pin_sts;
188 char *pull_up_sel;
189 char *pull_up_enable;
190 char *pull_down_enable;
191 char *output_value;
192 char *output_enable;
193
194 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
195 seq_printf(s, "GPIO bank%d\t", bank);
196
197 switch (bank) {
198 case 0:
199 i = 0;
200 pin_num = AMD_GPIO_PINS_BANK0;
201 break;
202 case 1:
203 i = 64;
204 pin_num = AMD_GPIO_PINS_BANK1 + i;
205 break;
206 case 2:
207 i = 128;
208 pin_num = AMD_GPIO_PINS_BANK2 + i;
209 break;
210 }
211
212 for (; i < pin_num; i++) {
213 seq_printf(s, "pin%d\t", i);
214 spin_lock_irqsave(&gpio_dev->lock, flags);
215 pin_reg = readl(gpio_dev->base + i * 4);
216 spin_unlock_irqrestore(&gpio_dev->lock, flags);
217
218 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
219 interrupt_enable = "interrupt is enabled|";
220
221 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
222 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
223 active_level = "Active low|";
224 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
225 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
226 active_level = "Active high|";
227 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
228 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
229 active_level = "Active on both|";
230 else
231 active_level = "Unknow Active level|";
232
233 if (pin_reg & BIT(LEVEL_TRIG_OFF))
234 level_trig = "Level trigger|";
235 else
236 level_trig = "Edge trigger|";
237
238 } else {
239 interrupt_enable =
240 "interrupt is disabled|";
241 active_level = " ";
242 level_trig = " ";
243 }
244
245 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
246 interrupt_mask =
247 "interrupt is unmasked|";
248 else
249 interrupt_mask =
250 "interrupt is masked|";
251
252 if (pin_reg & BIT(WAKE_CNTRL_OFF))
253 wake_cntrl0 = "enable wakeup in S0i3 state|";
254 else
255 wake_cntrl0 = "disable wakeup in S0i3 state|";
256
257 if (pin_reg & BIT(WAKE_CNTRL_OFF))
258 wake_cntrl1 = "enable wakeup in S3 state|";
259 else
260 wake_cntrl1 = "disable wakeup in S3 state|";
261
262 if (pin_reg & BIT(WAKE_CNTRL_OFF))
263 wake_cntrl2 = "enable wakeup in S4/S5 state|";
264 else
265 wake_cntrl2 = "disable wakeup in S4/S5 state|";
266
267 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
268 pull_up_enable = "pull-up is enabled|";
269 if (pin_reg & BIT(PULL_UP_SEL_OFF))
270 pull_up_sel = "8k pull-up|";
271 else
272 pull_up_sel = "4k pull-up|";
273 } else {
274 pull_up_enable = "pull-up is disabled|";
275 pull_up_sel = " ";
276 }
277
278 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
279 pull_down_enable = "pull-down is enabled|";
280 else
281 pull_down_enable = "Pull-down is disabled|";
282
283 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
284 pin_sts = " ";
285 output_enable = "output is enabled|";
286 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
287 output_value = "output is high|";
288 else
289 output_value = "output is low|";
290 } else {
291 output_enable = "output is disabled|";
292 output_value = " ";
293
294 if (pin_reg & BIT(PIN_STS_OFF))
295 pin_sts = "input is high|";
296 else
297 pin_sts = "input is low|";
298 }
299
300 seq_printf(s, "%s %s %s %s %s %s\n"
301 " %s %s %s %s %s %s %s 0x%x\n",
302 level_trig, active_level, interrupt_enable,
303 interrupt_mask, wake_cntrl0, wake_cntrl1,
304 wake_cntrl2, pin_sts, pull_up_sel,
305 pull_up_enable, pull_down_enable,
306 output_value, output_enable, pin_reg);
307 }
308 }
309 }
310 #else
311 #define amd_gpio_dbg_show NULL
312 #endif
313
314 static void amd_gpio_irq_enable(struct irq_data *d)
315 {
316 u32 pin_reg;
317 unsigned long flags;
318 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
319 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
320
321 spin_lock_irqsave(&gpio_dev->lock, flags);
322 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
323 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
324 pin_reg |= BIT(INTERRUPT_MASK_OFF);
325 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
326 spin_unlock_irqrestore(&gpio_dev->lock, flags);
327 }
328
329 static void amd_gpio_irq_disable(struct irq_data *d)
330 {
331 u32 pin_reg;
332 unsigned long flags;
333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
334 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
335
336 spin_lock_irqsave(&gpio_dev->lock, flags);
337 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
338 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
339 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
340 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
341 spin_unlock_irqrestore(&gpio_dev->lock, flags);
342 }
343
344 static void amd_gpio_irq_mask(struct irq_data *d)
345 {
346 u32 pin_reg;
347 unsigned long flags;
348 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
349 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
350
351 spin_lock_irqsave(&gpio_dev->lock, flags);
352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
353 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
354 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
355 spin_unlock_irqrestore(&gpio_dev->lock, flags);
356 }
357
358 static void amd_gpio_irq_unmask(struct irq_data *d)
359 {
360 u32 pin_reg;
361 unsigned long flags;
362 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
363 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
364
365 spin_lock_irqsave(&gpio_dev->lock, flags);
366 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
367 pin_reg |= BIT(INTERRUPT_MASK_OFF);
368 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
369 spin_unlock_irqrestore(&gpio_dev->lock, flags);
370 }
371
372 static void amd_gpio_irq_eoi(struct irq_data *d)
373 {
374 u32 reg;
375 unsigned long flags;
376 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
377 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
378
379 spin_lock_irqsave(&gpio_dev->lock, flags);
380 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
381 reg |= EOI_MASK;
382 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
383 spin_unlock_irqrestore(&gpio_dev->lock, flags);
384 }
385
386 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
387 {
388 int ret = 0;
389 u32 pin_reg;
390 unsigned long flags;
391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
392 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
393
394 spin_lock_irqsave(&gpio_dev->lock, flags);
395 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
396
397 switch (type & IRQ_TYPE_SENSE_MASK) {
398 case IRQ_TYPE_EDGE_RISING:
399 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
400 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
401 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
402 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
403 __irq_set_handler_locked(d->irq, handle_edge_irq);
404 break;
405
406 case IRQ_TYPE_EDGE_FALLING:
407 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
408 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
409 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
410 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
411 __irq_set_handler_locked(d->irq, handle_edge_irq);
412 break;
413
414 case IRQ_TYPE_EDGE_BOTH:
415 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
416 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
417 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
418 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
419 __irq_set_handler_locked(d->irq, handle_edge_irq);
420 break;
421
422 case IRQ_TYPE_LEVEL_HIGH:
423 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
424 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
425 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
426 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
427 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
428 __irq_set_handler_locked(d->irq, handle_level_irq);
429 break;
430
431 case IRQ_TYPE_LEVEL_LOW:
432 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
433 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
434 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
435 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
436 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
437 __irq_set_handler_locked(d->irq, handle_level_irq);
438 break;
439
440 case IRQ_TYPE_NONE:
441 break;
442
443 default:
444 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
445 ret = -EINVAL;
446 }
447
448 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
449 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
450 spin_unlock_irqrestore(&gpio_dev->lock, flags);
451
452 return ret;
453 }
454
455 static void amd_irq_ack(struct irq_data *d)
456 {
457 /*
458 * based on HW design,there is no need to ack HW
459 * before handle current irq. But this routine is
460 * necessary for handle_edge_irq
461 */
462 }
463
464 static struct irq_chip amd_gpio_irqchip = {
465 .name = "amd_gpio",
466 .irq_ack = amd_irq_ack,
467 .irq_enable = amd_gpio_irq_enable,
468 .irq_disable = amd_gpio_irq_disable,
469 .irq_mask = amd_gpio_irq_mask,
470 .irq_unmask = amd_gpio_irq_unmask,
471 .irq_eoi = amd_gpio_irq_eoi,
472 .irq_set_type = amd_gpio_irq_set_type,
473 };
474
475 static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
476 {
477 u32 i;
478 u32 off;
479 u32 reg;
480 u32 pin_reg;
481 u64 reg64;
482 int handled = 0;
483 unsigned long flags;
484 struct irq_chip *chip = irq_get_chip(irq);
485 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
486 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
487
488 chained_irq_enter(chip, desc);
489 /*enable GPIO interrupt again*/
490 spin_lock_irqsave(&gpio_dev->lock, flags);
491 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
492 reg64 = reg;
493 reg64 = reg64 << 32;
494
495 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
496 reg64 |= reg;
497 spin_unlock_irqrestore(&gpio_dev->lock, flags);
498
499 /*
500 * first 46 bits indicates interrupt status.
501 * one bit represents four interrupt sources.
502 */
503 for (off = 0; off < 46 ; off++) {
504 if (reg64 & BIT(off)) {
505 for (i = 0; i < 4; i++) {
506 pin_reg = readl(gpio_dev->base +
507 (off * 4 + i) * 4);
508 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
509 (pin_reg & BIT(WAKE_STS_OFF))) {
510 irq = irq_find_mapping(gc->irqdomain,
511 off * 4 + i);
512 generic_handle_irq(irq);
513 writel(pin_reg,
514 gpio_dev->base
515 + (off * 4 + i) * 4);
516 handled++;
517 }
518 }
519 }
520 }
521
522 if (handled == 0)
523 handle_bad_irq(irq, desc);
524
525 spin_lock_irqsave(&gpio_dev->lock, flags);
526 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
527 reg |= EOI_MASK;
528 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
529 spin_unlock_irqrestore(&gpio_dev->lock, flags);
530
531 chained_irq_exit(chip, desc);
532 }
533
534 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
535 {
536 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
537
538 return gpio_dev->ngroups;
539 }
540
541 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
542 unsigned group)
543 {
544 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
545
546 return gpio_dev->groups[group].name;
547 }
548
549 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
550 unsigned group,
551 const unsigned **pins,
552 unsigned *num_pins)
553 {
554 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
555
556 *pins = gpio_dev->groups[group].pins;
557 *num_pins = gpio_dev->groups[group].npins;
558 return 0;
559 }
560
561 static const struct pinctrl_ops amd_pinctrl_ops = {
562 .get_groups_count = amd_get_groups_count,
563 .get_group_name = amd_get_group_name,
564 .get_group_pins = amd_get_group_pins,
565 #ifdef CONFIG_OF
566 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
567 .dt_free_map = pinctrl_utils_dt_free_map,
568 #endif
569 };
570
571 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
572 unsigned int pin,
573 unsigned long *config)
574 {
575 u32 pin_reg;
576 unsigned arg;
577 unsigned long flags;
578 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
579 enum pin_config_param param = pinconf_to_config_param(*config);
580
581 spin_lock_irqsave(&gpio_dev->lock, flags);
582 pin_reg = readl(gpio_dev->base + pin*4);
583 spin_unlock_irqrestore(&gpio_dev->lock, flags);
584 switch (param) {
585 case PIN_CONFIG_INPUT_DEBOUNCE:
586 arg = pin_reg & DB_TMR_OUT_MASK;
587 break;
588
589 case PIN_CONFIG_BIAS_PULL_DOWN:
590 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
591 break;
592
593 case PIN_CONFIG_BIAS_PULL_UP:
594 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
595 break;
596
597 case PIN_CONFIG_DRIVE_STRENGTH:
598 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
599 break;
600
601 default:
602 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
603 param);
604 return -ENOTSUPP;
605 }
606
607 *config = pinconf_to_config_packed(param, arg);
608
609 return 0;
610 }
611
612 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
613 unsigned long *configs, unsigned num_configs)
614 {
615 int i;
616 u32 arg;
617 int ret = 0;
618 u32 pin_reg;
619 unsigned long flags;
620 enum pin_config_param param;
621 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
622
623 spin_lock_irqsave(&gpio_dev->lock, flags);
624 for (i = 0; i < num_configs; i++) {
625 param = pinconf_to_config_param(configs[i]);
626 arg = pinconf_to_config_argument(configs[i]);
627 pin_reg = readl(gpio_dev->base + pin*4);
628
629 switch (param) {
630 case PIN_CONFIG_INPUT_DEBOUNCE:
631 pin_reg &= ~DB_TMR_OUT_MASK;
632 pin_reg |= arg & DB_TMR_OUT_MASK;
633 break;
634
635 case PIN_CONFIG_BIAS_PULL_DOWN:
636 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
637 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
638 break;
639
640 case PIN_CONFIG_BIAS_PULL_UP:
641 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
642 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
643 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
644 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
645 break;
646
647 case PIN_CONFIG_DRIVE_STRENGTH:
648 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
649 << DRV_STRENGTH_SEL_OFF);
650 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
651 << DRV_STRENGTH_SEL_OFF;
652 break;
653
654 default:
655 dev_err(&gpio_dev->pdev->dev,
656 "Invalid config param %04x\n", param);
657 ret = -ENOTSUPP;
658 }
659
660 writel(pin_reg, gpio_dev->base + pin*4);
661 }
662 spin_unlock_irqrestore(&gpio_dev->lock, flags);
663
664 return ret;
665 }
666
667 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
668 unsigned int group,
669 unsigned long *config)
670 {
671 const unsigned *pins;
672 unsigned npins;
673 int ret;
674
675 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
676 if (ret)
677 return ret;
678
679 if (amd_pinconf_get(pctldev, pins[0], config))
680 return -ENOTSUPP;
681
682 return 0;
683 }
684
685 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
686 unsigned group, unsigned long *configs,
687 unsigned num_configs)
688 {
689 const unsigned *pins;
690 unsigned npins;
691 int i, ret;
692
693 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
694 if (ret)
695 return ret;
696 for (i = 0; i < npins; i++) {
697 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
698 return -ENOTSUPP;
699 }
700 return 0;
701 }
702
703 static const struct pinconf_ops amd_pinconf_ops = {
704 .pin_config_get = amd_pinconf_get,
705 .pin_config_set = amd_pinconf_set,
706 .pin_config_group_get = amd_pinconf_group_get,
707 .pin_config_group_set = amd_pinconf_group_set,
708 };
709
710 static struct pinctrl_desc amd_pinctrl_desc = {
711 .pins = kerncz_pins,
712 .npins = ARRAY_SIZE(kerncz_pins),
713 .pctlops = &amd_pinctrl_ops,
714 .confops = &amd_pinconf_ops,
715 .owner = THIS_MODULE,
716 };
717
718 static int amd_gpio_probe(struct platform_device *pdev)
719 {
720 int ret = 0;
721 int irq_base;
722 struct resource *res;
723 struct amd_gpio *gpio_dev;
724
725 gpio_dev = devm_kzalloc(&pdev->dev,
726 sizeof(struct amd_gpio), GFP_KERNEL);
727 if (!gpio_dev)
728 return -ENOMEM;
729
730 spin_lock_init(&gpio_dev->lock);
731
732 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
733 if (!res) {
734 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
735 return -EINVAL;
736 }
737
738 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
739 resource_size(res));
740 if (IS_ERR(gpio_dev->base))
741 return PTR_ERR(gpio_dev->base);
742
743 irq_base = platform_get_irq(pdev, 0);
744 if (irq_base < 0) {
745 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
746 return -EINVAL;
747 }
748
749 gpio_dev->pdev = pdev;
750 gpio_dev->gc.direction_input = amd_gpio_direction_input;
751 gpio_dev->gc.direction_output = amd_gpio_direction_output;
752 gpio_dev->gc.get = amd_gpio_get_value;
753 gpio_dev->gc.set = amd_gpio_set_value;
754 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
755 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
756
757 gpio_dev->gc.base = 0;
758 gpio_dev->gc.label = pdev->name;
759 gpio_dev->gc.owner = THIS_MODULE;
760 gpio_dev->gc.dev = &pdev->dev;
761 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
762 #if defined(CONFIG_OF_GPIO)
763 gpio_dev->gc.of_node = pdev->dev.of_node;
764 #endif
765
766 gpio_dev->groups = kerncz_groups;
767 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
768
769 amd_pinctrl_desc.name = dev_name(&pdev->dev);
770 gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc,
771 &pdev->dev, gpio_dev);
772 if (!gpio_dev->pctrl) {
773 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
774 return -ENODEV;
775 }
776
777 ret = gpiochip_add(&gpio_dev->gc);
778 if (ret)
779 goto out1;
780
781 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
782 0, 0, TOTAL_NUMBER_OF_PINS);
783 if (ret) {
784 dev_err(&pdev->dev, "Failed to add pin range\n");
785 goto out2;
786 }
787
788 ret = gpiochip_irqchip_add(&gpio_dev->gc,
789 &amd_gpio_irqchip,
790 0,
791 handle_simple_irq,
792 IRQ_TYPE_NONE);
793 if (ret) {
794 dev_err(&pdev->dev, "could not add irqchip\n");
795 ret = -ENODEV;
796 goto out2;
797 }
798
799 gpiochip_set_chained_irqchip(&gpio_dev->gc,
800 &amd_gpio_irqchip,
801 irq_base,
802 amd_gpio_irq_handler);
803
804 platform_set_drvdata(pdev, gpio_dev);
805
806 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
807 return ret;
808
809 out2:
810 gpiochip_remove(&gpio_dev->gc);
811
812 out1:
813 pinctrl_unregister(gpio_dev->pctrl);
814 return ret;
815 }
816
817 static int amd_gpio_remove(struct platform_device *pdev)
818 {
819 struct amd_gpio *gpio_dev;
820
821 gpio_dev = platform_get_drvdata(pdev);
822
823 gpiochip_remove(&gpio_dev->gc);
824 pinctrl_unregister(gpio_dev->pctrl);
825
826 return 0;
827 }
828
829 static const struct acpi_device_id amd_gpio_acpi_match[] = {
830 { "AMD0030", 0 },
831 { },
832 };
833 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
834
835 static struct platform_driver amd_gpio_driver = {
836 .driver = {
837 .name = "amd_gpio",
838 .owner = THIS_MODULE,
839 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
840 },
841 .probe = amd_gpio_probe,
842 .remove = amd_gpio_remove,
843 };
844
845 module_platform_driver(amd_gpio_driver);
846
847 MODULE_LICENSE("GPL v2");
848 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
849 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux with added FPC-III support