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gro: Allow tunnel stacking in the case of FOU/GUE
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-zynq.c
blob8c51a3c65513a0101b3d16295dc32be074741b35
1 /*
2 * Zynq pin controller
3 *
4 * Copyright (C) 2014 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/regmap.h>
31 #include "pinctrl-utils.h"
32 #include "core.h"
33
34 #define ZYNQ_NUM_MIOS 54
35
36 #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
37 #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
38
39 #define ZYNQ_PINMUX_MUX_SHIFT 1
40 #define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
41
42 /**
43 * struct zynq_pinctrl - driver data
44 * @pctrl: Pinctrl device
45 * @syscon: Syscon regmap
46 * @pctrl_offset: Offset for pinctrl into the @syscon space
47 * @groups: Pingroups
48 * @ngroupos: Number of @groups
49 * @funcs: Pinmux functions
50 * @nfuncs: Number of @funcs
51 */
52 struct zynq_pinctrl {
53 struct pinctrl_dev *pctrl;
54 struct regmap *syscon;
55 u32 pctrl_offset;
56 const struct zynq_pctrl_group *groups;
57 unsigned int ngroups;
58 const struct zynq_pinmux_function *funcs;
59 unsigned int nfuncs;
60 };
61
62 struct zynq_pctrl_group {
63 const char *name;
64 const unsigned int *pins;
65 const unsigned npins;
66 };
67
68 /**
69 * struct zynq_pinmux_function - a pinmux function
70 * @name: Name of the pinmux function.
71 * @groups: List of pingroups for this function.
72 * @ngroups: Number of entries in @groups.
73 * @mux_val: Selector for this function
74 * @mux: Offset of function specific mux
75 * @mux_mask: Mask for function specific selector
76 * @mux_shift: Shift for function specific selector
77 */
78 struct zynq_pinmux_function {
79 const char *name;
80 const char * const *groups;
81 unsigned int ngroups;
82 unsigned int mux_val;
83 u32 mux;
84 u32 mux_mask;
85 u8 mux_shift;
86 };
87
88 enum zynq_pinmux_functions {
89 ZYNQ_PMUX_can0,
90 ZYNQ_PMUX_can1,
91 ZYNQ_PMUX_ethernet0,
92 ZYNQ_PMUX_ethernet1,
93 ZYNQ_PMUX_gpio0,
94 ZYNQ_PMUX_i2c0,
95 ZYNQ_PMUX_i2c1,
96 ZYNQ_PMUX_mdio0,
97 ZYNQ_PMUX_mdio1,
98 ZYNQ_PMUX_qspi0,
99 ZYNQ_PMUX_qspi1,
100 ZYNQ_PMUX_qspi_fbclk,
101 ZYNQ_PMUX_qspi_cs1,
102 ZYNQ_PMUX_spi0,
103 ZYNQ_PMUX_spi1,
104 ZYNQ_PMUX_sdio0,
105 ZYNQ_PMUX_sdio0_pc,
106 ZYNQ_PMUX_sdio0_cd,
107 ZYNQ_PMUX_sdio0_wp,
108 ZYNQ_PMUX_sdio1,
109 ZYNQ_PMUX_sdio1_pc,
110 ZYNQ_PMUX_sdio1_cd,
111 ZYNQ_PMUX_sdio1_wp,
112 ZYNQ_PMUX_smc0_nor,
113 ZYNQ_PMUX_smc0_nor_cs1,
114 ZYNQ_PMUX_smc0_nor_addr25,
115 ZYNQ_PMUX_smc0_nand,
116 ZYNQ_PMUX_ttc0,
117 ZYNQ_PMUX_ttc1,
118 ZYNQ_PMUX_uart0,
119 ZYNQ_PMUX_uart1,
120 ZYNQ_PMUX_usb0,
121 ZYNQ_PMUX_usb1,
122 ZYNQ_PMUX_swdt0,
123 ZYNQ_PMUX_MAX_FUNC
124 };
125
126 const struct pinctrl_pin_desc zynq_pins[] = {
127 PINCTRL_PIN(0, "MIO0"),
128 PINCTRL_PIN(1, "MIO1"),
129 PINCTRL_PIN(2, "MIO2"),
130 PINCTRL_PIN(3, "MIO3"),
131 PINCTRL_PIN(4, "MIO4"),
132 PINCTRL_PIN(5, "MIO5"),
133 PINCTRL_PIN(6, "MIO6"),
134 PINCTRL_PIN(7, "MIO7"),
135 PINCTRL_PIN(8, "MIO8"),
136 PINCTRL_PIN(9, "MIO9"),
137 PINCTRL_PIN(10, "MIO10"),
138 PINCTRL_PIN(11, "MIO11"),
139 PINCTRL_PIN(12, "MIO12"),
140 PINCTRL_PIN(13, "MIO13"),
141 PINCTRL_PIN(14, "MIO14"),
142 PINCTRL_PIN(15, "MIO15"),
143 PINCTRL_PIN(16, "MIO16"),
144 PINCTRL_PIN(17, "MIO17"),
145 PINCTRL_PIN(18, "MIO18"),
146 PINCTRL_PIN(19, "MIO19"),
147 PINCTRL_PIN(20, "MIO20"),
148 PINCTRL_PIN(21, "MIO21"),
149 PINCTRL_PIN(22, "MIO22"),
150 PINCTRL_PIN(23, "MIO23"),
151 PINCTRL_PIN(24, "MIO24"),
152 PINCTRL_PIN(25, "MIO25"),
153 PINCTRL_PIN(26, "MIO26"),
154 PINCTRL_PIN(27, "MIO27"),
155 PINCTRL_PIN(28, "MIO28"),
156 PINCTRL_PIN(29, "MIO29"),
157 PINCTRL_PIN(30, "MIO30"),
158 PINCTRL_PIN(31, "MIO31"),
159 PINCTRL_PIN(32, "MIO32"),
160 PINCTRL_PIN(33, "MIO33"),
161 PINCTRL_PIN(34, "MIO34"),
162 PINCTRL_PIN(35, "MIO35"),
163 PINCTRL_PIN(36, "MIO36"),
164 PINCTRL_PIN(37, "MIO37"),
165 PINCTRL_PIN(38, "MIO38"),
166 PINCTRL_PIN(39, "MIO39"),
167 PINCTRL_PIN(40, "MIO40"),
168 PINCTRL_PIN(41, "MIO41"),
169 PINCTRL_PIN(42, "MIO42"),
170 PINCTRL_PIN(43, "MIO43"),
171 PINCTRL_PIN(44, "MIO44"),
172 PINCTRL_PIN(45, "MIO45"),
173 PINCTRL_PIN(46, "MIO46"),
174 PINCTRL_PIN(47, "MIO47"),
175 PINCTRL_PIN(48, "MIO48"),
176 PINCTRL_PIN(49, "MIO49"),
177 PINCTRL_PIN(50, "MIO50"),
178 PINCTRL_PIN(51, "MIO51"),
179 PINCTRL_PIN(52, "MIO52"),
180 PINCTRL_PIN(53, "MIO53"),
181 PINCTRL_PIN(54, "EMIO_SD0_WP"),
182 PINCTRL_PIN(55, "EMIO_SD0_CD"),
183 PINCTRL_PIN(56, "EMIO_SD1_WP"),
184 PINCTRL_PIN(57, "EMIO_SD1_CD"),
185 };
186
187 /* pin groups */
188 static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
189 24, 25, 26, 27};
190 static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
191 36, 37, 38, 39};
192 static const unsigned int mdio0_0_pins[] = {52, 53};
193 static const unsigned int mdio1_0_pins[] = {52, 53};
194 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
195
196 static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
197 static const unsigned int qspi_cs1_pins[] = {0};
198 static const unsigned int qspi_fbclk_pins[] = {8};
199 static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21};
200 static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33};
201 static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45};
202 static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15};
203 static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27};
204 static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39};
205 static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51};
206 static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
207 static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
208 static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
209 static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
210 static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
211 static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
212 static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 40, 51};
213 static const unsigned int sdio0_emio_wp_pins[] = {54};
214 static const unsigned int sdio0_emio_cd_pins[] = {55};
215 static const unsigned int sdio1_emio_wp_pins[] = {56};
216 static const unsigned int sdio1_emio_cd_pins[] = {57};
217 static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
218 15, 16, 17, 18, 19, 20, 21, 22, 23,
219 24, 25, 26, 27, 28, 29, 30, 31, 32,
220 33, 34, 35, 36, 37, 38, 39};
221 static const unsigned int smc0_nor_cs1_pins[] = {1};
222 static const unsigned int smc0_nor_addr25_pins[] = {1};
223 static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
224 12, 13, 14, 16, 17, 18, 19, 20,
225 21, 22, 23};
226 /* Note: CAN MIO clock inputs are modeled in the clock framework */
227 static const unsigned int can0_0_pins[] = {10, 11};
228 static const unsigned int can0_1_pins[] = {14, 15};
229 static const unsigned int can0_2_pins[] = {18, 19};
230 static const unsigned int can0_3_pins[] = {22, 23};
231 static const unsigned int can0_4_pins[] = {26, 27};
232 static const unsigned int can0_5_pins[] = {30, 31};
233 static const unsigned int can0_6_pins[] = {34, 35};
234 static const unsigned int can0_7_pins[] = {38, 39};
235 static const unsigned int can0_8_pins[] = {42, 43};
236 static const unsigned int can0_9_pins[] = {46, 47};
237 static const unsigned int can0_10_pins[] = {50, 51};
238 static const unsigned int can1_0_pins[] = {8, 9};
239 static const unsigned int can1_1_pins[] = {12, 13};
240 static const unsigned int can1_2_pins[] = {16, 17};
241 static const unsigned int can1_3_pins[] = {20, 21};
242 static const unsigned int can1_4_pins[] = {24, 25};
243 static const unsigned int can1_5_pins[] = {28, 29};
244 static const unsigned int can1_6_pins[] = {32, 33};
245 static const unsigned int can1_7_pins[] = {36, 37};
246 static const unsigned int can1_8_pins[] = {40, 41};
247 static const unsigned int can1_9_pins[] = {44, 45};
248 static const unsigned int can1_10_pins[] = {48, 49};
249 static const unsigned int can1_11_pins[] = {52, 53};
250 static const unsigned int uart0_0_pins[] = {10, 11};
251 static const unsigned int uart0_1_pins[] = {14, 15};
252 static const unsigned int uart0_2_pins[] = {18, 19};
253 static const unsigned int uart0_3_pins[] = {22, 23};
254 static const unsigned int uart0_4_pins[] = {26, 27};
255 static const unsigned int uart0_5_pins[] = {30, 31};
256 static const unsigned int uart0_6_pins[] = {34, 35};
257 static const unsigned int uart0_7_pins[] = {38, 39};
258 static const unsigned int uart0_8_pins[] = {42, 43};
259 static const unsigned int uart0_9_pins[] = {46, 47};
260 static const unsigned int uart0_10_pins[] = {50, 51};
261 static const unsigned int uart1_0_pins[] = {8, 9};
262 static const unsigned int uart1_1_pins[] = {12, 13};
263 static const unsigned int uart1_2_pins[] = {16, 17};
264 static const unsigned int uart1_3_pins[] = {20, 21};
265 static const unsigned int uart1_4_pins[] = {24, 25};
266 static const unsigned int uart1_5_pins[] = {28, 29};
267 static const unsigned int uart1_6_pins[] = {32, 33};
268 static const unsigned int uart1_7_pins[] = {36, 37};
269 static const unsigned int uart1_8_pins[] = {40, 41};
270 static const unsigned int uart1_9_pins[] = {44, 45};
271 static const unsigned int uart1_10_pins[] = {48, 49};
272 static const unsigned int uart1_11_pins[] = {52, 53};
273 static const unsigned int i2c0_0_pins[] = {10, 11};
274 static const unsigned int i2c0_1_pins[] = {14, 15};
275 static const unsigned int i2c0_2_pins[] = {18, 19};
276 static const unsigned int i2c0_3_pins[] = {22, 23};
277 static const unsigned int i2c0_4_pins[] = {26, 27};
278 static const unsigned int i2c0_5_pins[] = {30, 31};
279 static const unsigned int i2c0_6_pins[] = {34, 35};
280 static const unsigned int i2c0_7_pins[] = {38, 39};
281 static const unsigned int i2c0_8_pins[] = {42, 43};
282 static const unsigned int i2c0_9_pins[] = {46, 47};
283 static const unsigned int i2c0_10_pins[] = {50, 51};
284 static const unsigned int i2c1_0_pins[] = {12, 13};
285 static const unsigned int i2c1_1_pins[] = {16, 17};
286 static const unsigned int i2c1_2_pins[] = {20, 21};
287 static const unsigned int i2c1_3_pins[] = {24, 25};
288 static const unsigned int i2c1_4_pins[] = {28, 29};
289 static const unsigned int i2c1_5_pins[] = {32, 33};
290 static const unsigned int i2c1_6_pins[] = {36, 37};
291 static const unsigned int i2c1_7_pins[] = {40, 41};
292 static const unsigned int i2c1_8_pins[] = {44, 45};
293 static const unsigned int i2c1_9_pins[] = {48, 49};
294 static const unsigned int i2c1_10_pins[] = {52, 53};
295 static const unsigned int ttc0_0_pins[] = {18, 19};
296 static const unsigned int ttc0_1_pins[] = {30, 31};
297 static const unsigned int ttc0_2_pins[] = {42, 43};
298 static const unsigned int ttc1_0_pins[] = {16, 17};
299 static const unsigned int ttc1_1_pins[] = {28, 29};
300 static const unsigned int ttc1_2_pins[] = {40, 41};
301 static const unsigned int swdt0_0_pins[] = {14, 15};
302 static const unsigned int swdt0_1_pins[] = {26, 27};
303 static const unsigned int swdt0_2_pins[] = {38, 39};
304 static const unsigned int swdt0_3_pins[] = {50, 51};
305 static const unsigned int swdt0_4_pins[] = {52, 53};
306 static const unsigned int gpio0_0_pins[] = {0};
307 static const unsigned int gpio0_1_pins[] = {1};
308 static const unsigned int gpio0_2_pins[] = {2};
309 static const unsigned int gpio0_3_pins[] = {3};
310 static const unsigned int gpio0_4_pins[] = {4};
311 static const unsigned int gpio0_5_pins[] = {5};
312 static const unsigned int gpio0_6_pins[] = {6};
313 static const unsigned int gpio0_7_pins[] = {7};
314 static const unsigned int gpio0_8_pins[] = {8};
315 static const unsigned int gpio0_9_pins[] = {9};
316 static const unsigned int gpio0_10_pins[] = {10};
317 static const unsigned int gpio0_11_pins[] = {11};
318 static const unsigned int gpio0_12_pins[] = {12};
319 static const unsigned int gpio0_13_pins[] = {13};
320 static const unsigned int gpio0_14_pins[] = {14};
321 static const unsigned int gpio0_15_pins[] = {15};
322 static const unsigned int gpio0_16_pins[] = {16};
323 static const unsigned int gpio0_17_pins[] = {17};
324 static const unsigned int gpio0_18_pins[] = {18};
325 static const unsigned int gpio0_19_pins[] = {19};
326 static const unsigned int gpio0_20_pins[] = {20};
327 static const unsigned int gpio0_21_pins[] = {21};
328 static const unsigned int gpio0_22_pins[] = {22};
329 static const unsigned int gpio0_23_pins[] = {23};
330 static const unsigned int gpio0_24_pins[] = {24};
331 static const unsigned int gpio0_25_pins[] = {25};
332 static const unsigned int gpio0_26_pins[] = {26};
333 static const unsigned int gpio0_27_pins[] = {27};
334 static const unsigned int gpio0_28_pins[] = {28};
335 static const unsigned int gpio0_29_pins[] = {29};
336 static const unsigned int gpio0_30_pins[] = {30};
337 static const unsigned int gpio0_31_pins[] = {31};
338 static const unsigned int gpio0_32_pins[] = {32};
339 static const unsigned int gpio0_33_pins[] = {33};
340 static const unsigned int gpio0_34_pins[] = {34};
341 static const unsigned int gpio0_35_pins[] = {35};
342 static const unsigned int gpio0_36_pins[] = {36};
343 static const unsigned int gpio0_37_pins[] = {37};
344 static const unsigned int gpio0_38_pins[] = {38};
345 static const unsigned int gpio0_39_pins[] = {39};
346 static const unsigned int gpio0_40_pins[] = {40};
347 static const unsigned int gpio0_41_pins[] = {41};
348 static const unsigned int gpio0_42_pins[] = {42};
349 static const unsigned int gpio0_43_pins[] = {43};
350 static const unsigned int gpio0_44_pins[] = {44};
351 static const unsigned int gpio0_45_pins[] = {45};
352 static const unsigned int gpio0_46_pins[] = {46};
353 static const unsigned int gpio0_47_pins[] = {47};
354 static const unsigned int gpio0_48_pins[] = {48};
355 static const unsigned int gpio0_49_pins[] = {49};
356 static const unsigned int gpio0_50_pins[] = {50};
357 static const unsigned int gpio0_51_pins[] = {51};
358 static const unsigned int gpio0_52_pins[] = {52};
359 static const unsigned int gpio0_53_pins[] = {53};
360 static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
361 37, 38, 39};
362 static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
363 49, 50, 51};
364
365 #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
366 { \
367 .name = #nm "_grp", \
368 .pins = nm ## _pins, \
369 .npins = ARRAY_SIZE(nm ## _pins), \
370 }
371
372 struct zynq_pctrl_group zynq_pctrl_groups[] = {
373 DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
374 DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
375 DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
376 DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
377 DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
378 DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
379 DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
380 DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
381 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
382 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
383 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
384 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
385 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
386 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
387 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
388 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
389 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
390 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
391 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
392 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
393 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
394 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
395 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
396 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
397 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
398 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
399 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
400 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
401 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
402 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
403 DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
404 DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
405 DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
406 DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
407 DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
408 DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
409 DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
410 DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
411 DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
412 DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
413 DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
414 DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
415 DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
416 DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
417 DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
418 DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
419 DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
420 DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
421 DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
422 DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
423 DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
424 DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
425 DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
426 DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
427 DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
428 DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
429 DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
430 DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
431 DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
432 DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
433 DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
434 DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
435 DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
436 DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
437 DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
438 DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
439 DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
440 DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
441 DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
442 DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
443 DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
444 DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
445 DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
446 DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
447 DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
448 DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
449 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
450 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
451 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
452 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
453 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
454 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
455 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
456 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
457 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
458 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
459 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
460 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
461 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
462 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
463 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
464 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
465 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
466 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
467 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
468 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
469 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
470 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
471 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
472 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
473 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
474 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
475 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
476 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
477 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
478 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
479 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
480 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
481 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
482 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
483 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
484 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
485 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
486 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
487 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
488 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
489 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
490 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
491 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
492 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
493 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
494 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
495 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
496 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
497 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
498 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
499 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
500 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
501 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
502 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
503 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
504 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
505 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
506 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
507 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
508 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
509 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
510 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
511 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
512 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
513 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
514 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
515 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
516 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
517 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
518 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
519 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
520 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
521 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
522 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
523 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
524 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
525 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
526 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
527 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
528 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
529 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
530 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
531 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
532 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
533 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
534 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
535 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
536 DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
537 DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
538 };
539
540 /* function groups */
541 static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
542 static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
543 static const char * const usb0_groups[] = {"usb0_0_grp"};
544 static const char * const usb1_groups[] = {"usb1_0_grp"};
545 static const char * const mdio0_groups[] = {"mdio0_0_grp"};
546 static const char * const mdio1_groups[] = {"mdio1_0_grp"};
547 static const char * const qspi0_groups[] = {"qspi0_0_grp"};
548 static const char * const qspi1_groups[] = {"qspi0_1_grp"};
549 static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
550 static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
551 static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
552 "spi0_2_grp"};
553 static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
554 "spi1_2_grp", "spi1_3_grp"};
555 static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
556 "sdio0_2_grp"};
557 static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
558 "sdio1_2_grp", "sdio1_3_grp"};
559 static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
560 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
561 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
562 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
563 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
564 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
565 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
566 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
567 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
568 "gpio0_50_grp", "gpio0_52_grp"};
569 static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
570 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
571 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
572 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
573 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
574 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
575 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
576 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
577 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
578 "gpio0_51_grp", "gpio0_53_grp"};
579 static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
580 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
581 "gpio0_10_grp", "gpio0_12_grp",
582 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
583 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
584 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
585 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
586 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
587 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
588 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
589 "gpio0_3_grp", "gpio0_5_grp",
590 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
591 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
592 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
593 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
594 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
595 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
596 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
597 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
598 static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
599 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
600 "gpio0_10_grp", "gpio0_12_grp",
601 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
602 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
603 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
604 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
605 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
606 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
607 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
608 "gpio0_3_grp", "gpio0_5_grp",
609 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
610 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
611 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
612 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
613 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
614 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
615 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
616 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
617 static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
618 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
619 "gpio0_10_grp", "gpio0_12_grp",
620 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
621 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
622 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
623 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
624 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
625 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
626 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
627 "gpio0_3_grp", "gpio0_5_grp",
628 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
629 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
630 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
631 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
632 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
633 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
634 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
635 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
636 static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
637 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
638 "gpio0_10_grp", "gpio0_12_grp",
639 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
640 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
641 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
642 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
643 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
644 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
645 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
646 "gpio0_3_grp", "gpio0_5_grp",
647 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
648 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
649 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
650 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
651 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
652 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
653 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
654 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
655 static const char * const smc0_nor_groups[] = {"smc0_nor"};
656 static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
657 static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
658 static const char * const smc0_nand_groups[] = {"smc0_nand"};
659 static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
660 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
661 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
662 "can0_10_grp"};
663 static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
664 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
665 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
666 "can1_10_grp", "can1_11_grp"};
667 static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
668 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
669 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
670 "uart0_10_grp"};
671 static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
672 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
673 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
674 "uart1_10_grp", "uart1_11_grp"};
675 static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
676 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
677 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
678 "i2c0_10_grp"};
679 static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
680 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
681 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
682 "i2c1_10_grp"};
683 static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
684 "ttc0_2_grp"};
685 static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
686 "ttc1_2_grp"};
687 static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
688 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
689 static const char * const gpio0_groups[] = {"gpio0_0_grp",
690 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
691 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
692 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
693 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
694 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
695 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
696 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
697 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
698 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
699 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
700 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
701 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
702 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
703 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
704 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
705 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
706 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
707 "gpio0_51_grp", "gpio0_53_grp"};
708
709 #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
710 [ZYNQ_PMUX_##fname] = { \
711 .name = #fname, \
712 .groups = fname##_groups, \
713 .ngroups = ARRAY_SIZE(fname##_groups), \
714 .mux_val = mval, \
715 }
716
717 #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
718 [ZYNQ_PMUX_##fname] = { \
719 .name = #fname, \
720 .groups = fname##_groups, \
721 .ngroups = ARRAY_SIZE(fname##_groups), \
722 .mux_val = mval, \
723 .mux = offset, \
724 .mux_mask = mask, \
725 .mux_shift = shift, \
726 }
727
728 #define ZYNQ_SDIO_WP_SHIFT 0
729 #define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
730 #define ZYNQ_SDIO_CD_SHIFT 16
731 #define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
732
733 static const struct zynq_pinmux_function zynq_pmux_functions[] = {
734 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
735 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
736 DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
737 DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
738 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
739 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
740 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
741 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
742 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
743 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
744 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
745 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
746 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
747 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
748 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
749 ZYNQ_SDIO_WP_SHIFT),
750 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
751 ZYNQ_SDIO_CD_SHIFT),
752 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
753 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
754 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
755 ZYNQ_SDIO_WP_SHIFT),
756 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
757 ZYNQ_SDIO_CD_SHIFT),
758 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
759 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
760 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
761 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
762 DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
763 DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
764 DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
765 DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
766 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
767 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
768 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
769 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
770 DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
771 DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
772 };
773
774
775 /* pinctrl */
776 static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
777 {
778 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
779
780 return pctrl->ngroups;
781 }
782
783 static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
784 unsigned selector)
785 {
786 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
787
788 return pctrl->groups[selector].name;
789 }
790
791 static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
792 unsigned selector,
793 const unsigned **pins,
794 unsigned *num_pins)
795 {
796 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
797
798 *pins = pctrl->groups[selector].pins;
799 *num_pins = pctrl->groups[selector].npins;
800
801 return 0;
802 }
803
804 static const struct pinctrl_ops zynq_pctrl_ops = {
805 .get_groups_count = zynq_pctrl_get_groups_count,
806 .get_group_name = zynq_pctrl_get_group_name,
807 .get_group_pins = zynq_pctrl_get_group_pins,
808 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
809 .dt_free_map = pinctrl_utils_dt_free_map,
810 };
811
812 /* pinmux */
813 static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
814 {
815 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
816
817 return pctrl->nfuncs;
818 }
819
820 static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
821 unsigned selector)
822 {
823 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
824
825 return pctrl->funcs[selector].name;
826 }
827
828 static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
829 unsigned selector,
830 const char * const **groups,
831 unsigned * const num_groups)
832 {
833 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
834
835 *groups = pctrl->funcs[selector].groups;
836 *num_groups = pctrl->funcs[selector].ngroups;
837 return 0;
838 }
839
840 static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
841 unsigned function,
842 unsigned group)
843 {
844 int i, ret;
845 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
846 const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
847 const struct zynq_pinmux_function *func = &pctrl->funcs[function];
848
849 /*
850 * SD WP & CD are special. They have dedicated registers
851 * to mux them in
852 */
853 if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
854 function == ZYNQ_PMUX_sdio1_cd ||
855 function == ZYNQ_PMUX_sdio1_wp) {
856 u32 reg;
857
858 ret = regmap_read(pctrl->syscon,
859 pctrl->pctrl_offset + func->mux, &reg);
860 if (ret)
861 return ret;
862
863 reg &= ~func->mux_mask;
864 reg |= pgrp->pins[0] << func->mux_shift;
865 ret = regmap_write(pctrl->syscon,
866 pctrl->pctrl_offset + func->mux, reg);
867 if (ret)
868 return ret;
869 } else {
870 for (i = 0; i < pgrp->npins; i++) {
871 unsigned int pin = pgrp->pins[i];
872 u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
873
874 ret = regmap_read(pctrl->syscon, addr, &reg);
875 if (ret)
876 return ret;
877
878 reg &= ~ZYNQ_PINMUX_MUX_MASK;
879 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
880 ret = regmap_write(pctrl->syscon, addr, reg);
881 if (ret)
882 return ret;
883 }
884 }
885
886 return 0;
887 }
888
889 static const struct pinmux_ops zynq_pinmux_ops = {
890 .get_functions_count = zynq_pmux_get_functions_count,
891 .get_function_name = zynq_pmux_get_function_name,
892 .get_function_groups = zynq_pmux_get_function_groups,
893 .set_mux = zynq_pinmux_set_mux,
894 };
895
896 /* pinconfig */
897 #define ZYNQ_PINCONF_TRISTATE BIT(0)
898 #define ZYNQ_PINCONF_SPEED BIT(8)
899 #define ZYNQ_PINCONF_PULLUP BIT(12)
900 #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
901
902 #define ZYNQ_PINCONF_IOTYPE_SHIFT 9
903 #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
904
905 enum zynq_io_standards {
906 zynq_iostd_min,
907 zynq_iostd_lvcmos18,
908 zynq_iostd_lvcmos25,
909 zynq_iostd_lvcmos33,
910 zynq_iostd_hstl,
911 zynq_iostd_max
912 };
913
914 /**
915 * enum zynq_pin_config_param - possible pin configuration parameters
916 * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
917 * this parameter (on a custom format) tells the driver which alternative
918 * IO standard to use.
919 */
920 enum zynq_pin_config_param {
921 PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1,
922 };
923
924 static const struct pinconf_generic_params zynq_dt_params[] = {
925 {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
926 };
927
928 #ifdef CONFIG_DEBUG_FS
929 static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] = {
930 PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
931 };
932 #endif
933
934 static unsigned int zynq_pinconf_iostd_get(u32 reg)
935 {
936 return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
937 }
938
939 static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
940 unsigned pin,
941 unsigned long *config)
942 {
943 u32 reg;
944 int ret;
945 unsigned int arg = 0;
946 unsigned int param = pinconf_to_config_param(*config);
947 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
948
949 if (pin >= ZYNQ_NUM_MIOS)
950 return -ENOTSUPP;
951
952 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
953 if (ret)
954 return -EIO;
955
956 switch (param) {
957 case PIN_CONFIG_BIAS_PULL_UP:
958 if (!(reg & ZYNQ_PINCONF_PULLUP))
959 return -EINVAL;
960 arg = 1;
961 break;
962 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
963 if (!(reg & ZYNQ_PINCONF_TRISTATE))
964 return -EINVAL;
965 arg = 1;
966 break;
967 case PIN_CONFIG_BIAS_DISABLE:
968 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
969 return -EINVAL;
970 break;
971 case PIN_CONFIG_SLEW_RATE:
972 arg = !!(reg & ZYNQ_PINCONF_SPEED);
973 break;
974 case PIN_CONFIG_LOW_POWER_MODE:
975 {
976 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
977
978 if (iostd != zynq_iostd_hstl)
979 return -EINVAL;
980 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
981 return -EINVAL;
982 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
983 break;
984 }
985 case PIN_CONFIG_IOSTANDARD:
986 arg = zynq_pinconf_iostd_get(reg);
987 break;
988 default:
989 return -ENOTSUPP;
990 }
991
992 *config = pinconf_to_config_packed(param, arg);
993 return 0;
994 }
995
996 static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
997 unsigned pin,
998 unsigned long *configs,
999 unsigned num_configs)
1000 {
1001 int i, ret;
1002 u32 reg;
1003 u32 pullup = 0;
1004 u32 tristate = 0;
1005 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1006
1007 if (pin >= ZYNQ_NUM_MIOS)
1008 return -ENOTSUPP;
1009
1010 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
1011 if (ret)
1012 return -EIO;
1013
1014 for (i = 0; i < num_configs; i++) {
1015 unsigned int param = pinconf_to_config_param(configs[i]);
1016 unsigned int arg = pinconf_to_config_argument(configs[i]);
1017
1018 switch (param) {
1019 case PIN_CONFIG_BIAS_PULL_UP:
1020 pullup = ZYNQ_PINCONF_PULLUP;
1021 break;
1022 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1023 tristate = ZYNQ_PINCONF_TRISTATE;
1024 break;
1025 case PIN_CONFIG_BIAS_DISABLE:
1026 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1027 break;
1028 case PIN_CONFIG_SLEW_RATE:
1029 if (arg)
1030 reg |= ZYNQ_PINCONF_SPEED;
1031 else
1032 reg &= ~ZYNQ_PINCONF_SPEED;
1033
1034 break;
1035 case PIN_CONFIG_IOSTANDARD:
1036 if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
1037 dev_warn(pctldev->dev,
1038 "unsupported IO standard '%u'\n",
1039 param);
1040 break;
1041 }
1042 reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
1043 reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
1044 break;
1045 case PIN_CONFIG_LOW_POWER_MODE:
1046 if (arg)
1047 reg |= ZYNQ_PINCONF_DISABLE_RECVR;
1048 else
1049 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
1050
1051 break;
1052 default:
1053 dev_warn(pctldev->dev,
1054 "unsupported configuration parameter '%u'\n",
1055 param);
1056 continue;
1057 }
1058 }
1059
1060 if (tristate || pullup) {
1061 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1062 reg |= tristate | pullup;
1063 }
1064
1065 ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
1066 if (ret)
1067 return -EIO;
1068
1069 return 0;
1070 }
1071
1072 static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
1073 unsigned selector,
1074 unsigned long *configs,
1075 unsigned num_configs)
1076 {
1077 int i, ret;
1078 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1079 const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
1080
1081 for (i = 0; i < pgrp->npins; i++) {
1082 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1083 num_configs);
1084 if (ret)
1085 return ret;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static const struct pinconf_ops zynq_pinconf_ops = {
1092 .is_generic = true,
1093 .pin_config_get = zynq_pinconf_cfg_get,
1094 .pin_config_set = zynq_pinconf_cfg_set,
1095 .pin_config_group_set = zynq_pinconf_group_set,
1096 };
1097
1098 static struct pinctrl_desc zynq_desc = {
1099 .name = "zynq_pinctrl",
1100 .pins = zynq_pins,
1101 .npins = ARRAY_SIZE(zynq_pins),
1102 .pctlops = &zynq_pctrl_ops,
1103 .pmxops = &zynq_pinmux_ops,
1104 .confops = &zynq_pinconf_ops,
1105 .num_custom_params = ARRAY_SIZE(zynq_dt_params),
1106 .custom_params = zynq_dt_params,
1107 #ifdef CONFIG_DEBUG_FS
1108 .custom_conf_items = zynq_conf_items,
1109 #endif
1110 .owner = THIS_MODULE,
1111 };
1112
1113 static int zynq_pinctrl_probe(struct platform_device *pdev)
1114
1115 {
1116 struct resource *res;
1117 struct zynq_pinctrl *pctrl;
1118
1119 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1120 if (!pctrl)
1121 return -ENOMEM;
1122
1123 pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1124 "syscon");
1125 if (IS_ERR(pctrl->syscon)) {
1126 dev_err(&pdev->dev, "unable to get syscon\n");
1127 return PTR_ERR(pctrl->syscon);
1128 }
1129
1130 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1131 if (!res) {
1132 dev_err(&pdev->dev, "missing IO resource\n");
1133 return -ENODEV;
1134 }
1135 pctrl->pctrl_offset = res->start;
1136
1137 pctrl->groups = zynq_pctrl_groups;
1138 pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
1139 pctrl->funcs = zynq_pmux_functions;
1140 pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
1141
1142 pctrl->pctrl = pinctrl_register(&zynq_desc, &pdev->dev, pctrl);
1143 if (!pctrl->pctrl)
1144 return -ENOMEM;
1145
1146 platform_set_drvdata(pdev, pctrl);
1147
1148 dev_info(&pdev->dev, "zynq pinctrl initialized\n");
1149
1150 return 0;
1151 }
1152
1153 int zynq_pinctrl_remove(struct platform_device *pdev)
1154 {
1155 struct zynq_pinctrl *pctrl = platform_get_drvdata(pdev);
1156
1157 pinctrl_unregister(pctrl->pctrl);
1158
1159 return 0;
1160 }
1161
1162 static const struct of_device_id zynq_pinctrl_of_match[] = {
1163 { .compatible = "xlnx,pinctrl-zynq" },
1164 { }
1165 };
1166 MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match);
1167
1168 static struct platform_driver zynq_pinctrl_driver = {
1169 .driver = {
1170 .name = "zynq-pinctrl",
1171 .of_match_table = zynq_pinctrl_of_match,
1172 },
1173 .probe = zynq_pinctrl_probe,
1174 .remove = zynq_pinctrl_remove,
1175 };
1176
1177 module_platform_driver(zynq_pinctrl_driver);
1178
1179 MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>");
1180 MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver");
1181 MODULE_LICENSE("GPL");
Linux with added FPC-III support